Wafer Thinning and Thru-Silicon Vias The Path to Wafer Level Packaging jreche@trusi.com
Summary A new dry etching technology Atmospheric Downstream Plasma (ADP) Etch Applications to Packaging Wafer Thinning Cavity Etch 3-D Packaging Vias through Silicon Wafers All Silicon Die Packages Wafer Level Packaging
Wafer Thinning Requirements Wafer fab processing thickness 200mm diameter = 725 µm 300mm diameter = 810 µm Wafer thickness for packaging Year 2000 = 250-400 µm Year 2002 = 100-200 µm Max Die Size Year 2000 = 20 x 20mm Year 2002 = 40 x 40mm
ADP System
ADP Simplifies Wafer Thinning No Device Protection Needed No Resist or Tape Application and removal No Defect Removal by Wet Etch 2-5 micron etch No Chemical Difficulties Handling Disposal Lower Chemical Cost
Schematic Plasma Source
Plasma Source
No-Touch Wafer Holding No contact between wafer and holder Wafer Temperature adjustable between 160 and 300 ºC Allows wafers bumped with eutectic Sn/Pb to be thinned without protective coating Thin flexible wafers held flat during processing
Grinding Marks Removal
Silicon Crystal Orientations
Silicon Surface Etched by ADP
Wafer Edge ADP Smoothing
Before ADP After ADP
Damage Free Dicing Controlled Depth Dicing Apply tape on front side (over dicing) Grind back of wafer ADP etch on back of the wafer to singulate dies
SEM Damage Free Dicing Sawed die shows edge chipping ADP singulated die has rounded and smooth edges
Damage Free Dicing Benefits: Rounded edges and corners Mechanical Strength High Reliability during Temperature shock and cycling Ultra-thin die capability 20µm dies demonstrated Smooth edge helps pick-and-place
Stacked Dies in <1mm packages Ultra-thin packages strictly Japanese phenomena in the early 90s New US adoption of: Smart cards Memory cards Stacked dies desirable: Reduce loop height Minimize footprint
Stacked Wire Bonded Dies
Why 3-D Packages and Wafer Stacking? Electrical performance: Reduced interconnection length. Short connections is the most effective method to improve system speed. Gang processing: Lower labor cost Familiar wafer fab equipment Improved reliability:
The number of transistors double every 2nd year
Die area doubles every 5.5 years Lineal side dimension doubles every 11 years
System Bandwidth Limits Performance Chip Clock rates: Much faster than board level Determined by semiconductor architecture Interconnect length << wavelength Bus clock rates: High Speed outside chip requires transmission lines Parallel operation necessary 100 MHz bus clock --> 763 MBs on 32 bit bus
Array of vias (backside of wafer)
Test Substrate Layout - GDSII plot
Thru-Si Test Substrate
Interconnect Bump
What makes through Silicon vias tick?
Via Etch Masking
ADP Via Etch
ADP Via Etch (continued)
ADP Back Etch of via
Stackable Via
Tru-CSP face-to-face ICs
Stacked Chips: Tru-CSP
3-D Wafer Level Packaging
ADP Etch Aluminum Mask
Early Stage of ADP Via Etch
Via Hemispherical Shape
Wet Etched Via
Work in Progress Anisotropic Etching Model to predict shape of cavities Reliability Thermal Through the Silicon vias Thin Silicon Electrical Performance RLC characterization Model for CAD insertion
Summary of 3-D Development Short term goals: Bumped wafers All Silicon package Tiled wafers Wafer level packaging Long Term goals: 3-D Wafer Level Packaging Stacked dies Wafer level