DESIGN FOR TESTABILITY Raimund Ubar raiub@pld.ttu.ee
Design for Testability Lectures Testability of Digital Systems Design for Testability Methods BIST/BISD Practical Works Two laboratory works Course work Exam
Literature L.-T.Wang, C.-W.Wu, X.Wen. VLSI Test Principles and Architectures. Elsevier, 2006, 777 p. O.Novak, E.Gramatova, R.Ubar. Handbook of Testing Electronic Systems. Czech TU Publishing House, 2005, 395 p. A.Miczo. Digital Logic Testing and Simulation. Wiley-Interscience, New Yersey, 2003, 668 p. N.Jha, S.Gupta. Testing of Digital Systems. Cambridge Univ. Press, 2003, 1000 p. R.Ubar, J.Raik, Th.Vierhaus. IGI Global, Hershey New York, 2011, 550 p.
Literature Other: H.-J.Wunderlich, Ed. Models in Hardware Testing. Springer, 2010. M.Gössel, E.Sogomonjan et. al. New Methods of Concurrent Checking. Springer, 2008. D.Gizopulos. Advances in Electronic Testing, Technology & Engineering. Springer, 2006. D.Gizopulos, A.Paschalis, Y.Zorian. Embedded Processor-Based Self-Test. Kluwer Acad. Publishers, 2004.
Raimund Ubar Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus Why the topic of DFT is important? We depend too much on computers and on the technical systems controlled by computers Tiina Ubar 5
Raimund Ubar Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus Computers and Embedded Systems Universal computers 2% Embedded systems 98% 98 % Microprocessor market shares We notice our dependency on electronics only when it suddenly gives up to work 6
Raimund Ubar Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus Why the topic of DFT is important? To understand the difference between design and design for test Design is the field of direct problems Design for Test - is the field of reverse problems The central question of the diagnosis and DFT is WHY? This is the general question of every creative engineer at all How? is technical question and problem 7
Goals of the DFT Course To give the basic knowledge: How to improve test quality at increasing complexities of systems? This knowledges includes understanding of how the physical defects can influence on the behavior of systems, and what is diagnostic modelling learning fault simulation, test generation and fault diagnosis understanding the meaning of testability learning the basic methods of making systems self-testable The goal is also to give some hands-on experience of solving test related problems 8
Raimund Ubar Research in ATI Practical Importance of testability? To improve the manufacturing processes and to increase the yield To design reliable systems out of not reliable components which leads to the need of fault-tolerance Field diagnosis as the traditional task The Rule of Ten is the Sword of Damokles The increasing complexity of VLSI circuits has made test and diagnosis the most complicated problems in digital design Automated diagnosis is needed 9
Raimund Ubar Research in ATI Position of the DFT Field Dependability Reliability Security Safety There is no sequrity on the earth, there is only oportunity Douglas McArthur (General) Design for testability: Test Diagnosis Test Fault Diagnosis BIST/BISD Built-In Self-Test/Diagnosis Fault-Tolerance Dependability Self-Repair
Raimund Ubar Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus Terminology: Verification, Validation, Testing Validation VLSI Design Flow Specification Hardware description languages (VHDL) Implementation VLSI Design, System on Chip Manufacturing CMOS Verification Testing Verification is to check the consistence between the individual development phases Validation is checking the system whether it conforms to the user requirements
Introduction: Testing World Test experiment (BIST) System Test result Fault simulation Fault diagnosis Test System model Fault dictionary Test generation Go/No go Located defect Test tools
Raimund Ubar What is a test? Testprogram 12 + 10 =? How many test patterns are needed to test an adder? Processor Diagnosis 22 Test results 13
Raimund Ubar Testing of adder? 32 bit adder has 64 inputs The number of all possibile test patterns is 2 64 = 18 446 744 073 709 551 616 10 19 10011011 11010010 1 GHz processor will need 2 64 = 18 446 700 000 10 10 sec or 584 years Adder Mikroprocessor in the factory is tested only with 10 sec How about the quality of test in this case? 14
... Raimund Ubar Functional view on fault coverage Why we need 2 64 patterns 1 2 64 Fault coverage 100% Number of patterns Test quality: First pattern 100% 0% 93,75% 4. 3. Second pattern 87,5% 75% 50% 15
Raimund Ubar Structural view on fault coverage Testing of structural faults: 1 2 n Combinational circuit under test Not yet tested faults 2. pattern 4. pat. Fault coverage Fault Faults covered by 1. pattern 3. pat. 100% Number of patterns 4 16
Raimund Ubar Comparison of Two Approaches for Testing Testing of functions: 100% 0% 93,75% 4. pat. 87,5% Testing of faults: Not tested faults 3. patttern 4. pat. 2. pattern 100% will be reached only after 2 n test patterns Faulty functions covered by 1. pattern 50% 3. pattern Faulty functions covered by 2. pattern 75% Testing of faults 100% Testing of functions Faults covered by 1. pattern 100% will be reached when all faults from the fault list are covered 17
Raimund Ubar Why the topic of DFT is important? The main property of today s systems is COMPLEXITY To manage the complexity we have to know methods like: - abstraction - modeling - simulation - hierarchical divide and conquer -... 18
Raimund Ubar Fault Model Based Test Generation: Problems Test signals Testing of complex system: Component under test Example: 32-bit adder x 1 y Observable point Functional test: Number of test patterns N = 2 64 = 10 19 x n Activated blocks (sub-systems) Additionally activated blocks may disturb the test process Structural test: Alltogether about 2000 faults Number of test patterns: N << 2000 << 10 19 19
Hierarchy: Divide and Conquer Engineer vs. computer: To generate a test for a component in a system, the computer needed 2 days and 2 nights Sea of gates The best place to start is with a good title. Then build a song around it. (Wisdom of country music) An engineer did it by hand with 15 minutes So, why computers? Sequence of 2 16 bits 16 bit counter 1 & System Design for Testability
011001 Raimund Ubar Test generation process for detecting a fault: Why Design for Testability? Defect? Know-how Expert systems were used in Europe but not in US Expert system is needed to help the test programmer 21
011001 Raimund Ubar Test generation process for detecting a fault: Why Design for Testability? Defekt Gordion Knot? Hard-to-testpart New paradigm ScanPath Design 011001 22 mindmappingsoftwareblog.com
Making Systems Transparent IN Combinational circuit OUT q R q theisleofwightcomputergeek.co.uk IN Combinational circuit OUT Scan-Path design strategy Scan-IN q R q Scan-OUT 23
Boundary Scan Standard
Design for Testability To ways for improving testability with inserting of control points: Improving controllability System under test Improving observability Control points 25
Introduction: Ad Hoc Design for Testability Method of Test Points: Block 1 Block 2 Improving controllability and observability: Block 1 Block 2 1 OP CP OP Block 1 Block 2 CP & Block 1 is not observable, Block 2 is not controllable 1- controllability: CP = 0 - normal working mode CP = 1 - controlling Block 2 with signal 1 0- controllability: CP = 1 - normal working mode CP = 0 - controlling Block 2 with signal 0
Amusing testability: Introduction: Tradeoffs Theorem: You can test an arbitrary digital system by only 3 test patterns if you design it approprietly Proof: 011 101 & 011 001 & 101 001? & 011 101 & 001 011 1 010 & 101 001 General Solution? System Scan-Path FSM CC NAND
Introduction: Built-in Self-Test Cores have to be tested on chip Source: Elcoteq Source: Intel Copyright 2010 Raimund Ubar 28
Introduction: Self-Test in Digital Systems Source SoC SoC Test Access Mechanism SRAM CPU MPEG Peripheral Component Interconnect Wrapper Core Under Test UDL SRAM ROM DRAM Test Access Mechanism Sink Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution need for external ATE Combined solution mostly on-chip, ATE needed for control On-chip solution BIST
Introduction: What is BIST On circuit Test pattern generation Response verification Random pattern generation, very long tests Response compression IC BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Test Response Analysis (TRA)
Introduction: SoC BIST Optimization: Embedded Tester Test Controller Core 1 BIST Test access mechanism - testing time - memory Core 2 cost - power consumption - hardware BIST cost - test quality Tester Memory BIST BIST BIST Core 3 Core 4 Core 5 System on Chip
Introduction: BIST Embedding Example LFSR1 LFSR2 M1 M2 CSTP M4 MUX M5 M3 BILBO Concurrent testing: MISR1 LFSR, CSTP M2 MISR1 M2 M5 MISR2 (Functional BIST) CSTP M3 CSTP LFSR2 M4 BILBO MUX MISR2 M6
Course Work. Investigations of BIST Design of a circuit Evaluation of the testability of the circuit Redesign for testability Control points selection, optimization Scan path, optimization Built-in self-test. Design of solutions Experimental research
Course Work. Introduction In-circuit Test pattern generation Response verification Pseudorandom test generation, very long tests Hybrid test solutions Response compression IC BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Test Response Analysis (TRA)
Course Work. Description of the Circuit Test Generator - LFSR 4 A B C x z k 1, k 2 1. Design of a combinational circuit for the following functionality If x = 0, z = 0, then Y = k 1 A + k 2 B, else k 3, k 1 k 1, k 2, k 3 k 4, k 5, MUX if x = 0, z = 1, then Y = k 3 A - k 1 C, else if x = 1, z = 0, then Y = (k 1 A k 1 B k 2 C) (k 3 C NOT (k 3 A) k 1 B), k 6 4 Y else if x = 1, z = 1, then Y = k 4 A 2 + k 5 A + k 6 Signature Analyzer Interface Coefficients k i can be found on the next slide
Coefficients for the Course Work Versions Vers. No. k 1 k 2 k 3 k 4 k 5 k 6 Vers no. k 1 k 2 k 3 k 4 k 5 k 6 1 1 1 1 0,1 0,2 0,5 8 1 1 1 1,5 0,1 0,5 2 1 1 0 0,1 0,2 1,0 9 1 1 0 1,5 0,1 1,0 3 1 0 1 0,1 0,2 2,0 10 1 0 1 1,5 0,4 2,0 4 1 0 0 0,1 0,2 3,0 11 1 0 0 1,5 0,4 3,0 5 0 1 1 0,1 1,0 0,5 12 0 1 1 1,5 0,8 0,5 6 0 1 0 0,1 1,0 1,0 13 0 1 0 1,5 0,8 1,0 7 0 0 1 0,1 2,0 2,0 14 0 0 1 1,5 1,5 2,0
Course Work. Design of Interface Versions 4 Test Generator - LFSR A B C x z 2. Use three different interface versions for experiments: 1 bit, 2-bit and 4- or more bit interfaces for respective n-bit Signature Analyzers k 1, k 2 k 3, k 1 k 1, k 2, k 3 MUX The types of interface: Y 2 Y 2 4 Y k 4, k 5, k 6 1) 2) 3) n bit SA 4 Y Interface 1 bit SA 2 bit SA Signature Analyzer
Course Work. Design of a Testable Circuit 3. Enter the designed gate-level (AND, OR, NOT) combinational circuit into the computer, using CADENCE circuit editor 4. Generate test patterns with Turbo-Tester (TT) ATPG. If the fault coverage is 100%, remove one or more patterns from the test set, so that at least two faults remain undetected. 5. Improve the testability of the circuit to reach again 100% fault coverage with the updated test set Block 1 Block 2 CP 1 OP 1- controllability: CP = 0 - normal working mode CP = 1 - controlling Block 2 with signal 1
Course Work. Observability Investigation 6. Analyze two different testability improvement solutions: - Separate pins for all observability points - Single joint pin for all observability points Draw the graphics for both cases for the function P = f(t) where P is fault coverage, and T is test length
Course Work. Design of a Test Generator BILBO - Built- In Logic Block Observer: LFSR - Test Pattern Generator Combinational circuit 7. Generate test patterns by the BILBO tool for 10 different polynomials, and find the best structure for the LFSR Report for all 10 experiments the maximum achievable fault coverage, and fix the minimum test length needed for that Calculate the increase of the circuit size (in number of 2-input gates) due to adding of the self-test circuitry LFSR - Signature analyzer
Course Work. Design of a Test Generator CSTP - Circular Self-Test Path: LFSR - Test Pattern Generator & Signature analyser 8. Repeat the previous task for the case of using CSTP ("Circular Self Test Path") for self-test purposes Combinational circuit
Course Work. Design of a Signature Analyzer Test Generator - LFSR 4 A B C x z 1) 4 Y 9. Carry out experiments with the best test set found in task 7 for 4 different Signature Analyzers: 1-bit, 2-bit, 4- bit, and 8-bit k 1, k 2 1 bit SA Calculate the fault coverages k 3, k 1 k 1, k 2, k 3 k 4, k 5, MUX 2) 2 Y 2 Draw the graphic P = f(sa), where P is the fault coverage and SA is the number of bits in the Signature Analyzer k 6 4 Y Interface 3) 2 bit SA 4 Y n bit SA Draw 4 graphics P = f(t), for 4 SA cases, where T is the test length 5, 10, 15, 20 etc. up to P = 100% Explain the graphics Signature Analyzer
Course Work. Store-and-Generate BIST Fault Coverage The main motivations of using random patterns are: - low generation cost - high initial efeciency Problem: low fault coverage Long PR test: Hard to test faults Using many seeds: Pseudorandom test: 0 2 n -1 Pseudorandom test: 0 2 n -1 Time
Course Work. Store-and-Generate BIST 10. Synthesize an optimal BIST, using "store & generate architecture. Chose for that the best BILBO structure and ja the 100% test with length N. Minimize the number of seeds to be stored in the memory ROM TPG UUT ADR RD Counter 2 Counter 1 CL 11. Compare the results in tasks 4, 5, 7, 8 and 10. Which solution is the best and why? Draw the block-level final structure of the selected best BIST solution. 12. Present a report of the course work.