Analysis of Different Pseudo Noise Sequences

Similar documents
Pseudo noise sequences

WATERMARKING USING DECIMAL SEQUENCES. Navneet Mandhani and Subhash Kak

ARM7 Microcontroller Based Digital PRBS Generator

LFSRs as Functional Blocks in Wireless Applications Author: Stephen Lim and Andy Miller

Guidance For Scrambling Data Signals For EMC Compliance

FPGA IMPLEMENTATION AN ALGORITHM TO ESTIMATE THE PROXIMITY OF A MOVING TARGET

Individual Project Report

TERRESTRIAL broadcasting of digital television (DTV)

CS150 Fall 2012 Solutions to Homework 4

A Pseudorandom Binary Generator Based on Chaotic Linear Feedback Shift Register

Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20

MODULE 3. Combinational & Sequential logic

CSE 352 Laboratory Assignment 3

Scanned by CamScanner

Design for Test. Design for test (DFT) refers to those design techniques that make test generation and test application cost-effective.

True Random Number Generation with Logic Gates Only

A NOTE ON FRAME SYNCHRONIZATION SEQUENCES

The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of

Asynchronous (Ripple) Counters

Understanding Cryptography A Textbook for Students and Practitioners by Christof Paar and Jan Pelzl. Chapter 2 Stream Ciphers ver.

LFSR Counter Implementation in CMOS VLSI

INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY

Understanding Cryptography A Textbook for Students and Practitioners by Christof Paar and Jan Pelzl. Chapter 2 Stream Ciphers ver.

AIM: To study and verify the truth table of logic gates

Design and Implementation of Data Scrambler & Descrambler System Using VHDL

Implementation of CRC and Viterbi algorithm on FPGA

Chapter 3 Unit Combinational

Long and Fast Up/Down Counters Pushpinder Kaur CHOUHAN 6 th Jan, 2003

AC103/AT103 ANALOG & DIGITAL ELECTRONICS JUN 2015

Optimization of Multi-Channel BCH Error Decoding for Common Cases. Russell Dill Master's Thesis Defense April 20, 2015

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053

CHAPTER 4: Logic Circuits

IN DIGITAL transmission systems, there are always scramblers

REPEAT EXAMINATIONS 2002

Analogue Versus Digital [5 M]

Design of BIST with Low Power Test Pattern Generator

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters

A Novel Turbo Codec Encoding and Decoding Mechanism

Implementation of a turbo codes test bed in the Simulink environment

Chapter 6 Registers and Counters

Logic Design. Flip Flops, Registers and Counters

Efficient Architecture for Flexible Prescaler Using Multimodulo Prescaler

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS

Sequences and Cryptography

Chapter Contents. Appendix A: Digital Logic. Some Definitions

FPGA Implementation of Convolutional Encoder And Hard Decision Viterbi Decoder

VLSI Technology used in Auto-Scan Delay Testing Design For Bench Mark Circuits

1. Convert the decimal number to binary, octal, and hexadecimal.

A High- Speed LFSR Design by the Application of Sample Period Reduction Technique for BCH Encoder

Flip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari

Randomness analysis of A5/1 Stream Cipher for secure mobile communication

DESIGN and IMPLETATION of KEYSTREAM GENERATOR with IMPROVED SECURITY

CHAPTER 4: Logic Circuits

Principles of Computer Architecture. Appendix A: Digital Logic

Bit-Serial Test Pattern Generation by an Accumulator behaving as a Non-Linear Feedback Shift Register

CprE 281: Digital Logic

[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,

(Refer Slide Time: 2:03)

VeriLab. An introductory lab for using Verilog in digital design (first draft) VeriLab

UNIVERSITI TEKNOLOGI MALAYSIA

BISHOP ANSTEY HIGH SCHOOL & TRINITY COLLEGE EAST SIXTH FORM CXC CAPE PHYSICS, UNIT 2 Ms. S. S. CALBIO NOTES lesson #39

THE USE OF forward error correction (FEC) in optical networks

Chapter 4. Logic Design

DESIGN OF LOW POWER TEST PATTERN GENERATOR

(12) Patent Application Publication (10) Pub. No.: US 2003/ A1

Counter dan Register

Logic Design II (17.342) Spring Lecture Outline

TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic

QUICK GUIDE COMPUTER LOGICAL ORGANIZATION - OVERVIEW

Sequential Digital Design. Laboratory Manual. Experiment #7. Counters

On the design of turbo codes with convolutional interleavers

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012

International Journal of Scientific & Engineering Research, Volume 6, Issue 3, March-2015 ISSN DESIGN OF MB-OFDM SYSTEM USING HDL

Registers and Counters

Comparative Analysis of Stein s. and Euclid s Algorithm with BIST for GCD Computations. 1. Introduction

SRAM Based Random Number Generator For Non-Repeating Pattern Generation

Dynamic Power Reduction in Sequential Circuits Using Look Ahead Clock Gating Technique R. Manjith, C. Muthukumari

Logic Design Viva Question Bank Compiled By Channveer Patil

Digital Fundamentals: A Systems Approach

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \

Chapter 2. Digital Circuits

Implementation of BIST Test Generation Scheme based on Single and Programmable Twisted Ring Counters

MC9211 Computer Organization

WG Stream Cipher based Encryption Algorithm

Application of Symbol Avoidance in Reed-Solomon Codes to Improve their Synchronization

Figure 30.1a Timing diagram of the divide by 60 minutes/seconds counter

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

Microprocessor Design

Counters

Area-efficient high-throughput parallel scramblers using generalized algorithms

VLSI System Testing. BIST Motivation

MUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL

Electrical and Telecommunications Engineering Technology_TCET3122/TC520. NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York

Computer Architecture and Organization

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)

Vignana Bharathi Institute of Technology UNIT 4 DLD

Transcription:

Analysis of Different Pseudo Noise Sequences Alka Sawlikar, Manisha Sharma Abstract Pseudo noise (PN) sequences are widely used in digital communications and the theory involved has been treated extensively in this paper. This paper analyses some interesting properties of PN sequence. This paper further elaborates about various methods of generation of PN sequences, few methods discussed in this paper are: series-parallel method for high-speed generation, avoiding the zero states, shift registers with feedback, chaotic pattern generation. A detailed comparison of PN sequence and chaotic sequence is also described in this along with comparative analysis of LFSRs, Gold sequence, Barker sequence, Kasami sequence. Index Terms Spread spectrum, pseudo-noise, Chaos, LFSR, Code division multiple access, pseudo-noise codes, Maximal length, Gold, Barker, Kasami, autocorrelation, cross correlation. I. INTRODUCTION Pseudo random binary sequences (PRBSs), also known as pseudo noise (PN), linear feedback shift register (LFSR) sequences or maximal length binary sequences (m sequences), are widely used in digital communications, instrumentation and measurements [Lathi(998)]. In a truly random sequence the bit pattern never repeats. A pseudo random binary sequence is a semi-random sequence in the sense that it appears random within the sequence length, fulfilling the needs of randomness, but the entire sequence repeats indefinitely. To a casual observer the sequence appears totally random, however to a user who is aware of the way the sequence is generated all its properties should be known. PN sequences have several interesting properties, which are exploited in a variety of applications. Because of their good autocorrelation two similar PN sequences can easily be phase synchronized, even when one of them is corrupted by noise. A PN sequence is an ideal test signal, as it simulates the random characteristics of a digital signal and can be easily generated. The following fig. shows the overview of PN sequence. II. PROPERTIES OF PN SEQUENCES A PN sequence is a bit stream of s and 0 s occurring randomly, with some unique properties. The sequence serves as a reference pattern with known random characteristics for the analysis, optimization and performance measurement of communication channels and systems. A. Balance Property In each period of a maximum length sequence, the number of s is always one more than the number of 0s. B. Run Property Among the runs of s and 0s in each period of a maximum length sequence, one half the runs of each kind are of length one-fourth are of length two, one eighth are of length three, and so on as long as these fractions represent meaningful numbers of runs[hykin(200)]. C. Correlation Property Correlation is a measure of similarity between two sequences. When the two sequences compared are different it is the cross correlation and when they are the same it is the autocorrelation. Mathematically, the correlation between two sequences x (k) and y(k) as a function of the time delay m is expressed as R ( m) xy L k 0 x( k) y( k m).() The correlation equation for the digital bit sequence can thus be written as R (m) = total number of s / total number of bits (2) b b2 b3 b4 bk 2 3 4 K Reference Code Shift Register a a2 a3 a4 ak b b2 b3 b4 bk + + + + + Modulo-2 Adder y y2 y3 y4 yk Fig.Overview of PN Sequence y a b K y 0 if a if a y a b 0 if a Fig. 2. Correlator b if a b b b 56

Fig.2 shows a correlator of length K. One sequence ai is shifted through a K bit shift register and the output of each stage is applied to a set of K XNOR gate for comparison. D. Shift and add When a PN sequence is shifted and the shifted sequence modulo-2 added to the un-shifted sequence with an exclusive-or gate, the result is the same PN sequence with some other shift. This is illustrated in Fig. 3, where a 5 bit PN sequence, a (k)), is arbitrarily shifted by4 bits to get, a (k - 4). The two sequences when modulo-2 added give a sequence which is a 3 bit shifted version, a (k - 3), of the original sequence a (k). Only when the PN sequence is modulo-2 added to itself without shift is the result a sequence of zeros [Li and Hykin (995)]. A direct application of this property is in the generation of two identical sequences with a known large delay between them. 2 4 -=5 bits For example, the polynomial + xi4 + x5 means that the outputs from stages 4 and 5 are modulo- 2 added and fed back to the input of first stage of a 5- stage register to get a 25 - length sequence, as shown in Fig. 4. B. Series-parallel method for high-speed PN generation The maximum PN data rate depends on the type of logic device used. Since only one gate delay (due to the XOR gate) is introduced in the feedback path the maximum PN rate can be close to the highest operating frequency of the shift register. The operating frequency of the PN sequence can be pushed beyond the shift register clock rate by using a high-speed multiplexer. This technique uses the subsequence property of a PN sequence already discussed [Gupta and Kumareshan (2005)]. As we can demultiplex a PN sequence into two similar sequences at half the rate, we can also multiplex two PN sequences to obtain a sequence at double the rate. However, the two sequences should necessarily have a phase shift of half the sequence length.fig.5 shows the circuit for getting PN sequence of length 27 - using series parallel method. Start D3Q3 D7 Q7 Start D2Q2 D6Q6 S S2 DQ D5 Q5 D4Q4 Fig. 3. Addition of PN Sequence III. GENERATION OF PN SEQUENCES A. Using Shift Register with feedback A PN sequence is generated using a shift register and modulo-2 adders. Certain outputs of the shift register are modulo-2 added and the adder output is fed back to the register. An N-stage shift register can generate a maximal length sequence of 2N- bits. Only certain outputs, or taps, can generate a maximal length sequence. The generator output is expressed as a polynomial in 'x'. Fig. 4 A PN Generators with Polynomial + x I4 + x 5 Fig. 5 Series-parallel method for high-speed PN generation C. Avoiding the Zero State An N-bit register can generate 2N- states as against the 2N states of a binary counter, as shown in the state diagram in Fig. 6. Although the counter states generate an ascending or descending sequence, the PN generator output states are apparently random. The all-zero state is missing in the PN sequence. This state is inhibited, because the generator remains latched to it. The modulo-2 adder in the feedback circuit feeds only '0's to the input. An additional circuit is needed to detect the 'all zeros' state and reset the PN register to a valid state. When the register length, N, is small, a NOR gate can decode 0 outputs of the register, forcing a,to the feedback input, through an OR gate, as shown in Fig.7a. A modulo-n down counter may be used for decoding the all zeros state in the PN sequence for large N. The PN data is applied to the load input after inversion as shown in Fig.7b. 57

0 ISSN 2249-6343 but a preferred maximal sequences can only produce Gold codes, as shown in Fig.8. Fig (e) & (f) shows the encrypted 0000 0 0 speech signal and its spectrum using Gold sequences. 0 00 00 Down counter 000 0 Up counter 00 000 00 000 00 000 Fig. 6 State diagrams for (a) binary counter and (b) PN generator 00 00 0 0 00 X X2 X3 X4 X5 00 00 00 000 000 000 000 E. Barker Sequences Barker sequences are short length codes that offer good correlation properties. A Barker code is a sequence of some finite length N such that the absolute value of discrete autocorrelation function r (Ʈ) for Ʈ 0. Barker sequences have many advantages over other PN sequences [Kumar et al. (2008)]. These sequences have uniformly low auto-correlation side these pseudo-random or pseudo-noise (PN) properties include, among other properties, (a) balance, (b) run and (c) auto-correlation lobes ( ), but the size of these families is small. Fig.9 shows Barker sequence generator. XOR NOR Fig.7 (a). A PN generator with all zeros decoder PN generator (2 N -) Fig. 9 Barker Sequence Generator Clock Fig.7 (b). All zeros decoding with a counter D. Gold Sequences Gold sequences are generated by the modulo-2 operation of two different m-sequences of same length. Any two m- sequences are able to generate a family of many non-maximal product codes, a4 a3 a2 a a0 g(d)=45 LOAD CE a'4 a'3 a'2 a' a'0 Output N CO F. Kasami Sequences Kasami sequences are also PN sequences of length N = 2n-, which are defined for even values of n there are two classes of Kasami sequences: (i) small set of Kasami sequences, (ii) large set of Kasami sequences. Small set of Kasami sequences are optimal in the sense of matching Welch s lower bound for correlation functions. A small set of Kasami sequences is a set of 2n/2 binary sequences [Kumar et al. (2008)]. Fig.0 shows Kasami sequence generator. Small set of Kasami sequences are optimal sequences and have better correlation properties compared to Gold sequences. But the set contains less number of sequences. For the shift register of length n the number of possible sequences for the small Kasami sequence set is only 2 n/2 sequences, whereas Gold code set contains 2 n + 2 sequences. The number of sequences can be increased by making some relaxation on the correlation values of the sequences. The resulting set of sequences is called large set of Kasami sequences [Kumar et al. (2008)]. Fig. 8. Gold Sequence Generator 58

IV. COMPARATIVE ANALYSIS 6 5 h ( x) x x h= [,2,...,0] an arbitrary nonzero vector h ' [ d0, d,... dn ] h '( x) x x x x G. Correlation Measures Fig.0 Kasami Sequence Generator PN sequences of desired length are generated as described, and the MSAAC and MSACC measures are computed for the code set. Table. shows the correlation measures for PN sequences of length 6 bits and Table.2 is correlation measures for 32-bit PN sequences. From the results, among all PN sequences m-sequences have low MSAAC values since these sequences have single peak auto correlation function. But these sequences are not suitable for speech encryption since there is only one possible m-sequence of given LFSR length. Gold codes have less MSAAC and MSACC values and for a given length of m-sequence one can generate more number of Gold codes so, these sequence effectively remove the intelligibility of the speech signal by de-correlating the speech samples. The MWH codes have better auto correlation properties as compared to WH codes, but they have poor cross correlation properties. OVSF codes with some specific repetitive sequences gives less correlation values. The MSAAC and MSACC values for OVSF codes with repetitive sequences {-,-,-, } are less and these values are equal to the correlation values of MWH codes. Table : Correlation measures for PN sequences of length6 bits Sequence MSAAC MSACC m-sequences 0.3467 WH codes 4.0625 0.7292 MWH codes.825 0.8792 OVSF codes.825 0.8792 Table 2: Correlation measures for PN sequences of length32 bits Sequence MSAAC MSACC m-sequences 0.4807 6 5 3 WH codes 6.5938 0.7873 MWH codes 3.288 0.8962 OVSF codes 3.288 0.8962 Gold codes 0.6866 0.745 Barker sequence 0.827.0505 2 LFSR satisfies all the properties of PN sequences but for high degree of recursions it is computationally infeasible to evaluate the distance between the phase shifts. It has good autocorrelation but the sequence is not quite maximal length. With Series Parallel method, the rate of generation of PN sequence is at high speed and is used for doubling clock rate of PN generator. Performance of Gold code is good as compared to maximum length sequence and sample to sample correlation is reduced [Kumar et al. (2008)].Small Kasami sequences have less autocorrelation and hence more cross correlation values but the number of sequences that can be generated are less. Thus the security provided by these sequences is less compared to Barker sequence [Kumar et al. (2008)]. Concatenated Shift Registers are computationally feasible and provides a large class of linearly concatenated shift registers to generate approximately maximally spaced phase shifts of PN sequence for use in pseudo random number generation [Hurd and Welch (997)]. In Chaos Based PN sequence the generation of pseudo noise is using digital signal processor which is used in secure communication [Guo and Wang (200)]. It has good statistical properties and generates large set of PN sequence. It is used to randomize the signal over the links and provides PN sequence of higher rate. It is used to generate encryption key and its implementation is done using digital signals. Fig.showing time domain and its spectrum representation for 30 ms voice segment of the speech utterance using m-sequence, Gold code, WH codes, MWH codes and OVSF codes. Fig.2 to 6. shows a periodic auto-correlation function and cross-correlation function of Gold sequence, Barker-like sequence, large Kasami sequence of length 63 bits and MWH sequence, Gold sequence of length 64 bits. V. CONCLUSION We have shown the analysis of different PN sequences with different generation methods. A PN sequence generated by every method is analyzed to check if properties are satisfied. Advantages of every method of PN sequence is studied in this paper. PN sequences are used as spreading code. Correlation measures for PN sequences of length6 bits and 32 bits is given in Tables. We can extend analysis of PN sequences by giving different parameters which are helpful for different applications such as speech encryption and even generate PN sequence using elliptic curves over prime field. REFERENCES 59

[] Haykin, S Communication Systems. 4th Edition. New York: John Wiley and Sons, 200. [2] J.G.Proakis, DigitalCommunications.4 th Edition.United States: McGraw-Hill, 2000. [3] K. T. Alligood, T. D. Sauer, and J. A. Yorke, An Introduction to Dynamical Systems, Springer NY, 997. [4] Lathi, B.P, Modern Digital and Analog Communications Systems.3rd Edition, New York: Oxford University Press, 998. [5] Li.B. X, Haykin,S. A new PN Generator for Spread Spectrum Communications.IEEE,Acoustics,Speech,andSignalProcessing,Vol-5,no.9-2,pp.3603-3606,995. [6] M. P. Kennedy, R. Rovatti, and G. Setti, Chaotic Electronics in Telecommunications, CRC Press, 2007. [7] P. K. Gupta. R. Kumaresan Binary Multiplication with PN Sequences IEEE Transactions on Acoustics Speech and Signal Processing. Vol. 36, no.4, pp. 603-605, 2005. [8] Qianying Guo, Guangyi Wang- Generation of a Chaos-based PN sequence and its quality Analysis, IEEE Communication Society, Vol.54. no. 4, pp. 756-758,200. [9]. Rowtti, G. Setti, and G. Mazzini, Chaotic complex spreading sequences for asynchronous DSC DMA, Some Theoretical Performance Bounds. IEEE Transactions Circ. Sys. I, Vol-45, no. 4, pp. 496-506, 998. [0] V. Anil Kumar, A. Mitra, S. R. Prasanna, Performance Analysis of Different PN Sequences for Speech Encryption, International Journal of Information and Communication Engg, 2008. [] W. J. Hurd, L. R. Welch, Concatenated Shift Registers Chaos, An Introduction to Dynamical Systems, Springer, NY, 997. [2] X. Wang, Y. Wn and B. Caron, Transmitter Identification Using Embedded PN Sequences, IEEE Transaction Broadcasting, Vol. 50 no. 3, pp. 244-252, 2004. Fig : Time domain and its spectrogram representation for 30 ms voice segment of the speech utterance, for original speech segment ((a)&(b)), for encrypted signal, using m-sequences ((c)&(d)), signal using Gold codes ((e)&(f)), using WH codes ((g)&(h)), using MWH codes ((i)&(j)), and using OVSF codes ((k)&(l)). Fig.2: Aperiodic (a) auto-correlation function, (b) cross-correlation function, of Gold sequence of length 63 bits. Fig.3: Aperiodic (a) auto-correlation function, (b) cross-correlation function, of Barker-like sequence of length 63 bits. Fig 4. Aperiodic (a) auto-correlation function, (b) cross-correlation function, of large Kasami sequence of length 63 bits. 60

(a) Fig.5: Aperiodic (a) auto-correlation function, (b) cross-correlation function, of MWH sequence of length 64 bits Fig.6: Aperiodic (a) auto-correlation function, (b) cross-correlation function, of orthogonal Gold sequence of length 64 bits 6