UltraLogic 128-Macrocell ISR CPLD

256 PRELIMINARY Features 128 macrocells in eight logic blocks In-System Reprogrammable (ISR ) JTAG-compliant on-board programming Design changes don t cause pinout changes Design changes don t cause timing changes Up to 128 s Plus 5 dedicated inputs including 4 clock inputs High speed f MAX = 167 MHz t PD = 6.5 ns t S = 4.0 ns UltraLogic 128-Macrocell ISR CPLD t CO = 4.0 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual s Low power option on individual logic block basis 5V and 3.3V capability User-Programmable Bus-Hold capabilities on all s Simple Timing Model PCI compliant Available in 84-Lead PLCC and CLCC, 100-Lead TQFP and 160-Lead TQFP packages Pinout compatible with the CY37064/37064V, V, CY37192/37192V, CY37256/37256V, CY7C373i, CY7C374i, CY7C375i Logic Block Diagram (160-Lead TQFP) S S TDI TCLK TMS JTAG Tap Controller TDO 1 4 / MACROCELL MACROCELLS 4 4 JTAG EN 16 s 0 15 LOGIC BLOCK 36 36 A 16 PIM 16 LOGIC BLOCK H 16 s 112 127 16 s 16 31 LOGIC BLOCK B 36 36 16 16 LOGIC BLOCK G 16 s 96 111 16 s 32 47 LOGIC BLOCK C 36 36 16 16 LOGIC BLOCK F 16 s 80 95 28 63 16 s LOGIC BLOCK D 36 36 16 16 LOGIC BLOCK E 16 s 64 79 64 64 37128 1 Selection Guide -167-125 -100 Maximum Propagation Delay, t PD (ns) 6.5 10 12 Minimum Set-Up, t S (ns) 4 5.5 7.0 Maximum Clock to Output, t CO (ns) 4 6.5 6.5 Typical Supply Current, I CC (ma) in Low Power Mode 60 60 60 Cypress Semiconductor Corporation 3901 North First Street San Jose CA95134 408-943-2600 July 23, 1999

Functional Description The is an In-System Reprogrammable (ISR) Complex Programmable Logic Device (CPLD) and is part of the Ultra37000 family of high-density, high-speed CPLDs. Like all members of the Ultra37000 family, the is designed to bring the ease of use and high performance of the 22V10 to high-density PLDs. # of Leads # Buried Macrocells # Macrocells Package Types 84 64 64 PLCC/CLCC 100 64 64 TQFP 160 0 128 TQFP For a more detailed description of the architecture and features of the, see the Ultra37000 Family data sheet. Fully Routable with 100% Logic Utilization The is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout. This makes Ultra37000 optimal for implementing on-board design changes using ISR without changing pinouts. Simple Timing Model The features a very simple timing model with predictable delays. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. The timing model allows for design changes with ISR without causing changes to system performance. Low Power Operation Each Logic Block of the can be configured as either High-Speed (default) or Low-Power. In the Low-Power mode, the logic block consumes approximately 50% less power and slows down by t LP. Output Slew Rate Control Each output can be configured with either a fast edge rate (default) for high performance, or a slow edge rate for added noise reduction. In the fast edge rate mode, outputs switch at 3V/ns max. and in the slow edge rate mode, outputs switch at 1V/ns max. There is a nominal delay for s using the slow edge rate mode. 3.3V or 5V Operation The operates with a 5V supply, and can support 5V or 3.3V levels. connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the pins to 5V the user insures 5V TTL levels on the outputs. If is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. A nominal timing delay is incurred on output buffers when is set to 3.3V. This device requires 5V ISR programming. In-System Reprogramming The can be programmed in system using IEEE 1149.1 compliant JTAG programming protocol. The can also be programmed on a number of traditional parallel programmers. For an overview of ISR programming, refer to the Ultra37000 Family data sheet and for UltraISR cable and software specifications, refer to the Ultra37000 Programming Kit data sheet (CY3700i). User-Programmable Bus-Hold All outputs of the can either be configured into bushold mode or left floating. When in bus-hold mode, the undriven outputs retain their last value with a weak latch. This feature allows the designer the flexibility of either eliminating or including external pull-up/pull-down resistors. Enabling this feature affects all s simultaneously. Design Tools Development software for the is available from Cypress s Warp or third-party bolt-in software packages as well as a number of third-party development packages. Please refer to the Warp or third-party tool support data sheets for further information. 2

Pin Configurations 84-Lead PLCC (J83) / CLCC (Y84) Top View 0 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 8 12 73 55 9 13 72 54 /TDI 14 10 /TCLK 71 53 11 15 70 52 12 16 69 51 13 17 68 50 14 15 18 19 67 66 49 48 CLK 0 /I 0 20 65 CLK 3 /I 4 21 64 22 63 CLK 1 /I 1 23 62 CLK 2 /I 3 16 24 61 47 17 25 60 46 18 26 59 45 19 27 58 44 20 28 57 43 21 29 56 42 22 30 55 41 23 31 54 40 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 24 25 /TMS 26 27 28 29 30 31 I 2 [1] V CC 32 33 34 35 36 37 /TDO 38 39 7 6 5 4 3 2 1 V CC JTAG EN 63 62 61 60 59 58 57 56 37128-4 Note: 1. This pin is a N/C, but Cypress recommends that you connect it to V CC to ensure future compatibility. 3

Pin Configurations (continued) 100-Lead TQFP (A100) Top View NC 0 7 6 5 4 3 2 1 NC V CC N/C 63 62 61 60 59 58 57 56 NC TCLK 1 2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 TDI 8 9 10 11 12 3 4 5 6 7 73 72 71 70 69 55 54 53 52 51 13 14 15 8 9 10 68 67 66 50 49 48 CLK 0 /I 0 N/C CLK 1 /I 1 16 17 11 12 13 14 15 16 17 65 64 63 62 61 60 59 CLK 3 /I 4 NC CLK 2 /I 3 I / O 47 46 18 18 58 45 19 20 21 22 19 20 21 22 57 56 55 54 44 43 42 41 23 NC 23 24 25 53 52 51 40 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TMS 24 25 26 27 28 29 30 31 I 2 NC [1] V CC 32 33 34 35 36 37 38 39 TDO 37128-5 4

Pin Configurations (continued) 160-Lead TQFP (A160) Top View 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V CC JTAG EN 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 16 17 18 19 20 /TCLK 21 22 23 24 25 26 27 28 29 30 31 CLK 0 /I 0 CLK 1 /I 1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 41 159 48 42 158 49 43 157 50 44 156 51 45 155 52 /TMS 46 154 53 47 153 54 48 152 55 49 151 50 150 56 51 149 57 52 148 58 53 147 59 54 146 60 55 145 61 56 144 62 57 143 63 58 142 I 2 59 141 60 140 61 [1] 139 V CC 62 138 64 63 137 65 64 136 66 65 135 67 66 134 68 67 133 69 68 132 70 69 131 71 70 130 71 129 72 72 128 73 73 127 74 74 126 75 75 125 76 /TDO 76 124 77 77 123 78 78 122 79 79 121 80 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 111 110 109 108 /TDI 107 106 105 104 103 102 101 100 99 98 97 96 CLK 3 /I 4 CLK 2 /I 3 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 37256-2 5

Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature... 65 C to +150 C Ambient Temperature with Power Applied... 55 C to +125 C Supply Voltage to Ground Potential... 0.5V to +7.0V DC Voltage Applied to Outputs in High Z State... 0.5V to +7.0V DC Input Voltage... 0.5V to +7.0V DC Program Voltage...4.5 to 5.5V Current into Outputs...16 ma Static Discharge Voltage...>2001V (per MIL-STD-883, Method 3015) Latch-Up Current...>200 ma Operating Range [2] Ambient Junction Output Range Temperature [2] Temperature Condition V CC Commercial 0 C to +70 C 0 C to +90 C 5V 5V ± 0.25V 5V ± 0.25V 3.3V 5V ± 0.25V 3.3V ± 0.3V Industrial 40 C to +85 C 40 C to +125 C 5V 5V ± 0.5V 5V ± 0.5V 3.3V 5V ± 0.5V 3.3V ± 0.3V Military [3] 55 C to +125 C 55 C to +130 C 5V 5V ± 0.5V 5V ± 0.5V 3.3V 5V ± 0.5V 3.3V ± 0.3V Notes: 2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000 Family devices see the Ultra37000 family data sheet. 3. T A is the Instant On case temperature. 6

Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ. Max. Unit V OH Output HIGH Voltage V CC = Min. I OH = 3.2 ma 2.4 V (Com l/ind) [4] V OHZ I OH = 2.0 ma (Mil) [4] 2.4 V Output HIGH Voltage with Output V CC = Max. I OH = 0 µa (Com l) [5] 4.0 V Disabled [8] I OH = 0 µa (Ind/Mil) [5] 4.3 V I OH = 50 µa (Com l) [5] 3.6 V I OH = 100 µa (Ind/Mil) [5] 3.6 V V OL Output LOW Voltage V CC = Min. I OL = 16 ma (Com l/ind) [4] 0.5 V I OL = 12 ma (Mil) [4] 0.5 V V IH Input HIGH Voltage Guaranteed Input Logical HIGH voltage 2.0 V CCmax V for all inputs [6] V IL Input LOW Voltage Guaranteed Input Logical LOW voltage 0.5 0.8 V for all inputs [6] I IX Input Load Current V I = OR V CC, Bus-Hold Disabled 10 10 µa I OZ Output Leakage Current V O = or V CC, Output Disabled, 50 50 µa Bus-Hold Disabled I OZBH Output Leakage Current V CC = Max., V O = 3.3V, Output Disabled [5], Bus-Hold Enabled 0 70 125 µa I OS I BHL I BHH I BHLO I BHHO Inductance [8] Output Short Circuit V CC = Max., V OUT = 0.5V 30 160 ma Current [7, 8] Input Bus Hold LOW Sustaining Current Input Bus Hold HIGH Sustaining Current Input Bus Hold LOW Overdrive Current Input Bus Hold HIGH Overdrive Current V CC = Min., V IL = 0.8V +75 µa V CC = Min., V IH = 2.0V 75 µa V CC = Max. +500 µa V CC = Max. 500 µa 160-Lead 84-Lead 84-Lead 100-Lead Parameter Description Test Conditions TQFP CLCC PLCC TQFP Unit L Maximum Pin Inductance V IN = 5.0V at f = 1 MHz 9 5 8 8 nh Capacitance [8] Parameter Description Test Conditions Max. Unit C Input/Output Capacitance V IN = 5.0V at f = 1 MHz at T A = 25 C 8 pf C CLK Clock Signal Capacitance V IN = 5.0V at f = 1 MHz at T A = 25 C 12 pf Endurance Characteristics [8] Parameter Description Test Conditions Min. Typ. Unit N Minimum Reprogramming Cycles Normal Programming Conditions [2] 1,000 10,000 Cycles Notes: 4. I OH = 2 ma, I OL = 2 ma for TDO. 5. When the is output disabled, the bus-hold circuit can weakly pull the to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all s are output disabled during ISR programming. Refer to the application note Understanding Bus Hold for additional information. 6. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 7. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V OUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 8. Tested initially and after any design or process changes that may affect these parameters. 7

AC Test Loads and Waveforms 5V 35 pf INCLUDING JIG AND SCOPE 238Ω (COM'L) 319Ω (MIL) (a) 170Ω (COM'L) 236Ω (MIL) 37128-6 5V 5 pf INCLUDING JIG AND SCOPE (b) 238Ω (COM'L) 319Ω (MIL) 37128-7 170Ω (COM'L) 236Ω (MIL) 3.0V <2 ns ALL PULSES 90% 90% 10% 10% <2 ns (c) 37128-8 Equivalent to: THÉVENIN EQUIVALENT 99Ω (COM'L) 136Ω(MIL) 2.08V(COM'L) 2.13V(MIL) 5 OR 35 pf 37128-9 Parameter [9] V X Output Waveform Measurement Level t ER( ) 1.5V t ER(+) 2.6V t EA(+) 1.5V V OH 0.5V V X 37128-10 0.5V V X V OL 37128-11 0.5V V OH V X 37128-12 t EA( ) V the V X 0.5V (d) Test Waveforms V OL 37128-13 Note: 9. t ER measured with 5-pF AC Test Load and t EA measured with 35-pF AC Test Load. 8

Switching Characteristics Over the Operating Range [10] 37128-167 37128-125 37128-100 Parameter Description Min. Max. Min. Max. Min. Max. Unit Combinatorial Mode Parameters t PD t PDL t PDLL t EA t ER [11] Input Register Parameters Input to Combinatorial Output 6.5 10 12 ns Input to Output Through Transparent Input or Output Latch Input to Output Through Transparent Input and Output Latches 10 13 16.5 ns 12 15 17 ns Input to Output Enable 8.5 14 16 ns Input to Output Disable 8.5 14 16 ns t WL Clock or Latch Enable Input LOW Time [8] 2.5 3 3 ns t WH Clock or Latch Enable Input HIGH Time [8] 2.5 3 3 ns t IS Input Register or Latch Set-Up Time 2 2 2.5 ns t IH Input Register or Latch Hold Time 2 2 2.5 ns t ICO t ICOL Input Register Clock or Latch Enable to Combinatorial Output Input Register Clock or Latch Enable to Output Through Transparent Output Latch Synchronous Clocking Parameters t CO [12, 13] t S [11] Synchronous Clock (CLK 0, CLK 1, CLK 2, or CLK 3 ) or Latch Enable to Output Set-Up Time from Input to Sync. Clk (CLK 0, CLK 1, CLK 2, or CLK 3 ) or Latch Enable 11 12.5 16 ns 12 16 18 ns 4 6.5 6.5 ns 4 5.5 7 ns t H Register or Latch Data Hold Time 0 0 0 ns t CO2 t SCS [11] t SL [11] t HL Output Synchronous Clock (CLK 0, CLK 1, CLK 2, or CLK 3 ) or Latch Enable to Combinatorial Output Delay (Through Logic Array) Output Synchronous Clock (CLK 0, CLK 1, CLK 2, or CLK 3 ) or Latch Enable to Output Synchronous Clock (CLK 0, CLK 1, CLK 2, or CLK 3 ) or Latch Enable (Through Logic Array) Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK 0 CLK 1, CLK 2, or CLK 3 ) or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK 0, CLK 1, CLK 2, or CLK 3 ) or Latch Enable Product Term Clocking Parameters t COPT t SPT Product Term Clock or Latch Enable (PTCLK) to Output Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) 10 14 16 ns 6 8.0 10 ns 7.5 10 12 ns 0 0 0 ns 10 13 13 ns 2.5 3 3 ns t HPT Register or Latch Data Hold Time 2.5 3 3 ns t ISPT [11] Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or Latch Enable (PTCLK) Notes: 10. All AC parameters are measured with 2 outputs switching and 35-pF AC Test Load. 11. Logic Blocks operating in low power mode, add t LP to this spec. 12. Outputs using Slow Output Slew Rate, add t SLEW to this spec. 13. When = 3.3V, add t 3.3IO to this spec. -2-2 -2 ns 9

Switching Characteristics Over the Operating Range [10] (continued) 37128-167 37128-125 37128-100 Parameter Description Min. Max. Min. Max. Min. Max. Unit t IHPT t CO2PT Pipelined Mode Parameters t ICS [11] Buried Register Used as an Input Register or Latch Data Hold Time Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) Input Register Synchronous Clock (CLK 0, CLK 1, CLK 2, or CLK 3 ) to Output Register Synchronous Clock (CLK 0, CLK 1, CLK 2, or CLK 3 ) Operating Frequency Parameters 6.5 9 11 ns 14 19 21 ns 6 8 10 ns f MAX1 Maximum Frequency with Internal Feedback (Lesser of 1/t SCS, 1/(t S + t H ), or 1/t CO ) [8] 167 125 100 MHz f MAX2 Maximum Frequency Data Path in Output 200 158 153.8 MHz Registered/Latched Mode (Lesser of 1/(t WL + t WH ), 1/(t S + t H ), or 1/t CO ) [8] f MAX3 Maximum Frequency with External Feedback 105 83 76.9 MHz (Lesser of 1/(t CO + t S ) or 1/(t WL + t WH )) [8] f MAX4 Maximum Frequency in Pipelined Mode (Lesser of 1/(t CO + t IS ), 1/t ICS, 1/(t WL + t WH ), 1/(t IS + t IH ), or 1/t SCS ) [8] 143 125 100 MHz Reset/Preset Parameters t RW Asynchronous Reset Width [8] 8 10 12 ns [11] t RR Asynchronous Reset Recovery Time [8] 10 12 14 ns t RO Asynchronous Reset to Output 13 15 18 ns t PW Asynchronous Preset Width [8] 8 10 12 ns t PR [11] t PO User Option Parameters Asynchronous Preset Recovery Time [8] 10 12 14 ns Asynchronous Preset to Output 13 15 18 ns t LP Low Power Adder 2.5 2.5 2.5 ns t SLEW Slow Output Slew Rate Adder 2.5 2.5 2.5 ns t 3.3IO 3.3V Mode Timing Adder [8] 0.3 0.3 0.3 ns JTAG Timing Parameters t S JTAG Set-Up Time from TDI and TMS to TCK [8] 0 0 0 ns t H JTAG Hold Time on TDI and TMS [8] 20 20 20 ns t CO JTAG Falling Edge of TCK to TDO [8] 20 20 20 ns f JTAG Maximum JTAG Tap Controller Frequency [8] 20 20 20 MHz 10

Typical I cc Characteristics 160 140 High Speed 120 Icc (ma) 100 80 Low Power 60 40 20 0 0 20 40 60 80 100 120 140 160 180 Frequency (MHz) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. V cc = 5.0V, T A = Room Temperature 11

Switching Waveforms Combinatorial Output t PD COMBINATORIAL 37128-14 Registered Output with Synchronous Clocking t S t H SYNCHRONOUS t CO REGISTERED t CO2 REGISTERED t WH t WL SYNCHRONOUS 37128-15 Registered Output with Product Term Clocking Input Going Through the Array t SPT t HPT PRODUCT TERM t COPT REGISTERED 37128-16 12

Switching Waveforms (continued) Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register t ISPT t IHPT PRODUCT TERM t CO2PT REGISTERED 37128-17 Latched Output t SL t HL LATCH ENABLE t PDL t CO LATCHED 37128-18 Registered Input REGISTERED t IS t IH REGISTER t ICO COMBINATORIAL t WH t WL 37128-19 13

Switching Waveforms (continued) Clock to Clock REGISTER t ICS t SCS REGISTER 37128-20 Latched Input LATCHED t IS t IH LATCH ENABLE t PDL t ICO COMBINATORIAL t WH t WL LATCH ENABLE 37128-21 Latched Input and Output LATCHED t PDLL LATCHED LATCH ENABLE t ICOL t SL t HL t ICS LATCH ENABLE t WH t WL LATCH ENABLE 37128-22 14

Switching Waveforms (continued) Asynchronous Reset t RW t RO REGISTERED t RR 37128-23 Asynchronous Preset t PW t PO REGISTERED t PR 37128-24 Output Enable/Disable t ER t EA S 37128 25 15

Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range 167 P84 167JC J83 84-Lead Plastic Leaded Chip Carrier Commercial P100 167AC A100 100-Lead Thin Quad Flat Pack P160 167AC A160 160-Lead Thin Quad Flat Pack 125 P84 125JC J83 84-Lead Plastic Leaded Chip Carrier Commercial In-System Reprogrammable, ISR, UltraLogic, Ultra37000, and Warp are trademarks of Cypress Semiconductor Corporation.. Document #: 38 00558 E P100 125AC A100 100-Lead Thin Quad Flat Pack P160 125AC A160 160-Lead Thin Quad Flat Pack P84 125JI J83 84-Lead Plastic Leaded Chip Carrier Industrial P100 125AI A100 100-Lead Thin Quad Flat Pack P160 125AI A160 160-Lead Thin Quad Flat Pack P84 125YMB Y84 84-Lead Ceramic Leaded Chip Carrier Military 100 P84 100JC J83 84-Lead Plastic Leaded Chip Carrier Commercial P100 100AC A100 100-Lead Thin Quad Flat Pack P160 100AC A160 160-Lead Thin Quad Flat Pack P84 100JI J83 84-Lead Plastic Leaded Chip Carrier Industrial P100 100AI A100 100-Lead Thin Quad Flat Pack P160 100AI A160 160-Lead Thin Quad Flat Pack P84 100YMB Y84 84-Lead Ceramic Leaded Chip Carrier Military 16

Package Diagrams 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-B 17

Package Diagrams (continued) 160-Pin Thin Plastic Quad Flat Pack (TQFP) A160 51-85049-A 84-Lead Plastic Leaded Chip Carrier J83 51-85006-A 18

Package Diagrams (continued) 84-Pin Ceramic Leaded Chip Carrier Y84 51-80095 Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.