Loop Bandwidth Optimization and Jitter Measurement Techniques for Serial HDTV Systems

Abstract: Loop Bandwidth Optimization and Jitter Measurement Techniques for Serial HDTV Systems Atul Krishna Gupta, Aapool Biman and Dino Toffolon Gennum Corporation This paper describes a system level optimization of a studio serial digital interface for uncompressed High Definition Television (HDTV). The HDTV data rate is 5.5 times that of Standard Definition Television (SDTV) which allows little design margin for jitter. An intuitive time domain discussion of different sources of jitter is presented. This paper provides design guidelines for video sources, routers, digital signal processing units with serial interface, distribution amplifiers and production switchers. These guidelines reinforce the SMPTE 292M standard and other recommended practices, e.g. EG33-1998. Using commercially available general-purpose test units and some custom built boards it is shown that some of the important jitter parameters associated with serial HDTV can be easily measured. 1 page of 21

1. Introduction The HDTV signal is standardized by the SMPTE 292M standard [1]. SMPTE 292M is very similar to SMPTE 259M [2] with respect to several electrical characteristics. The randomizing polynomial and channel coding pose the same pathological signal challenges [3]. Table 1.1 compares jitter specifications for the SMPTE 259M and 292M standards. Figure 1.1 graphically illustrates the SMPTE- 292M jitter specification. Table 1.1 Jitter Parameter SMPTE 259M-1993 SMPTE 292M-1996 B1 (f1) (Timing jitter 10Hz 10Hz lower band edge) B2 (f3) (Alignment jitter 1kHz 100kHz lower band edge) B3 (f4) (Upper band >27MHz >148.5MHz edge) A1 (Timing jitter) 1.0UI 1.0UI A2 (Alignment jitter) 0.2UI 0.2UI Test Signal Colour bar test signal Colour bar test signal Clock divider ratio (n) Except 10 Except 10 (preferred) Timing Jitter 1.0UI A1-20dB/decade slope Sinusoidal Input Jitter Amplitude Alignment Jitter 0.2UI A2 10Hz B1 (f1) 20kHz (f2) 100kHz B2 (f3) Jitter Frequency for HDTV 148.5MHz B3 (f4) Figure1.1 Jitter template for SMPTE 292M According to the above table, the source should not have jitter more than 1UI (673ps) in the frequency band above 10Hz. The alignment jitter should not be more than 0.2UI (135ps) in the frequency band beyond 100kHz. The alignment jitter lower frequency has changed from 1kHz to 100kHz from SMPTE 259M to SMPTE 292M. Even though the alignment jitter is defined from 100kHz to greater 2 page of 21

than 1/10 th the serial clock frequency, it is important to make sure that the jitter is not more than 0.2UI up to 1/2 the serial clock frequency. This is because the SDI signal may have jitter in that band which could cause errors when it is sampled at the receiver or the re-timer. There could be fair amount of jitter present in the frequency band around 1/2 the serial clock frequency, because any data duty cycle distortion appears as jitter at 1/2 the serial clock frequency. The need for video field and line synchronization, and the unique channel coding makes the SMPTE standard different from other digital communication protocols, e.g. SONET, Fiber channel etc. 2. The Studio Model A simplified studio model is illustrated in Figure 2.1. Distribution Amplifiers (DAs), Digital signal processors (DSP) and Routers can be used several times in one signal stream. All the sources have to be synchronized to the master clock or the house synch. House synch is used to synchronize lines and frames so that switching does not create partially blank screens during multiplexing of various sources. Because both front-end (sources) and back-end (production switcher) are synchronized with the same master clock, it is important to control jitter and provide sufficient input jitter tolerance in individual blocks to prevent errors. House synch for Genlock Camera VTR Other sources Distribution Amplifier (DA) N inputs X M outputs Router SDI Sources Digital Signal Processing Unit Monitor Production Switcher Transmitter Figure 2.1 A Simplified Model of a TV Studio 3. Sources of Jitter and Their Frequency Spectrum 3 page of 21

Bandwidth limited devices in the signal chain e.g. cable drivers, cable equalizers and crosspoints all add jitter. Let us assume that there is a NRZI signal passing through a bandwidth-limited device. Figure 3.1 shows the generation of phase error by bandwidth limited circuits in the time domain. Input R=75, C=4pF Bandwidth limited channel Output Input Zero crossing (A) Input Output Shifted output to determine phase error Phase =0 UI Phase =0 UI Phase =0 UI Phase =-0.5 UI Phase =0 UI (B) Output (C) 0.1UI Output 0.0UI Phase -0.1UI time Pseudo Random Pathological (27 us) Pseudo Random (D) Jitter Histogram Figure 3.1: Illustration of time domain jitter introduction in a bandwidth limited system. (A) A bandwidth limited circuit. (B). The waveform of the input and output of a bandwidth limited system. (C) The eye diagram of the waveform in (B). (D) The phase plot with respect to time. The jitter introduced from this effect is a systematic jitter and it accumulates as arithmetic addition in a cascaded system. In some cases, it could subtract as well, however to build a robust system, we have to consider that it adds in every pass. This type of timing problem is also known as inter symbol interference (ISI). Most types of equipment used in the studio are based on phase locked loops (PLLs) because they are either synchronized to the house synch or to the received serial digital data. Depending upon the loop bandwidth (LBW) of the PLL, low frequency jitter will be passed and high frequency jitter will be filtered. Figure 3.2 shows a typical second order traditional PLL [4]. White noise in the VCO is assumed. Figure 3.2(C) shows the typical open loop voltage controlled oscillator (VCO) and phase locked loop VCO phase noise, which shows that the noise is also present within the loop bandwidth. The pathological pattern, which is unique to SMPTE signals, may last as long as the active video line. Similar to bandwidth limited circuits, the PLL could also have time domain jitter as shown in Figure 3.1(D). This is especially true for data recovery circuits, which extract clock from data, and are inevitably pattern dependent. The noise in PLLs inside serializers is not directly related to the data pattern because the PLL locks on to a clock, which does not have any pattern. However, board noise is often related to the data pattern, and thus could introduce jitter which has similar time domain characteristics as shown in Figure 3.1. 4 page of 21

Delay in most microchips is a function of the temperature. When the temperature changes over time, the output phase changes. However, the temperature change in microchips is slow, and the drift in the output phase happens slowly. This kind of jitter will fall in wander category, and does not pose any problem. While evaluating any unit for jitter, it is recommended for the unit to be temperature stabilized to isolate timing jitter and alignment jitter from wander jitter. White Noise Input Phase Phase Detector Charge pump Loop Filter VCO Output Phase (A) Gain 0db Loop bandwidth pole -20dB/decade Slope Noise Integrator pole PLL VCO noise spectrum Open loop VCO noise spectrum (1/f 2 noise) Loop Bandwidth Pole Frequency Frequency (B) (C) Figure 3.2 Intrinsic jitter generation in a typical PLL. (A) Typical linear PLL. (B) Jitter transfer function. (C) Noise spectrum density of the typical PLL. 4. Jitter Measurement Techniques: 4.1 Timing and Intrinsic Jitter Measurement: The clock extractor method is generally used to measure jitter. The timing jitter is measured with a clock extractor of 10Hz LBW and alignment jitter is measured with 100kHz LBW clock extractor. It is difficult to attain a clock extraction LBW of 10Hz without adding the intrinsic jitter of the clock extractor. As an alternate, we recommend measuring the intrinsic jitter of the individual units as shown in Figure 4.1. This is based on the assumption that the timing jitter of a device can be approximated to the intrinsic jitter of the device. The intrinsic jitter is the amount of jitter present in the entire jitter frequency spectrum with respect to a clean reference input. The timing jitter excludes jitter content in the frequency band from DC to 10Hz. Thus, intrinsic jitter overestimates timing jitter. However, in the case of a PLL (Figure 3.2), the presence of a integrator pole reduces the content of the jitter in the lower frequency band. In most cases the integrator pole occurs beyond 10Hz. As long as this assumption is true, timing jitter is very close to the intrinsic jitter. Figure 4.2 illustrates intrinsic jitter, timing jitter and alignment jitter 5 page of 21

Index Single ended signals Jitter Reconditioning Unit Differential signal Any HDTV source Receiver LBW=4.2MHz Parallel data Parallel Clock PLL LBW < BW of DUT Serializer LBW=1.41MHz Clock Multiplier CSA803 Scope Device Under Test (DUT) With Known LBW Ch 1 Direct Trigger Figure 4.1 Intrinsic jitter measurement setup Intrinsic Jitter Timing Jitter Alignment Jitter Noise Power 1 / Persistence Time 10Hz 100kHz 1/2 Data Rate Frequency Figure 4.2 Intrinsic, Timing and Alignment Jitter Spectrum It is important to verify that the LBW of the jitter-reconditioning unit is much lower than the LBW of the device under test. If the LBW of the jitter reconditioning unit is greater than the device under test and if there is fair amount of jitter present in that frequency band, the trigger will have more jitter than the device under test. In this case, the intrinsic jitter measurement will be more than the actual jitter of the device under test. Figure 4.3 illustrates a case where a cleaner PLL with narrow 6 page of 21

LBW is measured with a source having jitter beyond the LBW of the device under test. Noise Power Spectrum Source Jitter Spectrum f Noise Power Spectrum Noise Power Spectrum Jitter Reconditioning Board Jitter Spectrum f Noise Power Spectrum Device Under Test Jitter Spectrum Measured Intrinsic Jitter Not Due to DUT f f Figure 4.3 Incorrect choice of LBW in Jitter Reconditioning Board The jitter reconditioning unit must be checked for its own intrinsic jitter before it can be used to precisely characterize other units. A pristine bit error rate tester was used to test the jitter reconditioning unit. We also verified the intrinsic jitter using a special signal pattern programmed in the bit error rate tester, which accurately models the SMPTE pathological signal. A jitter-reconditioning unit was realized with a LBW of approximately 1.0kHz at 0.2UI input jitter modulation. The particular PLL which was used, with a voltage controlled crystal oscillator (VCXO), behaved partially as a slew PLL (Section 5) when used with a specific loop filter to achieve low LBW. The intrinsic jitter of the unit measured was approximately 60ps p-p for 2 23-1 pseudo random pattern and 70ps p-p for pseudo pathological pattern. 4.2 Alignment Jitter: The high frequency (above 100kHz) component of the timing jitter is classified as alignment jitter. The limits for the alignment jitter are tighter than those of timing jitter. As a result we may have to isolate the alignment jitter if timing jitter is more than the SMPTE alignment jitter limit, to make sure that the unit is tested according to SMPTE specifications. The alignment jitter can be tested using a calibrated 100kHz linear clock extractor. 7 page of 21

To measure the alignment jitter in accordance with the SMPTE guidelines, we devised a unit using a wide LBW clock recovery circuit. The 100kHz LBW was precisely set by a secondary PLL locked to the clock recovery circuit s extracted clock as shown in Figure 4.4. In most cases, the intrinsic jitter measurement alone is sufficient. In Section 6.3.2, it is mentioned where this measurement is absolutely required. Using a pristine data source, we measured alignment jitter of approximately 30ps for pseudo random pattern and 50ps for pseudo pathological pattern. This could be considered as the intrinsic jitter of this test setup. It is not obvious whether root-mean-square (rms) or arithmetic subtraction should be done to find the true alignment jitter of the device under test. We recommend mentioning the intrinsic jitter of the test instrument while describing jitter of any device. CSA803 Scope Ch 1 Direct Trigger Bypass Output Device Under Test Differential Input Clock Recovery Circuit LBW=1.41MHz 100kHz Clock Extractor Board Div 2 Div 2 VCO output Phase frequency Detector Charge Pump Extracted Clock Buffer VCO Loop filter LBW= 100kHz Figure 4.4. Alignment jitter measurement using a clock extractor 5. Slew Phase Lock Loop Most PLLs used in electronic circuits are linear. Linear PLLs are thoroughly covered in the literature. A brief discussion of a slew PLL used by Gennum is presented in this paper. A slew PLL is a non-linear PLL where the output phase variation is slew limited. A slew PLL offers significant advantages for SMPTE SDI signals over linear PLLs. In Section 6, bandwidth optimization is described where either a linear PLL or slew PLL could be used. While designing a PLL, there are two main objectives, jitter attenuation and VCO/board noise immunity. The jitter attenuation is achieved by lowering the LBW whereas noise tolerance is achieved by increasing the LBW. These two contradicting requirements are conveniently met with the slew PLL. 8 page of 21

Figure 5.1 compares linear and slew PLLs. For a fair comparison, the phase slew of the slew PLL and LBW of the linear PLL are chosen such that at 0.2UI input jitter modulation, both achieve 3dB 1 attenuation at 1.4MHz modulation frequency. The jitter transfer function is plotted at 2.8MHz to show how the PLL attenuates input jitter at higher frequency. It can be seen that the output jitter of the slew PLL attains a maximum and then it is limited. This is an attribute of the non-linearity present in the slew PLL. A linear PLL is unaffected by the input jitter modulation index. The slope of the jitter transfer line can be calculated by the jitter transfer function of a first order low pass filter. Consider, the slew PLL transfer function at 2.8MHz, the 3dB attenuation occurs at 0.1UI input jitter modulation. In other words, if the input jitter modulation is lowered, the 3dB LBW increases. For an infinitesimal small input signal, the slew PLLs have infinitely large LBW, where as the LBW of the linear PLL is fixed. In a careful design, the intrinsic VCO noise and board interference can be considered as a small signal noise. As we know that the higher LBW accounts for canceling more VCO noise, the PLLs with wider LBW tend to be more robust. Therefore, we believe that slew PLLs are more robust than the linear counterparts. Because of the non-linear characteristics, the slew PLL achieves higher jitter attenuation in the presence of large input jitter while providing small signal VCO/board noise immunity. In this paper, if bandwidth of any slew PLL is mentioned, unless otherwise noted, it is defined at 0.2UI (135ps) input jitter modulation. 1 The 3dB bandwidth of a non-linear system cannot be defined as it can be defined for the linear system. We define 3dB bandwidth as peak to peak jitter attenuation. For example if the input jitter is modulated at 0.2UIp-p then the 3dB jitter attenuation will result in 0.141UIp-p output jitter. 9 page of 21

0.5 Output Jitter (UI) 0.4 0.3 0.2 Input Jitter Modulation At 1.4MHz Linear PLL Slew PLL 0.1 At 2.8MHz 0.0 0.0 0.1 0.2 0.3 0.4 0.5 Input Jitter (UI) Figure 5.1 Transfer functions of Linear and Slew PLL 6. LBW optimization for different units in the Studio As mentioned in Section 2, several of the units could be cascaded in a studio. In such a signal chain, the jitter will accumulate from unit to unit. For error free operation, the LBW of the receiver of the subsequent units should be wider to track the accumulated jitter. Gennum recommends the bandwidth ranges shown in table 6.1 for the different units. This scheme will guarantee a trouble free interface between units. Table 6.1 Type of Unit Transmitter (Serializer) Re-timer Receiver (De-serializer) Bandwidth Range 1Hz-100kHz 500kHz-2MHz 3MHz-6MHz 6.1 Video Sources: In the studio, we define a source as a unit, which generates serial digital data e.g. cameras, VTRs etc. For synchronous use, it has to be genlocked to the house synch. Generally a very stable controlled crystal with very little intrinsic jitter is used for this purpose. Figure 6.1.1 shows a very simple diagram of a source. The house synch reference could have jitter. The specification on the synchronization pulse is mentioned in RP 154. The genlock utilizing a VCXO may be used with very low LBW (<10Hz) such that the recovered parallel clock (p- 10 page of 21

clock) meets the SMPTE 292M jitter specification where jitter is measured in time, and A1=673ps and A2=135ps (Table 1.1). Ideally, the jitter on the genlock generated parallel clock should be much better than the SMPTE specifications to accommodate jitter accumulation in the serializer and subsequent cascaded units. The design of the genlock circuit is beyond the scope of this paper. Because the parallel clock is derived from a clean VCXO, there is no need to further filter the jitter using the PLL in the serializer. In this case, the optimum bandwidth recommended by the manufacturer can be used. 0.05 UI Serializer & Cable Driver LBW=(129Kz- 1.4MHz) 2 UI Data Source Parallel clock clean reference signal VCXO Genlock PLL House Synch Fig 6.1.1 An HDTV source 6.1.1 Jitter Characterization of the Video Sources The intrinsic jitter of the serializer output can be measured using the Tektronix CSA 803 scope, triggered by the genlocked parallel clock. The output of the serializer could have a parallel clock jitter component, which may not be seen in this case, as it will be synchronous to the parallel clock. To accurately measure the jitter, we recommend multiplying the parallel clock to the HDTV rate, and using this to trigger the serial data stream. However, the multiplied clock may add some jitter. The jitter reconditioning unit (Figure 4.1) mimics a video source. It also has an on-board clock multiplier. Table 6.1.1 summarizes the achievable jitter measurements of these units. Table 6.1.1 Video Pattern SMPTE specification Colour bars Pathological Intrinsic jitter of the serializer at 129kHz LBW 673ps (Timing) 135ps (Alignment) 30ps-60ps 40ps-60ps Since the intrinsic jitter is less than the SMPTE alignment jitter specification, there is no need to isolate alignment jitter. 6.2 Routers 11 page of 21

A simplified router is shown in Figure 6.2.1. The cable driver, cable equalizer and the crosspoint can be modeled as a bandwidth limited channel. Figure 6.2.2 shows the jitter addition and jitter filtering inside a router. It is assumed that the equalizer jitter is 0.2UIp-p at the input of the re-timer and the source is clean. During the pseudo random section of the data pattern, the jitter is attenuated. During the pathological section, the re-timer follows the input jitter. The time it takes to follow the input jitter is decided by the LBW. If LBW is set low, it is possible to reduce the jitter of the router, however, it will take significant time to settle during synchronous switching. In synchronous switching, the worst case phase offset could be 0.5UI. If it takes several lines to recover the 0.5UI step, then during this time, the phase offset will look like input jitter. If the phase offset is more than the input jitter tolerance, errors will result. We believe the best compromise is to set the LBW between 500kHz to 2MHz. Equalizer Equalizer Cross Point Re-timer & Cable Driver Re-timer & Cable Driver Equalizer Re-timer & Cable Driver Figure 6.2.1 Simplified Router architecture 12 page of 21

0.05UI Input phase of the Re-timer Output phase of the Re-timer Pseudo random pattern output peak-peak jitter Output Phase 0.0UI Pathological pattern output peak-peak jitter -0.05UI time Pseudo Random Pathological (27 us) Pseudo Random Figure 6.2.2: Illustration of jitter filtering in a router Due to the synchronous lock time specification we do not recommend using a very narrow LBW. Conversely, if very high LBW is used, some of the high frequency jitter will be passed onto next unit in the chain, causing jitter accumulation. The jitter peaking in re-timers is usually less than 0.1dB, which adds approximately 1% jitter. Thus the effects of jitter peaking could be ignored in most cases. 6.2.1 Jitter Characterization of Routers An application circuit board containing an equalizer and a re-timer (LBW=1.4MHz) can be used to model the router. The intrinsic jitter of the router can be characterized according to the Figure 4.1. Table 6.2.1 summarizes the achievable intrinsic jitter for 0m and 100m of Belden 8281 cable between the jitter reconditioning unit and the device under test. Table 6.2.1 Video Pattern 0m Belden 8281 Cable 100m Belden 8281 Cable SMPTE specification 673ps (Timing) 135ps (Alignment) 673ps (Timing) 135ps (Alignment) Colour Bars 30ps-60ps 30-80ps Pathological 40ps-70ps 40-100ps The jitter added by the crosspoint can be assumed as bandwidth limited and systematic and should be added to the intrinsic jitter for worst case analysis. 13 page of 21

6.3 De-serializer and Serializer Units A de-serializer and serializer unit receives a serial digital signal, and converts it into 20 bit words. A parallel clock is also generated which is 1/20 th the serial clock rate. Digital signal processing is then done on the parallel, 20 bit data, after which a serializer converts the 20 bit words into the serial digital stream. The interface between serializer and de-serializer is a 20 bit parallel bus. Because of this interface, there is a built-in data buffer, which increases the jitter tolerance (specified as set-up and hold time) between these two microchips. Ideally this could add +/-10 bits of data buffer. However, because of slower rise/fall times and set-up and hold times, +/-5 bits of data buffer is usually achieved. The LBW of the de-serializer should be chosen between 3MHz to 6MHz and the LBW of the serializer should be chosen less than 100KHz. This combination allows the input jitter tolerance template to overlap with the jitter transfer function. If the receiver s LBW is 4.2MHz and the router s LBW is 1.4MHz, the receiver will follow the jitter of the router during the pathological video line. Both, the receiver and re-timer could be based on the slew PLL. The phase at the re-timer at 1.4MHz slews slowly so that 4.2MHz receiver could closely track it even for the worst case manufacturing LBW tolerances. The choice of these two LBWs is key to a robust system design. The parallel clock interface is single ended and the presence of single ended 20 bit parallel data could add fair amount of systematic jitter (approximately 0.7UI) during pathological signal. Noise resulting from parallel DSP microchips is another source of systematic jitter introduction. We can differentiate the De-serializer/Serializer units as being of two types. The first type filters the jitter in the parallel clock using a VCXO/PLL and the second type of unit circuit does not filter the parallel clock which feeds the serializer. 6.3.1 VCXO based De-serializer/Serializer units: The VCXO based PLL is the most commonly used approach for Deserializer/Serializer units. Figure 6.3.1 shows the block diagram. 14 page of 21

0.2 UI 0.3 UI Equalizer De-serializer (LBW =3MHz- 6MHz) 1.0 UI 0.073 UI Serializer & Cable Driver (LBW = 129kHz- 1.4MHz) 3.0 UI 0.023 UI DSP Core 0.023 UI 1.0 UI VCXO Slew PLL 1kHz-3kHz Loop BW Figure 6.3.1 VCXO Based De-serializer/Serializer Unit Assuming alignment jitter of the source to be 0.2UI and 0.1UI of jitter added by the equalizer, the jitter seen by the de-serializer is 0.3UI. The typical input jitter tolerance of the de-serializer is about 0.5UI. The wider LBW follows input jitter as much as possible. Delay between the clock and the output data of the DSP core should be properly considered. The PLL with a VCXO is used to clean the jitter present in the parallel clock from the receiver. The data input to the serializer is from a DSP microchip or an FPGA whereas the clock with which the parallel data is sampled is from the clean VCXO output. The alignment and jitter of the parallel data may stress the input jitter tolerance (set-up and hold time) of the serializer. The designer should watch for two potential pitfalls in today s off-the-shelf PLL microchips designed to work with the VCXO. 1. Dead zone: Some PLL microchips could have a dead zone. This may result in abnormally high jitter when the input phase aligns in the dead zone of phase detector. This happens because there is no corrective feedback for the VCO phase when the phase alignment is in the dead zone of the phase detector. To avoid a dead zone, a shunt resistor to ground or power supply should to be used at the phase frequency detector (PFD) output. This shunt resistor may cause a phase offset. The choice between shunting to ground or power supply is determined by the one, which provides the best set-up and hold time for the serializer. 15 page of 21

2. Input phase offset: Some PLLs, which do not have a charge pump, could have input phase offset due to a different locking position for the VCXO. By choosing proper LBW or phase slew, the phase drift during one video line can be chosen as low as 15ps-20ps. Due to the clean reference available, the PLL within the serializer does not need to filter any jitter; thus wider LBW can be used. A wider LBW is more tolerant to board noise. However, phase detector noise passes through the wider LBW and therefore increasing the LBW excessively may also increase the output jitter. We recommend LBW within 129kHz to 1.4MHz. 6.3.1.1 Jitter Characterization of VCXO Based De-serializer/Serializer Units This type of unit can be tested for intrinsic jitter using the jitter reconditioning unit (Figure 4.1). In this case the LBW of the jitter reconditioning unit should be set lower than the VCXO based De-serializer/Serializer unit under test. Table 6.3.1 summarizes the achievable jitter. Table 6.3.1 Video Pattern SMPTE Specification Colour Bars Pathological Pattern Intrinsic Jitter 673ps (Timing), 135ps (Alignment) 30ps-100ps 30ps-100ps Since the total jitter is less than the alignment jitter, there is no need to isolate timing jitter and the alignment jitter. 6.3.2 De-serializer/Serializer units without a VCXO: In certain situations, it is desirable to have a low cost solution by just using a serializer and a de-serializer without filtering the parallel clock. The block diagram of such a De-serializer/Serializer unit is shown in Figure 6.3.2. The source is assumed to have 0.2UI jitter and the jitter added by the equalizer is assumed to be 0.1UI. The jitter is additive assuming systematic jitter. The jitter that is added at the parallel clock generation from the de-serializer is assumed to be 0.7UI. The jitter that is added by the DSP core is assumed to be 2UI. Therefore the total phase step (jitter) could be as high as 3.0UI into the serializer. With a narrow LBW the serializer can be designed with a phase slew, which results in 0.4UI phase drift during the pathological line. Depending upon the pattern dependency, the peak to peak systematic jitter would be 2X0.4=0.8UI. 16 page of 21

Adding 0.05UI random jitter, the total output jitter would be 0.85UI, which is less than the SMPTE 1UI timing jitter specification. Most of the jitter component is around 37kHz (pathological line) which is low frequency jitter. The timing jitter extracted using a 10Hz clock extractor will be close to the intrinsic jitter. Thus, the timing jitter can be considered as intrinsic jitter and there is no need to use the clock extraction method to measure timing jitter. Since the timing jitter is greater than the alignment jitter specification, we have to measure the alignment jitter. As mentioned in Section 4.2, the clock extractor with 100kHz LBW setting should be used. This architecture meets the SMPTE requirement, however, it may require careful board layout because of the low LBW involved and it does not provide superior jitter performance. Let us consider how jitter accumulates in the time domain when similar Deserializer/Serializer units are cascaded (Figure 6.3.2). The longest run of pattern dependency in a SMPTE SDI signal is about 27µs (equal to one active video line). Since the phase drift in every unit is determined by the PLL slew, we could set the slew such that the maximum phase drift is limited to 0.85UI. As a first order of approximation the overall phase will not drift more than 0.85UI even when similar units are cascaded. De-serializer 1.0 UI DSP Core 3.0 UI Serializer LBW=50kHz 0.3 UI Equalizer 0.85 UI 0.2 UI 0.85 UI De-serializer 1.65 UI DSP Core Serializer LBW=50kHz 0.95 UI 3.65 UI Equalizer 0.85 UI 0.85 UI 0.85 UI Clock Extractor 100KHz loop BW Figure 6.3.2: Jitter accumulation in a cascaded De-serializer/Serializer Units without a VCXO 6.3.2.1 Jitter Characterization of De-serializer/Serializer Units without a VCXO: The intrinsic jitter and the alignment jitter could be measured according to Section 4. Table 6.3.2 summarizes the expected jitter of these types of units. 17 page of 21

Table 6.3.2 Video Pattern Intrinsic (Timing) Jitter Alignment Jitter SMPTE specification 673ps 135ps Color Bars 50ps-300ps 40ps-80ps Pathological pattern 400ps-600ps 50ps-110ps 6.4 Distribution Amplifier (DA) Two types of DAs could be realized depending upon the performance needed and the cost target; re-timer based units and De-serializer/Serializer based units. 6.4.1 Re-timer based DA: The block diagram of the re-timer based DAs is shown in Figure 6.4.1 Equalizer Re-timer Cable Driver Cable Driver Cable Driver Cable Driver Figure 6.4.1: Re-timer based DA This is the simplest DA. Because the re-timer does not have any data buffer, the typical input jitter tolerance is 0.5UIp-p beyond the LBW. Since this architecture of the DA is very similar to that of the router, jitter filtering happens in the same way as shown in Figure 6.2.2. In a system, a DA could be used directly after the source, or it could be cascaded in front of another similar DA or a router. Figure 6.4.2 shows how jitter accumulates in a multiple pass situation. Consider jitter from a router as a first pass (Figure 6.2.2). The output phase of the router s re-timer is the input of the DA through a bandwidth-limited channel (shown with the thick line in Figure 6.4.2). The jitter during pseudo-random pattern does not add arithmetically, however during pathological line, the jitter 18 page of 21

from one pass to the next adds arithmetically. This is because the response time, which is related to the LBW of the re-timer, is less than the pathological line duration. If all the DAs and Routers in a chain have exactly the same LBW, then the next re-timer will follow the accumulative jitter. However, in manufacturing it is not possible to manufacture PLLs with exactly the same loop bandwidth. The bandwidth of similar re-timer microchips may vary over process (approximately +/-45%) and from manufacturer to manufacturer it may vary even more (up to 500%). The worst case results when re-timers earlier in the chain have a wider LBW causing accumulation of jitter in that frequency band and the last re-timer with a nominal LBW or lower LBW does not track the accumulated jitter. When the accumulated jitter exceeds the input jitter tolerance of the last re-timer, errors will be generated. The jitter peaking which is typically less than 0.1db or 1%, is not a major reason for jitter build up in SMPTE signal because the pathological line induced jitter dominates. Output Phase 0.05UI Output phase of the first Re-timer + Jitter of Bandwidth limited channel before second Re-timer Output phase of the second Re-timer Pseudo random pattern output peak-peak jitter 0.0UI Pathological pattern output peak-peak jitter of second DA -0.05UI -0.10UI time Pseudo Random Pathological (27 us) Pseudo Random Figure 6.4.2: Illustration of jitter accumulation 6.4.2 De-Serializer and Serializer Based DA To ensure a large number of passes, the jitter may be filtered in the parallel domain to utilize the data buffer provided by the de-serializer and serializer interface. This type of DA is very similar to the De-serializer/Serializer units and a similar design criterion could be used. Again, a VCXO based or a non-vcxo based DA could be realized. 19 page of 21

6.5 Production Switcher A production switcher representation is illustrated in Figure 6.5.1 Input Channel 1 Equalizer De-serializer LBW 4.2MHz +/-1 Video Line FIFO House Synch Genlock P-clock Vertical Synch and Horizontal Synch Recovery Block P-clock V-Synch H-Synch Digital Multiplexor and FIFO Controller Digital Signal Processor Block Serializer LBW (129kHz - 1.4MHz) Input Channel 2 Equalizer De-serializer LBW 4.2MHz +/-1 Video Line FIFO Figure 6.5.1 Simplified Production Switcher Architecture Production switcher uses a combination of De-serializer/Serializer units and a source. The output jitter will be a function of the genlocked parallel clock and the serializer jitter, irrespective of the input jitter. Since the internal parallel clock is not derived from the input data, it may momentarily drift from the input data alignment. If there is not sufficient amount of data buffer, it could cause bit errors. Generally De-serializer/Serializer units have a latency in the order of 1 video line, thus 1 line worth of FIFO is used in a production switcher. This FIFO also takes care of the momentarily drift of the internal parallel clock. The jitter of the production switcher should be characterized just like a video source (Section 6.1) because the output is referenced to the house synch. 7 Miscellaneous Tips on PLL Based System Design The paper has shown several configurations of video equipment which may be encountered in the studio. One element common to most of the configurations is a PLL. The following design tips are useful in such systems. 1. Wider LBW PLLs are more immune to the board noise. It is the best choice when jitter filtering is not required, as in the case of a serializer when a clean parallel clock is available. However, phase detector noise may increase the total output jitter at high LBW. Therefore, the LBW should be optimized for the minimum output jitter. 20 page of 21

2. A regulated or filtered power supply should be used when designing low LBW circuits. Even VCXO based PLLs may require clean power supplies when a bandwidth around 1kHz at 0.2UI phase modulation is designed. 3. A loop-through output derived from a de-serializer may have jitter content up to 6MHz because of the higher LBW. If total jitter content increases more than the 0.4UI limit of a re-timer, it could cause errors. Thus, loop-through outputs should not be used for cascading units. If a loop-through output must be used as a cascading output, this signal should be re-timed with a lower LBW to provide a clean output. 8 Conclusion System level design considerations for various units used in a studio are presented in this paper. Time domain jitter is discussed to show the challenges presented by the pathological pattern in the SMPTE signal coding. It is demonstrated how slew PLL based units could achieve higher jitter attenuation without sacrificing robustness. It is also shown how it is possible to attain or even surpass the SMPTE jitter requirements if the designer optimizes the LBW selection. Acknowledgment The authors would like to thank J. Francis, T. Kapucija, E. Fankhauser and D. Lynch for their helpful advice and contributions. References 1. ANSI/SMPTE 292M-1996, Bit-Serial Digital Interface for High-Definition Television Systems. 2. ANSI/SMPTE 292M-1993, 10-Bit 4:2:2 Component and 4fsc Composite Digital Signals - Serial Digital Interface. 3. J. R. Waschura, Testing in Uncompressed HDTV Signals, 140 th Annual SMPTE Technical Conference and Exhibit, pp. 528-551, Oct 28-31, 1998. 4. A. Hajimiri, T. H. Lee, Low Noise Oscillators, Phase Noise and Jitter in Phase-Locked Loops, Kluwer Academic Publishers, pp. 166-178. 21 page of 21