UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop 3.2.6 Preset And Clear Inputs 3.2.7 Shift Register Check Your Progress 3.3 Binary Counter 3.3. Asynchronous Counter 3.3.2 BDC Counter 3.3.3 Synchronous Counter Check Your Progress 2 3.4 Summary 3.5 Glossary 3.6 References 3.7 Answers to Check Your Progress Questions
3. OBJECTIVES After going through this unit, you will be able to use logic gates to construct basic latches recognize the difference between a latch and a flip-flop explain how R-S and J-K flip-flops differ apply flip-flops in basic applications use flip-flops to construct a register explain the functions of an universal register describe the difference between an asynchronous and a synchronous counter analyze the counter timing diagrams determine the modulus of a counter modify the modulus of a counter 3. INTRODUCTION Digital circuits are divided into two categories - combinational and sequential. In combinational circuits the output at any instance of time depend upon the inputs present at that instance of time i.e., there is no memory in these circuits. In sequential circuits, the output at any instant of time depend upon the present inputs as well as past inputs and outputs i.e., these are elements used to store past information. These elements are known as memory. 3.2 SEQUENTIAL CIRCUITS There are two types of sequential circuits namely synchronous and asynchronous. A synchronous sequential circuit is a system where behavior can be defined from the knowledge of its signals at discrete instants of time. The behavior of an asynchronous sequential circuit depends upon the order in which its input signals change and can be affected at any instant of time. A flip-flop is a binary cell capable of storing one bit of information i.e., or. It has two outputs, one for normal value and other for the complement value of the stored bit. A flip-flop remains in a binary state ( or ) as long as it is not disturbed by any external sources. 3.2. NAND latch NAND latch (Figure 3.) is the fundamental building block in constructing a flip-flop. It has the property of holding on to any previous output, as long as it is not disturbed.
Figure 3. NAND latch The latch has two outputs Q and Q. When the circuit is switched on the latch may enter into any state. If Q=, then Q =, which is called SET state. If Q=, then Q =, which is called RESET state. Whether the latch is in SET state or RESET state, it will continue to remain in the same state, as long as the power is not switched off. But the latch is not an useful circuit, since there is no way of entering the desired input. It is the fundamental building block in constructing flip-flops, as explained in the following sections. 3.2.2 R-S flip-flop: The basic flip-flop is a one bit memory cell that gives the fundamental idea of memory device. It constructed using two NAND gates. The two NAND gates N and N2 are connected such that, output of N is connected to input of N2 and output of N2 to input of N. These form the feedback path the inputs are S and R, and outputs are Q and Q. The logic diagram and the block diagram of R-S flip-fop with clocked input is shown in Figure 3.2. a) Logic diagram
b) Block diagram Figure 3.2 R-S flip-flop The flip-flop can be made to respond only during the occurrence of clock pulse by adding two NAND gates to the input latch. So synchronization is achieved. i.e., flip-flops are allowed to change their states only at particular instant of time. The clock pulses are generated by a clock pulse generator. The flip-flops are affected only with the arrival of clock pulse. Operation:. When CP= the output of N3 and N4 are regardless of the value of S and R. This is given as input to N and N2. This makes the previous value of Q and Q unchanged. 2. When CP= the information at S and R inputs are allowed to reach the latch and change of state in flip-flop takes place. 3. CP=, S=, R= gives the SET state i.e., Q=, Q =. 4. CP=, S=, R= gives the RESET state i.e., Q=, Q =. 5. CP=, S=, R= does not affect the state of flip-flop. 6. CP=, S=, R= is not allowed, because it is not able to determine the next state. This condition is said to be a race condition. In the logic symbol CP input is marked with a triangle. It indicates the circuit responds to an input change from to. The characteristic table gives the operation conditions of flip-flop. Q (t) is the present state maintained in the flip-flop at time t. Q (t+) is the state after the occurrence of clock pulse. Truth table S R Q (t+) Comments Q t * No change Reset / clear Set Not allowed
3.2.3 D flip-flop: The D flip-flop is the modified form of R-S flip-flop. R-S flip-flop is converted to D flipflop by adding an inverter between S and R and only one input D is taken instead of S and R. So one input is D and complement of D is given as another input. The logic diagram and the block diagram of D flip-fop with clocked input are shown in Figure 3.2. a) Logic diagram b) Block diagram Figure 3.2 D flip-flop When the clock is low both the NAND gates (N and N2) are disabled and Q retains its last value. When clock is high both the gates are enabled and the input value at D is transferred to its output Q. D flip-flop is also called Data flip-flop. Truth table CP D Q x Previous state
3.2.4 J-K flip-flop The race condition in RS flip-flop, when R=S= is eliminated in J-K flip-flop. There is a feedback from the output to the inputs. Figure 3.4 represents one way of building a JK flip-flop. a) Logic diagram Truth table b) Block diagram Figure 3.4 J-K flip-flop J K Q (t+) Comments Q t Q t No change Reset / clear Set Complement/ toggle. The J and K are called control inputs, because they determine what the flip-flop does when a positive clock edge arrives.
Operation:. When J=, K= then both N3 and N4 will produce high output and the previous value of Q and Q retained as it is. 2. When J=, K=, N3 will get an output as and output of N4 depends on the value of Q. The final output is Q=, Q = i.e., reset state 3. When J=, K= the output of N 4 is and N 3 depends on the value of Q. The final output is Q= and Q = i.e., set state 4. When J=, K= it is possible to set (or) reset the flip-flop depending on the current state of output. If Q=, Q = then N4 passes to N2 which produces Q =, Q= which is reset state. When J=, K=, Q changes to the complement of the last state. The flip-flop is said to be in the toggle state. 3.2.5 Edge triggered RS flip-flop: Some flip-flops have an RC circuit at the input next to the clock pulse. By the design of the circuit the R-C time constant is much smaller than the width of the clock pulse. So the output changes will occur only at specific level of clock pulse. The capacitor gets fully charged when clock pulse goes from low to high. This change produces a narrow positive spike. Later at the trailing edge it produces narrow negative spike. This operation is called edge triggering, as the flip-flop responds only at the changing state of clock pulse. If output transition occurs at rising edge of clock pulse ( ), it is called positively edge triggering. If it occurs at trailing edge ( ) it is called negative edge triggering. Figure 3.5 shows the logic and block diagram. a) Logic diagram of edge triggered RS flip-flop
b) Block diagram of positive edge triggered flip-flop c) Block diagram of negative edge triggered flip-flop Figure 3.5 Edge triggered RS flip-flop 3.2.6 PRESET and CLEAR inputs Flip-flops available in IC packages will sometime provide a special input terminal for setting or clearing the flip-flop whenever needed. This is useful for bringing the flip-flop to the initial state before starting the operation. For this we add two AND gates to the latch with PRESET and CLEAR inputs. When PRESET= then whatever may be the other input the flip-flop is set (i.e.) Q=. When CLEAR= the output Q= (i.e.) clear state. The flip-flop will return to the active state only when PRESET= and CLEAR=. Figure 3.6 shows the logic and block diagram of flip-flop with PRESET and CLEAR inputs a) Logic diagram
b) Block diagram Figure 3.6 D flip-flop with PRESET and CLEAR Truth table PRESET CLEAR CP D Q X X X X X X X X X *(forbidden) NC NC NC Propagation delay time (t p ) It is the time taken by the output of a gate or flip-flop to change its status. Setup time (t setup ): It refers to the minimum amount of time that the data bit must be present before the clock edge strikes. Hold time(t hold ): It is the minimum amount of time the data bit must be present after the clock edge has struck.
3.2.7 Shift Register A flip-flop can store -bit of digital information. It is also referred to as a -bit register. A register contains a group of flip-flops, the number of flip-flops in a register being equal to the number of bits present in the data. Flip-flops are connected in such a way that binary number can be entered into the register and retrieved from the same. A register capable of shifting its binary information either to the right or to the left is called a Shift register. Shift registers are classified into the following types depending on the way in which the data is entered and retrieved..serial-in Serial-out(SISO) 2.Serial-in Parallel-out(SIPO) 3.Parallel-in Serial-out(PISO) 4.Parallel-in Parallel-out(PIPO) Serial-in Serial-out (SISO) Consider a shift register with two flip-flops as shown in the Figure 3.7, Figure 3.7 SISO Shift Register To set an in a flip-flop A, hold the J input high and K input low and allow the clock to progress through one cycle. To set in flip-flop A hold the J input low and K input high and allow the clock to progress through one cycle. Anytime a exists in flipflop A will be shifted to B during the next cycle of the clock. Similarly anytime a in flip-flop A will be shifted to B during next clock cycle. Suppose if it is required to shift the binary number into the register it will be done in the following manner. First of all, the three flip-flops are cleared. Then for flip-flop A set the inputs as J= and K=. Thus (LSB) will be shifted into A during first clock pulse. In the mean time B and C will remain in the reset state.(i.e.) ABC= During the occurrence of the second pulse, make J= and K=. This resets flip-flop A. The in A will be shifted to B and C is still in the reset state (i.e.) ABC=.
During the occurrence of third pulse make J= & k= for flip-flop A, so that will be entered into A (MSB) and in A will be shifted to B and in B will be shifted to C. i.e. ABC =. This can be summarized in the truth table as follows. Truth table Its corresponding waveforms and logic diagram are shown in Fig.3.8 a) Wave forms b)logic diagram Figure 3.8 SISO Shift Register In this way data can be entered serially into the register. To retrieve the data the following procedure is adopted. Now LSB() of the data is available at C. By the application of the next clock pulse the 2nd bit B will come to C. Similarly by applying
one more pulse the MSB will be available at C. Thus by applying two more pulses the data will be retrieved bit by bit. Serial in Parallel out (SIPO) In a SIPO shift register the data will be entered in the same way as in SISO. The output is taken directly from the flip flops in parallel as shown in the Figure 3.9. At the end of the third pulse the data will be available at ABC = D2 D D Figure 3.9 SIPO Shift Register Parallel in Serial out (PISO) In a PISO shift register loading of data is done with the help of PRESET terminals as shown in the Figure 3.. When Load= data input operation is disabled. Figure 3. PISO Shift Register When Load =, the data inputs are entered through the NAND gates into the PRESET terminals of the flip-flops. Load line is enabled for parallel loading. It is always high so that the flip-flop will be either set or reset. Thus without any clock pulse all the bits are
loaded simultaneously into the register. For retrieving, the output is obtained at S OUT by the application of clock pulses. Parallel-in Parallel-out(PIPO) Figure 3. PIPO Shift Register Figure 3. shows the PIPO Shift Register. In this shift register loading is done as in PISO. For retrieving the data the output of A, B and C are taken as D2, Dand D respectively. Using the PIPO Shift Register it is possible to handle the data in any of the four ways discussed above. Hence it is also called an Universal Shift Register. CHECK YOUR PROGRESS. The invalid state of an S-R latch occurs when (a) S =, R = (b) S =, R = (c) S =, R = (d) S =, R = 2. The purpose of the clock input to a flip-flop is to (a) clear the device (b) set the device (c) always cause the output to change states (d) cause the output to assume a state dependent on the controlling inputs 3. For an edge-triggered D flip-flop, (a) a change in the state of an flip-flop occurs only at a clock pulse edge (b) the state that the flip-flop goes to depends on the D inputs
(c) the output follows the input at each clock pulse (d) all the above 4. A flip-flop is in the toggle condition when (a) J =, K = (b) J =, K = (c) J =, K = (d) J =, K = 5. A stage in a shift register consists of (a) a flip-flop (b) a word of storage (c) a byte of storage (d) four bits of storage 6. To serially shift a byte of data into a shift register, there must be (a) One clock pulse (b) one load pulse (c) eight clock pulses (d)one clock pulse for each in the data 7. To parallel load a byte of data into shift register with a synchronous load, there must be (a) one clock pulse (b) one clock pulse for each in the data (c) eight clock pulse (d) one clock pulse for each in the data 8. The group of bits is serially shifted into an 8-bit parallel output shift register with an initial state of. After two clock pulses, the register contains (a) (b) (c) (d) 3.3 BINARY COUNTER A counter is a register capable of counting number of clock pulses that have arrived at its clock input. They are used for counting number of occurrences of an event and are also useful for generating timing signals to control the sequence of operations in a computer. A counter that follows the binary number sequence is called a binary counter. They are two types of counters. i) Serial or Asynchronous Counter. ii) Parallel or Synchronous Counter. i) Serial or Asynchronous Counter: In an asynchronous counter the output change in one flip-flop is given as clock input to the next flip-flop. The clock input to one flip-flop is different from another. It requires minimum hardware but is very slow in operation. ii) Parallel or Synchronous Counter:
In a synchronous counter all the flip-flops receive the same clock pulse, so that they change their states at the same time. The hardware is increased, but it is faster than an asynchronous counter. 3.3.Asynchronous Counter (Ripple Counter) Flip-flops can be connected to get an binary counter, which counts the number of input triggers (clock pulses). Figure 3.2 shows such a counter with three flipflops. Figure 3.2 Asynchronous Counter The clock pulse drives A. The output of A drives B and the output of B drives C. All the J&K inputs are tied to +Vcc, which means J=K=. Each flip-flop will toggle with a negative transition at its clock input. This kind of a counter in which output of one flipflop drives the other is called a ripple or asynchronous counter (as trigger moves like a ripple in water). A has to change its state before it can trigger B and B has to change its state before it can trigger C. So the overall propagation delay time is the sum of the individual delays. The operation of the counter can be explained as follows. Initially all the flip-flops are reset to produce outputs by making use of the clear inputs. The output condition is CBA=. When the first clock pulse strikes, A changes its states from to. Since it is a positive change it will not trigger B. So the output is CBA=. For the second pulse A changes from to. Since it is a negative change it triggers B. So B changes from to. Since it is a positive change, it will not trigger C. Now output is CBA=. For the third pulse A changes from to and it will not trigger B. So the output is CBA=. In this manner the counter will count up to which is given in the following truth table. Truth table
C B A Count Decimal equivalent 2 3 4 5 6 7 8 2 3 4 5 6 7 Figure 3.3 Waveforms From the waveform shown in the Figure 3.3 it is clear that the counter can also be used as a frequency divider. The waveform at A is one half of the clock frequency. B is one fourth of the clock frequency and C is one eighth of the clock frequency. So using three flip-flops we are able to get 8[2 3 ] distinct states which can count up to the largest binary number equal to 7 [(2 3 -) = 7]. Mod-n counter The total number of counts or discrete states through which a counter can progress is given by 2 n, where n is the total number of flip-flops. The total number of states through which a counter can progress is said to be modulus of a counter. The counter which can count through 2, 4, 8, or 6 can be constructed easily by using the proper number of flip-flops. Sometimes it is required to construct a counter which can have modulus other than 2,4,8, or 6. In that case a smaller modulus counter is constructed from a larger modulus counter by skipping states. Such counters are said to have modified counts. The correct number of flip-flops is determined by choosing the lowest natural count (total number of states) which is greater than the desired modified count. For e.g. a mod-7 counter requires three flip-flops since 8 is the lowest natural count greater than the desired modified count of 7. Mod-7 Counter (Divide by 7 Counter)
Mod-7 counter has only 7 states. The nearest greater natural number for this counter is 2 3 =8. So we should take three flip-flops from which any one of the states can be skipped. The logic diagram of a mod-7 counter which makes use of feedback is shown in Figure3.4. Figure 3.4 Mod-7 Counter The working of the above circuit can be explained as follows. Imagine the circuit without a NAND gate. Now it will count from through l l l. To get a mod-7 Counter, we have to skip state, thereby reducing the count from 8 to 7. This can be done by giving all the outputs (i.e.) A, B and C to a NAND gate, the output of which is given to the clear inputs of all the flip-flops. So when A = B = C =, all the flip-flops will be cleared to s immediately as the counter advances to count the next state. Now one state is skipped so that the total number of states becomes equal to 7. Thus a mod-7 counter is obtained (from mod-8). The truth table and waveforms of a mod-7 Counter are shown in Figure 3.5. Truth table
Figure 3.5 Truth table and Waveforms 3.3.2 BCD Counter (Mod- Counter/Decade Counter) A BCD Counter counts through different states. It is constructed from a mod-6 counter, by skipping 6 states. The logic diagram is shown in the Figure 3.6. Figure 3.6BCD Counter In Figure 3.6 the six states from to are skipped by giving ABCD to clear inputs through a NAND gate, where A=, B=, C= and D= enables the clear inputs and clears all the flip-flops. Since it counts only states, it is called a mod- Counter or decade counter. Figure 3.7 shows the truth table and wave forms of a BCD Counter.
Truth table Figure 3.7 Truth table and Waveforms 3.3.3 Synchronous Counter (Parallel Counter) The ripple counter is easy to build but there is a limitation of to its highest operating frequency. Here each flip-flop has a delay time and these delays are additive so the propagation delay of the entire counter is the sum of the individual delays. This speed limitation can be overcome by the use of a synchronous or parallel counter. Because here each flip-flop is triggered by the clock and this makes simultaneously transition in all the flip-flops.
Mod-8 Parallel Binary Counter The circuit diagram of a mod-8 Parallel Counter is shown in the Figure 3.8. Figure 3.8 Mod-8 parallel Binary Counter All the three flip-flops are negatively edge triggered and both J&K inputs are tied to +Vcc. The flip-flop A changes state with each negative transition at the clock input. The output of the AND gate () goes high whenever the clock is high and A is high. Thus flip-flop B changes state with every other clock. The output of AND gate (2) goes high each time the clock is high and both A are B are high. Thus flip-flop A changes state with every fourth clock. It is found to have eight distinct states which represent a mod-8 parallel counter. The truth table and the wave forms are given in the Figure 3.9 Truth table C D A Count 2 3 4 5 6 7 Figure 3.9 Truth table and Waveforms of Parallel Binary Counter
CHECK YOUR PROGRESS 2. Asynchronous counters are known as (a) ripple counters (b) multiple clock counters (c) decade counters (d) modulus counters 2. Asynchronous counter differs from an synchronous counter in (a) the number of states in its sequence (b) the method of clocking (d) the type of flip-flops used (d) the value of the modulus 3. A 4-bit binary counter has a maximum modulus of (a) 6 (b) 32 (c) 8 (d) 4 4. A BCD counter is an example of (a) a full-modulus counter (c) a truncated-modulus counter (b) a decade counter (d) answers (b) and (c) 3.4 SUMMARY Latches are bistable devices whose state normally depends on asynchronous inputs. Edge-triggered flip-flops are bistable devices with synchronous inputs whose state depends on the inputs only on the triggering transition of a clock pulse. Asynchronous and synchronous counters differ only in the way in which they are clocked. Synchronous counters can run at faster clock rates than asynchronous counters. The maximum modulus of a counter is the maximum number of possible states and is a function of number of flip-flops. 3.5 GLOSSARY Asynchronous counter : A type of counter in which each stage is clocked from the output of the preceding stage. Clock : The basic timing signal in a digital system Decade counter : A digital counter having ten states. Flip-flop : A basic storage circuit that can store only one bit at a time. Latch : A bistable digital circuit used for storing a bit
Preset : An asynchronous input used to set a flip-flop Ripple counter : An asynchronous counter. Synchronous counter : A type of counter in which each stage is clocked by the same pulse. Toggle : The action of a flip-flop when it changes state on each clock pulse. Trigger : A pulse used to initiate a change in the state of a logic circuit. Universal shift register : A register that has both serial and parallel input and output capability 3.6 REFERENCES. Moris Mano, Digital Computer Fundamentals TMH 3 rd Edition 2. Thomas C Bartee Computer Architecture and Logic and logic Design TMH 3. Malvino and Leech Digital Principles and Applications, TMH 4. Thomas L.Floyd Digital fundamentals Pearson Education 8 th Edition 3.7 ANSWERS TO CHECK YOUR PROGRESS QUESTIONS Check your progress.(c) 2.(d) 3.(d) 4.(b) 5.(a) 6.(c) 7.(a) 8.(c) Check your progress 2. (a) 2.(b) 3.(a) 4.(b)