DDR2 Application Note

Similar documents
User s Guide DDR2 Compliance Test

System-Level Timing Closure Using IBIS Models

Versatile IO Circuit Schemes for LPDDR4 with 1.8mW/Gbps/pin Power Efficiency. Kyoung-Hoi Koo

DM Segment Decoder/Driver/Latch with Constant Current Source Outputs

DM Segment Decoder/Driver/Latch with Constant Current Source Outputs

Document Part Number: Copyright 2010, Corelis Inc.

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Circuit Analysis

MT8812 ISO-CMOS. 8 x 12 Analog Switch Array. Features. Description. Applications

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT /12/14 BIT 10 TO 105 MSPS ADC

Model 5240 Digital to Analog Key Converter Data Pack

Nan Ya NT5DS32M8AT-7K 256M DDR SDRAM

DM Segment Decoder Driver Latch with Constant Current Source Outputs

Model 5250 Five Channel Digital to Analog Video Converter Data Pack

MT x 12 Analog Switch Array

ASNT_PRBS20B_1 18Gbps PRBS7/15 Generator Featuring Jitter Insertion, Selectable Sync, and Output Amplitude Control

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT /12/14 BIT 10 TO 65 MSPS DUAL ADC

64CH SEGMENT DRIVER FOR DOT MATRIX LCD

MT8806 ISO-CMOS 8x4AnalogSwitchArray

Model CMX3838A2 AV Matrix Switch with DSP audio (firmware 1.0)

DEM B SBH-PW-N (A-TOUCH)

DP8212 DP8212M 8-Bit Input Output Port

CDK3402/CDK bit, 100/150MSPS, Triple Video DACs

IS43/46R16800E, IS43/46R32400E

MT8814AP. ISO-CMOS 8 x 12 Analog Switch Array. Features. -40 to 85 C. Description. Applications

S6B CH SEGMENT DRIVER FOR DOT MATRIX LCD

74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Procedure for DDR Clock Skew and Jitter Measurements

DX-10 tm Digital Interface User s Guide

LMH0344 3Gbps HD/SD SDI Adaptive Cable Equalizer

EMERGING DISPLAY CUSTOMER ACCEPTANCE SPECIFICATIONS 32F00(CCFL TYPES) EXAMINED BY : FILE NO. CAS ISSUE : FEB.16,2000 TOTAL PAGE : 10

DS2176 T1 Receive Buffer

DM74LS377 Octal D-Type Flip-Flop with Common Enable and Clock

Designing High Performance Interposers with 3-port and 6-port S-parameters

FE-I4B wafer probing. ATLAS IBL General Meeting February David-Leon Pohl, Malte Backhaus, Marlon Barbero, Jörn Große-Knetter.

64CH SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION FEATURES 100 QFP-1420C

UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN

NT Output LCD Segment/Common Driver NT7701. Features. General Description. Pin Configuration 1 V1.0

psasic Timing Generator

LX3V-4AD User manual Website: Technical Support: Skype: Phone: QQ Group: Technical forum:

Hello and welcome to this training module for the STM32L4 Liquid Crystal Display (LCD) controller. This controller can be used in a wide range of

IS43/46R83200F IS43/46R16160F IS43/46R32800F

ASNT8140. ASNT8140-KMC DC-23Gbps PRBS Generator with the (x 7 + x + 1) Polynomial. vee. vcc qp. vcc. vcc qn. qxorp. qxorn. vee. vcc rstn_p.

V54C3128(16/80/40)4VB*I 128Mbit SDRAM, INDUSTRIAL TEMPERATURE 3.3 VOLT, TSOP II / FBGA 8M X 16, 16M X 8, 32M X 4

C8491 C8000 1/17. digital audio modular processing system. 3G/HD/SD-SDI DSP 4/8/16 audio channels. features. block diagram

User s Guide DDR3 Compliance Test

Special Applications Modules

FM25F01 1M-BIT SERIAL FLASH MEMORY

Agilent U7233A DDR1 Compliance Test Application

Product Specification PE4151

LM16X21A Dot Matrix LCD Unit

RGB-3400-X RGB SEQUENCER / 3-CHANNEL UNIVERSAL LED DIMMER

74F273 Octal D-Type Flip-Flop

Video Filter Amplifier with SmartSleep and Y/C Mixer Circuit

DEM N1 TMH-PW-N

Agilent N6465A emmc Compliance Test Application

V6118 EM MICROELECTRONIC - MARIN SA. 2, 4 and 8 Mutiplex LCD Driver

INTEGRATED CIRCUITS DATA SHEET. TDA4510 PAL decoder. Product specification File under Integrated Circuits, IC02

OWL micro+ WIRELESS ELECTRICITY MONITOR

Model 6010 Four Channel 20-Bit Audio ADC Data Pack

UNISONIC TECHNOLOGIES CO., LTD 89CXX/89NXX Preliminary CMOS IC

JRC ( JTAG Route Controller ) Data Sheet

DDR3 SDRAM REGISTERED DIMM MODULE,1.5V 8GByte - 1GX72 AVF721GR64F7066G7-BP

ASNT8142-KMC Generator of DC-to-23Gbps PRBS with Selectable Polynomials

FMS3810/3815 Triple Video D/A Converters 3 x 8 bit, 150 Ms/s

Octal 3-State Bus Transceivers and D Flip-Flops High-Performance Silicon-Gate CMOS

WizFi250 Datasheet. Introduction. Features. WizFi250 Datasheet v English. Datasheet History

ML6428. S-Video Filter and 75Ω Line Drivers with Summed Composite Output. Features. General Description. Block Diagram Σ BUFFER.

Agilent N5413A DDR2 Compliance Test Application

82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

A/D and D/A convertor 0(4) 24 ma DC, 16 bits

LCD MODULE DEM B SYH

MMI: A General Narrow Interface for Memory Devices

CMD197C GHz Distributed Driver Amplifier

"shell" digital storage oscilloscope (Beta)

RSL MusicPower Plug-In Installation Manual For Naim NAC 72 Preamp

74F574 Octal D-Type Flip-Flop with 3-STATE Outputs

Design of Fault Coverage Test Pattern Generator Using LFSR


CLC011 Serial Digital Video Decoder

V54C3256(16/80/40)4VH 256Mbit SDRAM 3.3 VOLT, TSOP II PACKAGE 16M X 16, 32M X 8, 64M X 4

SMG12864A LCM SPECIFICATION

HCF4027B DUAL J-K MASTER SLAVE FLIP-FLOP

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION 100 QFP

LAB #6 State Machine, Decoder, Buffer/Driver and Seven Segment Display

SDA 3302 Family. GHz PLL with I 2 C Bus and Four Chip Addresses

Debugging Memory Interfaces using Visual Trigger on Tektronix Oscilloscopes

3500/72M Rod Position Monitor

FM25F04A 4M-BIT SERIAL FLASH MEMORY

Spring Probes and Probe Cards for Wafer-Level Test. Jim Brandes Multitest. A Comparison of Probe Solutions for an RF WLCSP Product

LCD MODULE DEM B SYH-PY

74F377 Octal D-Type Flip-Flop with Clock Enable

DPS-250AB-18 E. 電氣規格 (Electrical Specification) REV. Description Date DESCRIPTION : MODEL NO. : Date Drawn Desing(EE) Design(ME) DOCUMENT NO. : REV.

Obsolete Product(s) - Obsolete Product(s)

DUAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH LOW POWER CONSUMPTION

IQORX30 / IQORX31. Single Mode Fiber Optic Receivers for 3G/HD/SD-SDI Signals

C8188 C8000 1/10. digital audio modular processing system. 4 Channel AES/EBU I/O. features. block diagram. 4 balanced AES inputs

NT7108. Neotec Semiconductor Ltd. 新德科技股份有限公司 NT7108 LCD Driver. Copyright: NEOTEC (C)

Model 5405 Dual Analog Sync Generator Data Pack

AD9884A Evaluation Kit Documentation

C8000. sync interface. External sync auto format sensing : AES, Word Clock, Video Reference

Transcription:

DDR2 ODT(On Die Termination) Control March 2006 Engineering Team MEMORY DIVISION SAMSUNG ELECTRONICS Co., LTD

DDR2 ODT (On Die Termination) On board termination resistance is integrated inside of Motherboard Termination(MBT) On Die Termination (ODT) Controller Slot Slot On Board termination Vtt Controller Slot Slot

On Die Termination On/Off Control ODT turn on/off is controlled by ODT pin One ODT control pin per : Turn-on or Turn-off control Two ODT control pin per DIMM to support rank by rank control But in most application, one ODT pin per slot is being used DDR2 Rtt ODT On/Off Control ODT high active ODT turn-on period SW Controller ODT pin CK ODT ODT On ODT Off Input buffer Input pin Source DQ, DQS, DQS#, RDQS, RDQS# tis setup time ODT turn on delay time taond = 2*tCK taofd = 2.5*tCK ODT turn off delay time

On Die Termination Value Selection should be determined during power-up by EMRS SW2 SW1 300 ohm 300 ohm 300 ohm VDD Address Field A9 A8 A7 A6 BA1 0 0 1 1 A5 BA0 0 1 0 1 A4 MRS Mode MRS EMRS(1) EMRS(2) EMRS(3) : Reserved A3 A2 A1 A0 SW1 SW2 300 ohm 300 ohm 300 ohm Control Circuit VSS DQ, DQS, DM Pin ODT Pin OCD program EMRS(1) Rtt A6 0 0 1 1 Additive latency Rtt D.S A2 Rtt (Nominal) 0 ODT Disabled 1 0 1 DLL SW1 on ODT on SW2 on

Test Condition for ODT Verification Capacitance Specification for DDR2-667 & 800 Parameter DDR2-667/DDR2-800 MIN MAX UNIT Input capacitance CK, /CK 1.0 2.0 pf Input capacitance Delta, CK, /CK - 0.25 pf Input capacitance C/A 1.0 2.0 pf Input capacitance Delta, C/A - 0.25 pf Input capacitance DQ/DM/DQS 2.5 3.5 pf Input capacitance Delta, DQ/DM/DQS - 0.5 pf

ODT Case Study @DDR2-667 Writes For two slot population, 50ohm seems to be better than 75ohm in term of signal integrity For one slot population, even 150ohm seems O.K. 2R X X 2R 1R X X 1R

ODT Case Study @DDR2-800 Writes For two slot population, 50ohm seems to be better than 75ohm in term of signal integrity For one slot population, even 150ohm seems O.K. 2R X X 2R 1R X X 1R

Recommended ODT Control - Writes Termination Matrix for Writes to Configuration 2R Empty Empty 2R 1R Empty Empty 1R Write To Controller Target DQ ODT Resistance RTT Module in Module in Rank 1 Rank 2 Rank 1 Rank 2 75 or 75 or 75 or Unpopulated 75 or Unpopulated Unpopulated 75 or 75 or Unpopulated Unpopulated 75 or Unpopulated 75 or Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated ODT on a controller always turned-off Example : (write to ) R1 R2 R1 R2 Vtt Memory Controller 75 or Slot 1 Slot 2

ODT Case Study @DDR2-667 Reads For two slot population, either 75ohm or 50ohm could be O.K. 50ohm does not help on reads that much For one slot population, even 150ohm seems O.K. 2R X X 2R 1R X X 1R

ODT Case Study @DDR2-800 Reads For two slot population, either 75ohm or 50ohm could be O.K. 50ohm does not help on reads that much For one slot population, even 150ohm seems O.K. 2R X X 2R 1R X X 1R

Recommended ODT Control - Reads Termination Matrix for Reads to Configuration 2R Empty Empty 2R 1R Empty Empty 1R Read from Controller Target DQ ODT Resistance RTT Module in Module in Rank 1 Rank 2 Rank 1 Rank 2 75 or 75 or 75 or Unpopulated 75 or Unpopulated Unpopulated 75 or 75 or Unpopulated Unpopulated 75 or Unpopulated 75 or Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated Unpopulated ODT on a controller always turned-on Example : (Read from ) R1 R2 R1 R2 Vtt Memory Controller 75 or Slot 1 Slot 2

Summary of ODT Control should be decided depending on channel environment and set during initialization sequence For one slot/channel implementation, 150ohm seems O.K. For two slots/channel implementation, need to be determined properly For DDR2-400/533, 75ohm seems O.K. For DDR2-667/800, 50ohm is better than 75ohm ODT trun-on/off is controlled by ODT pin There re more possible termination methods, but not covered in this material For example, 37.5ohm termination is possible with both ODTs turned-on on a dual rank DIMM, which may result better signal integrity, but relatively small voltage swing and more power consumption.