TM Enabling Analog Integration Paul Kempf
Overview The New Analog Analog in New Markets Opportunity in Integrated Analog/RF Outsourcing Trends in Analog Enabling Functional Integration Technology Requirements Requirement for Analog / RF Foundry 2
Digital Integration Drives More Analog Interfaces ANALOG ANALOG DIGITAL DIGITAL Analog Modem Analog Modem Ethernet (DSL / Cable) Analog Modem Ethernet (DSL / Cable) WLAN 802.11b Analog Modem Ethernet (DSL / Cable) WLAN 802.11a/b/g Bluetooth WiMax, UWB 3
Integrated Functions for Added Value Digital Integration CMOS process scaling enable high gate counts for digital SoC Analog Integration Limited by available technology Analog sub-systems have emerged OPPORTUNITY Mixer LNA MPU Filter Memory DSP ADC DAC Filter VCO/ Synth Driver PA Mixer Power Management Power Control Switch Filters 4
System in a Package (SiP) Progress Pin Count Through-Hole Area Array Through- Hole DIP SIP SDIP ZIP PGA Quad-Leaded Surface Mount QFP LQFP TQFP SOP SOJ TSOP SSOP TSSOP Leaded Surface Mount Area Array BGA FBGA TBGA TFBGA SCSP MCM SiP MCM/SiP Custom Discretes Memory Passives in Package Digital Integration Digital Chip (Moore s Law) RF/Analog (Analog Integration) Analog Integration Time Source: Semico 5
SiP Growth as the Leading Indicator SiP Packaging Sales (Units in Millions, Dollars in Million$US) 1,800 $0.80 1,600 $0.70 1,400 $0.60 Units and Dollars 1,200 1,000 800 600 Units Dollars ASP $0.50 $0.40 $0.30 ASP 400 $0.20 200 $0.10 0 2001 2002 2003 2004 2005 2006 2007 $0.00 Source: Semico 6
Outsourcing to Reduce Cost Total Wafer Sales Standard CMOS 1993 2002 2005 6% 19% 28% $37B $52B $77B Advanced Analog/RF (Specialty) 2% $1B 10% 18% $2.7B $4.8B Source: IC Insights Foundry 7 IDM
Analog/RF Functions Increasing Cell Phone Example Multi-band world phones Computing/communications convergence Specialty Silicon Power Amplifier WCDMA 3G WLAN GPS GSM 2.5G Bluetooth TV Tuner Expanding features Camera Sensor Mixed Signal Greater need for integration Standard CMOS Memory Multimedia Processor Baseband Processor Analog/RF functions increasing in multiple consumer, wireless applications 8
Performance/Cost Optimization The Advantages of Focusing on Analog/RF Processes Smaller size Lower cost Addressing Both Digital and Analog Scaling Standard CMOS D A 0.35µm Jazz Specialty D A More features Predictable performance Digital Scaling D A A 0.25µm 0.18µm D A DA A 0.13µm Analog Scaling A Digital Analog 9
Modular Technology Enables Analog Sub-System Integration 2002 2003 2004 2005 0.35µm 0.25µm 0.18µm 0.13µm BiCMOS RF CMOS RF CMOS RF CMOS SiGe BiCMOS SiGe BiCMOS SiGe BiCMOS SiGe 2fF MIM Cap HV CMOS 6µm Inductor 4fF MIM Cap 6µm Inductor 4fF MIM Cap Power NPN HV MOS HV CMOS RF LDMOS V PNP Power NPN V PNP Direct Conversion Radio Low-Noise SiGe LNA Data Converters Power Amplifier Power Management Digital Control + + + Functional Scaling Rx Tx Rx Tx M/S Rx PA Tx M/S Rx Tx M/S PMIC PA PMIC 10
Example: Bipolar Modules 200 175 Ft (GHz) 150 125 100 75 SiGe 0.18 Improved Performance 50 SiGe 0.35 25 Si 0.35 0 0.01 0.1 1 10 Ic (ma) for Minimum We and Le=1um Reduced Power Consumption Analog technology can also provide performance/power consumption advantage 11
Power Amplifier Integration in SiGe BiCMOS Base Emitter Collector 1000 Higher Speed SBC18H2 Ft (GHz) 100 SBC18 Better Power Efficiency Collector Implant 10 SBC35 BC35 1 3 5 7 BVceo (V) 12
Power Integration in 0.18µm CMOS RF LDMOS Silicide Block 25 HV Drain 20 Vds = 5V Pwell P-Substrate High Performance Ft 20GHz Ron < 4 Ohm-mm BVdss > 15V Extended Drain MOS Ft (GHZ) 15 10 5 0 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 Id (A) Power Management Options N+ Pwell STI Nwell N+ Vgs 1.8 3.3 5 12 Vds 1.8 3.3 5 12 20 40 13
Vertical PNP Integration Push/Pull Amplifiers Hard Disk Drive (HDD) Pre-Amp and Driver ICs High-Performance Data Converters 0.35µm VPNP 0.18µm VPNP Peak Beta 50 50 Ft (Vce = -5V) 15 17 GHz BVceo -7-7 V 14
Ultra-High Performance: 200GHz SiGe BiCMOS 200/200GHz Ft and Fmax Shallow and Deep Trench Isolation SiGe epitaxial base (vertical scaling) Self-aligned emitter integration (lateral scaling) 15
Scaling Linear Capacitors 3 Sigma Mismatch (%) 1 0.1 0.01 0.001 2fF/µm 2 MIM Capacitor Performance Linear VCC - 40 ppm /V 2 Quadratic VCC 25 ppm/v Common Centroid 0.01 0.1 1 10 100 Capacitance (pf) Breakdown Voltage (V) 25 20 15 10 5 0 4.5-8 ff/µm 2 High K MIM 0 3 6 9 Capacitance Density (ff/mm2) 16
Integrated Inductors Inductor Scaling 1.E+06 3µm Top Metal Constant Q of 10 Area (µm 2 ) 1.E+05 1.E+04 6µm Top Metal 1.E+03 0 2 4 6 8 10 Inductance (nh) Thick metal to improve Q or reduce inductor area 17
Integrated MEMS MEMS Circuits Tunable capacitor RF Filter Reconfigurable VCO RF Switch Example: Tunable capacitor in VCO design courtesy Carnegie Mellon University 18
Example: RF/Analog SoC Products Single Chip TV Tuner The World s First with Integrated Tuner + DeMod Single chip SoC RF to Baseband IC Tuner and DeMod Integration Single Chip WLAN RF Solution The World s Most Integrated competing 3-chip solution Single chip 802.11b/g Transceiver, VCO PA integration competing 5-chip solution Single chip 802.11a/b/g Transceiver, LNA, VCO PA integration 19
Analog Foundry: Design Support Digital Libraries Analog Foundry AMS Design Platform Digital Foundry PDK Analog/RF Models Backend FA/Test/Yield Digital/MS IP Analog/RF IP Higher level of investment in design support required in an Analog Foundry 20
Scalable Models Physical scalable models for all devices to ensure accurate simulation GATE NF Design flexibility for optimum performance NS NWELL 21
Scalable RF Inductor Model Layout Input + Technology Parameters = RF Circuit Model Xsize S * * * * N=4 W Sheet Resistances Dielectric Constants Layer Thicknesses L4 R4 Port 1 L0 Rvia L3 R3 Port 2 L2 R2 Port 1 Port 2 * * * * L1 R1 Substrate Scalable model enables optimization of inductor area/performance 22
Statistical Modeling Infrastructure Implication of Process Variation Product Yield Process Parameters (e.g., Tox, Doping, CD) p f Device Parameters (e.g., Idsat, Vth, Beta, Ft) Circuit Performance (e.g., Gain, NF) VCC Product Performance (Yield, Sales) LN A XX102 $$$ 23
Wafer / Lot / Fab Specific Models Select wafer/lot/series of lots from Web site TAR file with specific model e-mailed to user User Un-TARs package Pull-down menu in Design Kit enables Ckt simulation 24
Enabling Functional Integration Pure-Play Play Foundry Streamlined Supply Chain Seamless Manufacturing Modular silicon technology Complete design platform Economies of scale Analog Foundry 25
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