Low-cost HDTV set-top box decoder for H.264 and Microsoft WMA9. SD video in USB 2.0. Digital video input. STBus

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Low-cost HDTV set-top box decoder for H.264 and Microsoft WMA9 Data Brief Features The is a single-chip, high-definition video decoder including: Microsoft VC-1, WMA9 and H.264 support Linux, Windows CE and OS21 compatible ST40 CPU core: 266 MHz transport filtering and descrambling video decoder: VC-1 (including WMA 9), H.264 (MPEG-4 part 10) and MPEG-2 SVP compliant Windows DRM support graphics engine and dual display: standard and high-definition audio decoder: including Windows Media Audio 9 (WMA-9) and WMA-9 Pro DVD data retrieval and decryption The also features the following embedded interfaces: USB 2.0 host controller/phy interface DVI/ output digital audio and video auxiliary inputs low-cost modem 100BT ethernet controller with integrated MAC and MII/RMII interface for external PHY serial ATA (SATA) ST40 core 266 MHz UDI 16 K Icache Int. control MMU 32 K Dcache 32 DDR SDRAM Video LMI 32 System LMI 5 x 2-ch PCM out S/PDIF AudioL AudioR 2-ch PCM in Audio decoder and interfaces ST231 core Audio DACs SD video in Digital video input Serial ATA interface USB 2.0 2x I/F SmCard 6x GPIO Peripheral I/O and external interrupts IR Tx/Rx ILC MAFE interface 4x UARTs PWM 3x SSCs STBus 2 x PDES PTI PTI TSmerger/router CP FDMA Clock generator and system services Ethernet, MII/RMII Video decoder VC-1 (inc WMV-9) H264/MPEG-2 ST231 core DVI-HDCP 2D gamma blitter Output stage DACs CUR 3 x GDP Display compositor DENC DACs DEI Main video display Aux video display EMI EMPI TSIN0 TSIN1 TS I/O NRSS-A MII/RMII for 100BT Ethernet TMDS main video output (HD) Main video output (HD) YPbPr Aux video output (SD) YC/CVBS or companion chip December 2006 Rev 2 1/9 For further information contact your local STMicroelectronics sales office. www.st.com 9

Description 1 Description The is a new generation, high-definition set-top box / DVD decoder chip, and provides very high performance for low-cost HD systems. includes both Windows Media Video 9 and H.264 video decoders for new, low bit rate applications. Based on the Omega2 (STBus) architecture, this system-on-chip is a full back-end processor for digital terrestrial, satellite, cable, DSL and IP client high-definition set-top boxes, compliant with ATSC, SMPTE VC-1, DVB, DIRECTV, DCII, OpenCable and ARIB BS4 specifications. It includes all processing for DVD applications. The demultiplexes, decrypts and decodes HD or SD video streams with associated multichannel audio. Video is output to two independently formatted displays: a full resolution display intended for a TV monitor, and a downsampled display intended for a VCR or DVD- R. Connection to a TV or display panel can be analog through the DACs, or digital through a copy protected DVI/. Composite outputs are provided for connection to the VCR with Macrovision protection. Audio is output with optional PCM mixing to an S/PDIF interface, PCM interface, or through integrated stereo audio DACs. Digitized analog programs can also be input to the for reformatting and display. The includes a graphics rendering and display capability with a 2D graphics accelerator, three graphics planes and a cursor plane. A dual display compositor provides mixing of graphics and video with independent composition for each of the TV and VCR/DVD-R outputs. The includes a stream merger to allow seven different transport streams from different sources to be merged and processed concurrently. Applications include DVR timeshifted viewing of a terrestrial program, while acquiring an EPG/data stream from a satellite or cable front end. The flexible descrambling engine is compatible with required standards including DVB, DES, AES and Multi2. The embeds a 266 MHz ST40-202 CPU for applications and device control. A dual DDR1 SDRAM memory interface is used for higher performance, to allow the video decoder the required memory bandwidth for VC-1/HD H.264 and sufficient bandwidth for the CPU and the rest of the system. A second memory bus is also provided for flash memory, storing resident software, and for connection of peripherals. This bus also has a high speed synchronous mode that can be used to exchange data between two devices. This can be used to connect a second as a co-decoder for a dual TV STB application. A hard-disk drive (HDD) can be connected either to the serial ATA interface, or as an expansion drive through the USB 2.0 port. For IP-TV applications, the integrated 100BT Ethernet controller and MII/RMII interface can be used for generic Ethernet delivery, as shown in Figure 4: Low-cost HD IP-TV set-top box with HDD on page 4. The USB or Ethernet interfaces can also be used to connect to a DOCSIS 2.0 CM gateway for interactive cable applications. The is supported by STMicroelectronics STAPI software, and is compatible with the STx7100 and STi7710. 2/9

Description Figure 1. Low-cost satellite HD set-top box 2 x 128 Mbit DDR1 2 x 128 Mbit DDR1 IR Tx/Rx QPSK Rx STV0299 +STi6000 Transport stream in RGB/YPbPr/ CVBS/YC PTSN MAFE Smart cards VCR Figure 2. Low-cost cable HD set-top box with return channel CableCARD interface 2 x 128 Mbit DDR1 2 x 128 Mbit DDR1 Broadcast Tuner and SAW filter STV0498B EMI IB data/ OOB Tuner and SAW filter Duplex filter Upstream PGA Cable front end QAM/QPSK transceiver IR Tx/Rx RGB/YPbPr/ CVBS/YC Smart cards RS232 VCR 3/9

Description Figure 3. Low-cost dual satellite and terrestrial HD set-top box with HDD and DVD HDD DVD optical interface chip 2xDDR1 IR Tx/Rx EMI SATA QPSK Rx STV0299 +STi6000 8VSB Rx DVB-CI RGB/YPbPr/ Tuner STV0370 RS232 PSTN MAFE Smart cards USB 2.0 HDD (expansion) Figure 4. Low-cost HD IP-TV set-top box with HDD HDD 2xDDR1 IR Tx/Rx EMI SATA Ethernet RJ45 PHY MII RGB/YPbPr/ RS232 Smart cards USB 2.0 HDD (expansion) 4/9

Description 1.1 Detailed features list 1.1.1 Processor subsystem ST40 32-bit superscaler RISC CPU 266 MHz, 2-way set associative 16-Kbyte ICache, 32-Kbyte DCache, MMU 5-stage pipeline, delayed branch support floating point unit, matrix operation support debug port, interrupt controller 1.1.2 Transport subsystem TS merger/router 2 serial/parallel inputs 1 bidirectional interface merging of 3 external transport streams transport streams from memory support NRSS-A module interface TS routing for DVB-CI and CableCARD modules Programmable transport interfaces (PTIs) two programmable transport interfaces two transport stream demultiplexers: DVB, DIRECTV, ATSC, ARIB, OpenCable, DCII integrated DES, AES, DVB and Multi2 descramblers NDS random access scrambled stream protocol (RASP) compliant NDS ICAM CA support for VGS, Passage and DVS042 residue handling 1.1.3 Video/graphics subsystem Microsoft VC-1 MP@HL (WMV 9) and AP@L3/H.264(MPEG-4 part 10) main and high profile level 4.1/MPEG-2 MP@HL video decoder advanced error concealment and trick mode support dual MPEG-2 MP@HL decode SD (standard package) or HD/SD (extended package) digital video input Displays one HD display multi format capable (1080I, 720P, 480P/576P, 480I/576I) - analog HD output RGB or YPbPr - encoded output one standard-definition display - analog SD output: YPbPr or YC and CVBS Gamma 2D/3D graphics processor triple source 2D gamma blitter engine alpha blending and logical operations color space and format conversion 5/9

Description fast color fill arbitrary resizing with high quality filters acceleration of direct drawing by CPU Gamma compositor and video processor 7-channel mixer for high definition output independent 2-channel mixer for SD output 3 graphic display planes high-quality video scaler motion and detail adaptive deinterlacer linear resizing and format conversions horizontal and vertical filtering Copy protection /HDCP copy protection hardware SVP compliant Macrovision copy protection for 480I, 480P, 576I, 576P outputs DTCP-IP AWG-based DCS analog copy protection 1.1.4 Audio subsystem Digital audio decoder support for all the most popular audio standards including WMA-9, WMA-9 Pro, MPEG-1 layer I/II, MPEG-2 layer II, MPEG-2 AAC, MPEG-4 AAC LC 2- channel/5.1 channel MPEG-4 AAC+SBR 2-channel/5.1 channel, Dolby Digital EX, Pro Logic II, MLP and DTS PCM mixing with internal or external source and sample rate conversion 6- to 2-channel downmixing PCM audio input independent multichannel PCM output, S/PDIF output and analog output Stereo 24-bit audio DAC for analog output IEC958/IEC1937 digital audio output interface (S/PDIF) CSS/CPxM copy protection hardware 6/9

Description 1.1.5 Interfaces External memory interface (EMI) 16-bit interface supporting ROM, flash, S, SRAM, peripherals access in 5 banks high speed synchronous mode for interconnecting two devices External microprocessor interface (EMPI) 32-bit MPX satellite, target-only interface, synchronous operation at MPX clock speed, capable of 100 MHz, Dual local memory interface (LMI) dual interface (2 x 32-bit) for DDR1 200-MHz (DDR400) memories, supports 128-, 256- and 512-Mbit devices USB 2.0 host controller/phy interface Serial ATA hard-disk drive support record and playback with trick modes pause and time shifting, watch and record 100BT Ethernet controller, MAC and MII/RMII On-chip peripherals 4 ASCs (UARTs) with Tx and Rx FIFOS, two of which can be used in smartcard interfaces 2 smartcard interfaces and clock generators (improved to reduce external circuitry) 3 SSCs for I²C/ SPI master slaves interfaces serial communications interface (SCIF) 2 PWM outputs teletext serializer and DMA module 6 banks of general purpose I/O, 3.3 V tolerant SiLabs line-side (DAA) interface modem analog front end (MAFE) interface infrared transmitter/receiver supporting RC5, RC6 and RECS80 codes UHF remote receiver input interface interrupt level controller and external interrupts, 3.3 V tolerant low power/rtc/watchdog controller integrated VCXO DiSEqC 2.0 interface PWM capture/compare functions Flexible multi-channel DMA 1.1.6 Services and package JTAG/TAP interface, ST40 toolset support, ST231 toolset support Two package options 35 x 35 PBGA, 580 + 100 balls (standard version) 35 x 35 PBGA 708 + 84 balls (extended version) 7/9

Revision history 2 Revision history Table 1. Document revision history Date Revision Changes 19-Dec-2006 2 Rewritten to include latest information and corrected product code. 10-Sep-2005 1 Initial release. 8/9

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