MEMS WAFER-LEVEL PROCESSES

MEMS WAFER-LEVEL PROCESSES Ken Gilleo PhD - Ken@T-Trends.com ET-Trends LLC West Greenwich, RI ABSTRACT MEMS could become a hallmark technology for the 21 st century. Ability to sense, analyze, compute, control and manufacture materials at chip-level can provide new and powerful products during this decade and far into the future. MEMS is about integration of electronics, mechanics, motion, light, sound, biology, chemistry, radio, video, and much more. While sensors are a large market today, MEMS also brings control including electrical, mechanical, optical, fluidic, and electromagnetic. MEMS is a vital enabler where convergence of technology and science will miniaturize devices and help these fields work in partnership. Continued success is assured because MEMS is a robust and well-supported member of the immense semiconductor industry. But there are challenges in fabrication, micro-assembly and packaging. The complete MEMS device can require assembly of several parts, especially for systems having internal cavities and fluid or gas channels. Several structural layers can be bonded together creating complex 3-dimensional parts that will later be singulated into tiny machines. Wafer-level packaging is not only feasible, it has been commercialized. Once the final release step is completed, movable parts are no longer protected by a surrounding sacrificial structure. The devices are now more fragile and very sensitive to contamination until they are packaged. A tiny particle can permanently immobilize a MEMS chip making contamination a major yield loss factor. One strategy, that is becoming increasingly popular, is to complete as many processes as practical at wafer-level. Many other WL processes will be implemented in the future. This paper will describe existing wafer-level processes and suggest new possibilities. Key words: MEMS, packaging, wafer-level MEMS TECHNOLOGY INTRODUCTION MEMS is nearly as mature as the IC, but as modern as Nanotechnology. MEMS deals with the integration of just about everything; motion, light, sound, molecules, bioagents, radio waves and computation in single chips to deliver extraordinary functionality. What s more, these added levels of integration translate to extreme density, but a different kind that can shrink motors, pumps, and even rocket engines down to the semiconductor scale. MEMS technology can literally build a machine on a chip! MEMS, the unification of mechanical, electrical and electronic subcomponents into an integrated system, may be the most important technology zone today. MEMS bridges a geometric and size gap that can connect nano-technology with macro-world products. We can also add optics and photonics to create the rapidly emerging subset MOEMS that is also called optical-mems. We now have a potent and versatile convergence of essentially from all the world's technologies onto and into a single remarkable chip. We can build minuscule, nearly invisible machines that perform the same mechanical, optical, electrical and electronic functions found in the complex, and often-massive machines from the macro-world. It s like shrinking every-day machines of our conventional world onto tiny chips. MEMS is becoming the embodiment of the tech cliché, Shrink the world onto a chip - the ultimate System on a Chip (SOP). Some products send and receive light beams, others detect specific molecules and some deal with several senses simultaneously. If the logic device is the brain, MEMS adds the eyes, noise, ears, touch, and other sensory input. But MEMS is also control - the hands and fingers since these devices can move their own components but also external objects. MEMS, and close kin Nanotech, can more than meet expectations for marvelous micro-machines during the next decade. The merging of motion, sensing and computation represents a major leap in technology. CHALLENGES But there are challenges! Processes are still evolving and there is no standard manufacturing technology yet. In fact, there are still several fundamentally different fabrication processes being used. While most can agree on how to fab a transistor, there are many ways to build 3D structures. Packaging is also an area of many issues with many different strategies. Packaging specialists will tell you that MicroElectroMechanical Systems (MEMS) package design and manufacturing represent the greatest challenge ever encountered by their industry. Not only are the newest MEMS devices small and complex, many types must communicate with the outside world by modes beyond just electrical input/output. Most of the long history of packaging has dealt with electronic I/Os. Now add to that, gases, fluids and even solids, and you can appreciate the increased complexity of MEMS packaging. 1

WAFER-LEVEL MEMS MEMS, like semiconductor electronics, begins in a waferlevel process that employs many of the same processes used to fabricate transistors. Most MEMS devices are made from a silicon wafer, but other materials can be used including pure metal. One strategy is to stay at WL throughout the entire fabrication process including packaging. MEMS often requires the assembly of parts and this is obviously most practical and cost-effective at wafer-level. While some companies, like Analog Devices, Inc., have successfully fabricated mechanics and electronics on the same chip (called imems ), others have applied different strategies that require parts to be joined at wafer-level. Many complex 3D structures, especially those with internal cavities, require assembly that may only be economically viable at wafer level. Wafer-level packaging, and prepackaging, is not only viable, it s being used in production by several companies. 3D FABRICATION There are a number of MEMS devices that have been designed and fabricated with internal structures and this type of device will become more popular as BioMEMS and MEMS medical products expand. The ability to create 3D structures without assembly is limited, but still impressive. MEMS etching processes require access to the areas where material, called sacrificial, is to be removed. Designs typically have access holes built into the surface parts to allow etchant to flow through and underneath. An internal chamber, closed to the outside, would be very difficult to make, and perhaps impossible, without fabricating parts and bonding them together. A cavity would thus be created by etching half cavities on two different wafers and bonding them together rather than attempt to bond individual pieces together. Most have viewed this as a wafer-level process. Although a large number of MEMS parts can be built from single wafers, more complex 3-dimensional structures require assembly. Figure 1 shows a small section of Texas Instruments Digital Light Processor (DLP) made up of movable mirrors (16μ x 16μ) with flow holes. BUILDING CHAMBERS AND PUMPS MEMS pumps have become increasingly popular since these devices can be valuable for miniaturized medical and analytical systems. The most common approach is to fabricate two halves of a chamber and fuse them together. This is an ideal wafer-level process. Figure 2 shows a more complex pump assembly from The UC-Berkeley. The present concept uses a MEMS component, but development can lead to a complete MEMS-level machine that can be assembled at wafer-level. Figure 2 Pump Based on MEMS components Ideally, the separate parts can be assembled at waferlevel and singulated after testing. However, complex systems may only be partially assembled at waferlevel at this point in development, or even assembled as discrete parts. The University of Florida, Shape Change Technology, and Memry Corp. are working on an implantable system for diabetics that contains a pump that would serve as a component of an artificial pancreas. The system would deliver controlled amounts of insulin as required, all automatically. The pump is shown in Figure 3 that could be developed into an all-mems, wafer-level assembled device in the future. Figure 1 TI DLP Section (center mirror removed) Figure 3 - Pump 2

JET ENGINES & ROCKET CHIPS The US government has supported several projects aimed at developing tiny rocket engines, perhaps for future use as attitude control for micro-satellites. Both MIT and Caltech have achieved initial success. The MIT rocket chip is shown in Figure 4. While rocket engines that have an exhaust opening might be built without wafer assembly, a precise and sophisticated engine, with feed lines, valves and even pumps, would require assembly, preferably at WL. Figure 6 MIT Turbine Blade Figure 4- MIT Micro-Rocket MIT has also been developing micro-gas turbines. The complexity of such a machine requires assembly of several components as shown in Figure 5 and Figure 6 shows the turbine blade. A future implementation could be a tiny electric generator that would run on more readily available fuels than even the most advanced fuel cell. Figure 5 MIT Gas Turbine PACKAGING The full-hermetic package was the original standard box for MEMS, but at a cost penalty. More recently, MEMS-specific packages have been developed and at least one novel design has been commercialized. MEMS accelerometers have successfully penetrated the consumer market, including game controllers, where low cost packaging is essential. Even though MEMS can be viewed as a semiconductor device, it has one special requirement found almost nowhere else. MEMS needs living space to allow movement. An accelerometer, for example, has movable inertiasensing beams that must be unencumbered. Conventional plastic package processing would cover and lock up the MEMS mechanical action while hermetic packaging allows the devices to operate freely. All may concur that overmolding or any kind of direct encapsulation would be bad since goop in the gears would result in non-functionality for the micro-mechanical chip. But not all agree on how to solve this MEMS packaging dilemma. Some will continue with traditional hermetic packaging until something better comes along or they sink under the cost burden. Others hope that thermoplastic injectionmolded cavity packages will become the costeffective solution. A third group believes in the allsilicon wafer-level approach. Interestingly, the last two approaches have been combined and are already being used commercially. The MEMS device, primarily inertial sensors, is being capped at waferlevel and then being enclosed in plastic packaging. Initially, the capped parts were overmolded since the cap prevented entry of plastic into the mechanical structure, but stress caused by epoxy shrinkage in some products led to the switch to cavity plastic packages. Next, we ll look at wafer-level capping. 3

Capping The idea of capping a chip to make an all-silicon package goes back at least 17 years. LSI filed a patent application for such a concept in 1988 for Integrated circuit chip sealing assembly that was granted a patent in 1990 1. The invention describes forming caps by etching a wafer and then bonding to a MEMS, or other type of wafer, followed by singulation. The patent also describes extending the chip bonding pads to allow wire bonding after capping. Figure 7, from the patent drawing, shows the construction. While the present process requires high cutting precision, it allows the MEMS chip to be wire bonded without rerouting the pads to the back of the die or through the cap. The wafer capping strategy also solves the problem of contamination during sawing that would otherwise require temporary protection of the surface. While conventional electronic wafers can be cleaned after singulation, MEMS devices can trap debris and also be damaged by cleaning fluids. A more recent ADI patent describes a method where the two wafers are sawn simultaneously 2. Figure 8 ADI Process Part 1 Figure 7 Early MEMS Capping Patent (modified) Several wafer-capping methods have been implemented over the past several years and one of the leaders is Analog Devices, Inc. who commercialized a process for inertial sensors a few years ago. Their process involves first etching cavities in a silicon wafer and then applying a bonding material to the resulting wall edges. The present bonding agent is glass frit that is screen printed so that only the wall edges are coated as shown in Figures 8-9. The frit is dried and fused prior to mating the cap wafer to the MEMS wafer. Once the two wafers are aligned, bonding is accomplished by heating the assembly to the glass frit fusion point of somewhat less than 500 o C. The bonded wafer pair is now ready to saw, but a special process is used to singulate that cap wafer in a way that exposes the bonding pads on the MEMS chips. If both wafers were sawn through and simultaneously singulated, the cap would cover the bonding pads. While it is possible to route the pads through the cap and to the surface, the ADI process uses a special cap design and etched pattern that allows the cap to be partially sawn so that cap material over the pad area is removed. A diamond saw is positioned so that the blade only cuts down as far as the etched notch in the caps as shown in Figures 8-9 while Figure 10 shows the cross-section of an actual part that was overmolded. Figure 9 ADI Process Part 2 Figure 10 Actual Capped & Molded Part Since the cap structure and selective sawing process result in a cap, that only covers the active area and not the bonding pads, the die can be wire bonded and handled almost like conventional die. While the capping concept has come a long way in providing the right MEMS package, more work is needed to achieve optimum general MEMS packaging. Many more cap-on-chip designs are sure to evolve like those from Motorola and other accelerometer makers. 4

One of the Motorola patents3 discloses a wafer-level capping process that provides a slot opening for wire bonding as shown in Figure 1. The cap is bonded to the substrate-device wafer by first applying glass frit to the cap wafer to create walls that are self-bonding with the application of sufficient heat. Figure 11- Motorola Capping - Wire Bonding Access Other capping concepts could further simplify MEMS packaging by using feed-through caps that eliminate wire bonding. While it is possible to create feed-through vias in MEMS chips, a simpler concept is to add them to the cap. The fused on cap would need to form electrical connections with the pads on the MEMS chip. After wafer sealing, the cap could be bumped, or some other 2nd-level interconnect structure could be formed. The wafer pair would then be singulated to yield all-silicon hermetic packages. One concept is shown in Figure 12. Figure 12 Cap with Connectivity Another approach is to adopt a new die stacking idea to MEMS capping that would allow smaller caps to be bonded to larger MEMS chips. This would eliminate the need for precision sawing of caps or having to create feed-through bonding structures. The concept would involve first etching cavities in the cap wafer. Then, a bonding agent, such as glass frit, would be applied and probably hardened, but this step could also be done after singulation. Other wafer-bonding methods could also be used. The ready-to-bond wafer is next singulated by traditional sawing methods. Alternatively, the cap wafer would first be sawn and then coated for bonding. The bonding agent would only be applied to the edges by known means. The sawn and coated wafer is now ready for expansion. The dicing tape is actually a highelongation elastomer that may have a dot-like pattern of adhesive instead of the normal continuous coating. The tape is next stretched, or expanded, using edge grippers, or other means, to pull outwardly until the desired die spacing is achieved as shown in Figure 13. The expanded wafer is then aligned with the MEMS wafer that will have die that are larger than the caps. The MEMS and cap array are then bonded together as shown in Figure 14. The final step is singulation of the MEMS wafer. Since the wafer cap was previously diced, only the MEMS wafer is sawn and the die are protected from debris by the cap. The singulated chips, now protected with caps, can be overmolded or placed into molded cavity plastic packages that do not require hermeticity. Figure 13 Cap Wafer Expansion Step 5

Figure 14 Cap & Singulate (ET-Trends) SUMMARY & CONCLUSIONS Prediction: MEMS will be a hallmark technology for the 21st century. The capability to sense, analyze, compute and control, all within a single chip, will provide new and powerful products during the next decade. While package challenges are substantial, progress is being made. Waferlevel assembly and packaging is ideal for MEMS from many perspectives. While simpler concepts have already been commercialized, expect more sophisticated and higher-value processes to be implemented in the near future. REFERENCES 1. Sahakian, V. K., U.S. Patent 4,907,065, March 1990. 2 Spooner, T. R., U.S. Patent 6,555,417, April 2003. 3. Adams, V. J., U.S. Patent 5,323,051, April 1994. For further information see; Gilleo, K., MOEMS the Word, Circuits Assembly, pp. 28-31, 33, 34, Nov. 2000. Gilleo, K., MEMS Packaging Solutions, pp. 49-50, 52-53, 55-56, EP & P, June 2000. Gilleo, K, MEMS/MOEMS Packaging, McGraw-Hill, New York 2005. 6