October 31, 2003 Texas Instruments TNETE2201 Ethernet Transceiver Circuit Analysis Table of Contents List of Figures...Page 1 Introduction...Page 4 Device Summary Sheet...Page 6 Top Level Diagram...Tab 1 Parallel / Serial Converter...Tab 2 Serial / Parallel Converter...Tab 3 Synchronous Detect...Tab 4 Receiver PLL...Tab 5 Transmitter PLL (Clock Multiplier)...Tab 6 PLL Lock Detector...Tab 7 Received Data Output Multiplexer...Tab 8 Input Buffers...Tab 9 Output Buffers...Tab 10 Power Up...Tab 11 Symbol and Signal Naming Conventions...Tab 12 Signal Cross-Reference...Tab 13 For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. F1.2
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Texas Instruments TNETE2201 Ethernet Transceiver Page 1 List of Figures 0.1.1 Package Markings 0.1.2 Package X-Ray 0.1.3 Pin Configuration 0.1.4 Die Markings 0.2.0 Die Photograph 0.2.1 Annotated Die Photograph 0.2.2 Die Architecture 0.3.0 Power Busing Architecture (top metal layer) 0.3.1 Power Busing Architecture (bottom metal layer) 0.3.2 Power Busing Architecture (polysilicon layer) 0.3.3 Detailed Power Busing Architecture 0.3.4 Layout of Power Busing (top metal layer) 0.4.0 Close-up of Guard Rings (metal layers removed) 0.4.1 FESEM Cross-Section of Guard Rings (silicon stain) 0.4.2 FESEM Cross-Sectional Guard Rings at Y-Y [1] (oxide stain) 0.5.0 FESEM Cross-Section of Decoupling Capacitance at Y-Y [2] (oxide stain) 0.6.0 Bipolar Transistor Definitions 0.7.0 ECL Flip-Flop 1 Definition 0.7.1 ECL Flip-Flop 2 Definition 0.7.2 ECL Flip-Flop 3 Definition 0.7.3 ECL Flip-Flop 4 Definition 0.7.4 ECL Latch Definition 0.7.5 ECL Inverter/Buffer Definition 0.7.6 ECL Complementary Level Shifter 1 Definition 0.7.7 ECL Complementary Level Shifter 2 Definition 0.7.8 ECL Single Level Shifter Definition 0.7.9 ECL 2:1 Multiplexer Definition 0.7.10 ECL NAND Definition 0.7.11 ECL XOR Definition 0.7.12 CMOS-ECL Level Shifter Definition 0.7.13 CMOS D Flip-Flop 1 Definition 0.7.14 CMOS D Flip-Flop 2 Definition 0.7.15 CMOS D Flip-Flop 3 Definition 0.7.16 CMOS D Flip-Flop 4 Definition 0.7.17 CMOS 2:1 Multiplexer Definition 0.7.18 CMOS XOR Definition 1.0.0 Top Level Diagram 2.0.0 Parallel/Serial Converter 2.1.0 10Bit Transmitter Register
Texas Instruments TNETE2201 Ethernet Transceiver Page 2 2.2.0 5:1 Transmitter MUX 2.3.0 TX Output Buffer 2.4.0 Transmitter Bias 3.0.0 Serial/Parallel Converter 3.1.0 10Bit Receiver Shift Register 3.1.1 Receiver Shift Register 3.2.0 Received Data Sense Amplifier 3.3.0 Comma Detector 3.5.0 Comma Detector Bias 4.0.0 Synchronous Detect 4.1.0 K28.5 Misalignment Detector 4.1.1 K28.5 Character Decoder 4.2.0 Data Realignment Decoder 4.3.0 Clock Stretch Register 4.4.0 RBC Divider 4.5.0 RBC/Test Multiplexer 4.6.0 SYNC Pulse Output 4.7.0 Synchronous Enable 5.0.0 Receiver PLL 5.1.0 RX Input Buffer 5.2.0 Data-in/Loop-back MUX 5.3.0 Phase Detector I and Data Retiming 5.4.0 Charge Pump I 5.5.0 Receiver PLL Filter 5.6.0 Voltage Controlled Oscillator I 5.6.1 VCO I Cell 5.7.0 Test Multiplexer 5.8.0 Phase Detector II 5.9.0 Charge Pump II 5.10.0 Recovered Clock Divider 5.10.1 Recovered Clock Divider (part I) 5.10.2 Recovered Clock Divider (part II) 5.10.3 Receiver Output Clocks 5.11.0 Receiver PLL BIAS 5.11.1 Receiver PLL Bias I 5.11.2 Receiver PLL Bias II 5.11.3 Receiver PLL Bias III 6.0.0 Transmitter PLL (Clock Multiplier) 6.1.0 Phase Detector III 6.2.0 Charge Pump III
Texas Instruments TNETE2201 Ethernet Transceiver Page 3 6.3.0 Transmitter PLL Filter 6.4.0 Voltage Controlled Oscillator II 6.4.1 VCO II Cell 6.5.0 Transmitter Clock Divider 6.6.0 Transmitter PLL BIAS 6.6.1 Transmitter BIAS I 6.6.2 Transmitter PLL Bias II 6.6.3 Transmitter BIAS III 7.0.0 PLL Lock Detector 7.1.0 Reference Clock LFSR 7.2.0 Reset Pulse Generator 7.3.0 Recovered Clock LFSR 7.4.0 Lock Counter 8.0.0 Received Data Output Multiplexer 9.0.0 Input Buffers 9.1.0 Input Buffer 9.2.0 {REFCLK} Input Buffer 9.3.0 {RESERVED} Input Buffer 9.4.0 TD Register Clocks Generator 9.5.0 Bias Generator 10.0.0 Output Buffers 10.1.0 Output Buffer 11.0.0 Power Up 11.1.0 Start-Up Timer 11.2.1 Power-Up Bias Generator 11.2.2 Receiver Bias A.1.0 Symbol Conventions A.2.0 Symbol Definitions - 1 A.2.1 Symbol Definitions - 2 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation