For Video Equipment MNS External Synchronization Control LSI for Color Video Cameras Overview The MNS is an external synchronization control LSI for color video cameras. When used in combination with a synchronizing signal generator (MN0NS or MN0PS), it provides external synchronization control for NTSC and PAL video systems. Features Synchronization of both the video camera and the VCR External synchronization inputs: Composite synchronizing signal and burst subcarrier External synchronization techniques Horizontal synchronization: phase-locked loop Vertical synchronization: reset technique Subcarrier synchronization: phase-locked loop Support for both NTSC and PAL systems Built-in feature for automatically switching between external and internal synchronization Built-in horizontal phase adjustment circuit Applications Color video cameras Pin Assignment SCPSW SCPSW N/P BGP GLBSC V SS V DD GLSYNC TEST f HP HPCO Xf H OSCI Xf H OSCO 0 (TOP VIEW) SOP0-P-0 0 f SC f SC OSCO f SC OSCI SOPCO V DD V SS TEST HBLK EXT/INT LSWCONT LSW VR Xf H SDB000BEM
MNS For Video Equipment Block Diagram f HP VR Xf H oscillator Monostable multivibrator fv V separation GLSYNC Phase comparator Phase comparator fh H separation Internal/external synchronization switch HBLK and BGP pulse generator N/P CK Line switch control pulse generator Shift register D EXT/INT HBLK 0 LSWCONT Xf H Xf H OSCO Xf H OSCI HPCO Line switch V DD V SS 0 V DD V SS Selector SCPSW SCPSW f SC generator 0 Gate 0 TEST TEST f SC f SC OSCO f SC OSCI SCPCO GLBSC BGP LSW
For Video Equipment MNS Pin Descriptions Pin No. Symbol Pin Name Function Description V DD Power supply "H" level (V) power supply for subcarrier circuits V SS Power supply "L" level (GND) power supply for subcarrier circuits V DD Power supply "H" level (V) power supply for synchronizing signal circuits V SS Power supply "L" level (GND) power supply for synchronizing signal GLSYNC External synchronizing signal input CLBSC External burst subcarrier input Horizontal synchronization input f HP Monostable multivibrator input Subcarrier input SCPSW Subcarrier phase SCPSW switch inputs LSW Line switch input N/P NTSC/PAL selection input HPCO Horizontal phase comparator output Xf H OSCI Oscillator input for the synchronization circuits Xf H OSCO Oscillator output for the synchronization circuits Xf H Clock output for synchronizing signal circuits circuits Input pin for composite synchronizing signal derived from video signal (reference for horizontal and vertical signals) Input pin for burst subcarrier signal derived from video signal (reference for subcarrier signals) Input pin for signal from synchronizing signal generator Pin for connecting CR circuit for adjusting delay for analog monostable multivibrator (thus adjusting horizontal phase) Input pin for signal from synchronizing signal generator Pin selecting which of the four phase signals generated from the signal goes to the phase comparator For a PAL system, supply the LSW signal from the synchronizing signal generator. For an NTSC system, keep this pin at "H" level. "H" level selects NTSC operation; "L" level, PAL operation. This pin is at "L" level when the signal, after passing through the monostable multivibrator, leads the rising edge of the HSYNC signal derived by separating off the horizontal component of the GLSYNC signal and is at "H" level when the signal lags. At all other times, it is in the high-impedance state. Clock oscillator pins for the synchronization circuits. Connect these pins to an inductor, capacitor, and variable capacitor. (The pins have built-in feedback resistors.) The circuit oscillates during external synchronization mode. The oscillation stops for internal synchronization mode. The oscillator frequency, Xf H is. MHz (0f H ) for NTSC and.0 MHz (f H ) for PAL. Clock output pin for synchronizing signal circuits. This pin provides the clock (Xf H ) for the external synchronization mode and stays at "L" level for the internal synchronization mode. Connect to the EX0f H I pin of the synchronizing signal generator for NTSC operation and to the EXf H I pin for PAL operation.
MNS For Video Equipment Pin Descriptions (continued) Pin No. Symbol Pin Name Function Description VR Vertical reset output This pin generates a vertical reset pulse for the V-SERATION interval detected in the GLSYNC signal. Connect it to the VR pin of the synchronizing signal generator. SCPCO Subcarrier phase comparator output f SC OSCI Oscillator input for subcarrier circuits f SC OSCO Oscillator output for subcarrier circuits f SC Subcarrier clock output In external synchronization mode, this pin provides the (f SC ) clock signal; in internal synchronization mode, it remains at "L" level. Connect this pin to the EXf SC I pin on the synchronizing signal generator. LSWCONT Line switch polarity During PAL operation, this pin emits an error detection control output EXT/INT Automatic internal/ external switching output BGP Burst gate pulse output 0 HBLK Horizontal blanking output TEST Test inputs 0 TEST This pin is at "L" level when the signal leads the GLBSC signal and is at "H" level when the signal lags. At all other times, it is in the high-impedance state. Clock oscillator pins for the subcarrier circuits. Connect these pins to a crystal oscillator, capacitor, and variable capacitor. (The pins have built-in feedback resistors.) The circuit oscillates during external synchronization mode. The oscillation stops for internal synchronization mode. The oscillator frequency, f SC, is. MHz for NTSC and. MHz for PAL. Clock output from subcarrier circuits. pulse if the LSW polarity is wrong, and the chip reverses the LSW polarity. During internal synchronization mode, this pin remains at "L" level. Connect this pin to the LSWCONT pin on the synchronizing signal generator. If the chip detects GLSYNC input, it switches to external synchronization mode and drives this pin at "H" level. Otherwise, it switches to internal synchronization mode and drives this pin at "L" level. Connect this pin to the EXT/INT pin on the synchronizing signal generator. These pulses have a width of. µs (NTSC) or. µs (PAL) and trail the rising edge of the HSYNC signal by. µs (NTSC) or. µs. They are generated for only 0 H to H (NTSC) or 0 H (PAL) after the VR pulse. These pulses have a width of. µs (NTSC) or. µs (PAL) and follow the rising edge of the HSYNC signal. Leave these test inputs open. (The pins include built-in pull-up resistors.)
For Video Equipment MNS Timing Chart. Horizontal synchronization block This block compares the phases of the HSYNC signal derived by separating off the horizontal component of the GLSYNC input and the signal from the synchronizing signal generator after it has passed through the monostable multivibrator. It is thus possible to adjust the horizontal phase by adjusting the CR integral circuit's time constant. GLSYNC HSYNC DELAY Timing chart for horizontal pulse phase comparison. Vertical synchronization block This block detects the V-SERATION interval in the GLSYNC input and generates a vertical reset (VR) pulse with 0. H of the start of that interval. It then issues no pulses for H (NTSC) or 0 H (PAL) after this VR pulse. GLSYNC VR.0µs (NTSC).µs (PAL).µs (NTSC).µs (PAL) Vertical reset pulse timing chart
MNS For Video Equipment. Subcarrier synchronization block This block converts the output from the synchronizing signal generator into four signals with the same frequency as the burst subcarrier, but different phases. In this phase-locked loop circuit, the phase of GLBSC is compared with the phase selected by bits (SCPSW and SCPSW). During PAL operation, if the LSW polarity is wrong, this block sends an error detection pulse (LSWCONT) to the synchronizing signal generator and reverses the LSW polarity. It also adjusts the relationship between fields through.. Oscillator blocks The Xf H and f SC oscillator blocks operate only during external synchronization mode. Connecting a variable capacitor creates voltage-controlled oscillators that generate the synchronization signal circuit clock (Xf H ) and subcarrier circuit clock (f SC ) for output to the synchronization signal generator.. Automatic internal/external switching block If it detects a minimum of ten edges from the GLSYNC input, this block switches the chip to the external synchronization mode and drives the EXT/INT pin at "H" level. If there are no edges in the GLSYNC input for 0 H, this block switches the chip to the internal synchronization mode and drives this pin at "L" level. HBLK and BGP plus generator GLSYNC HBLK BGP.µs (NTSC).µs (PAL).µs (NTSC).µs (PAL).µs (NTSC).µs (PAL) HBLK and BGP pulse timing chart There is an HBLK pulse for each H. BGP pulses are generated for only 0 H to H (NTSC) or 0 H (PAL) after the VR pulse.
For Video Equipment MNS Application Circuit Example. External synchronization for NTSC system V 0µF + V DD V DD V SS V SS EXf SC I SYNC SYNC f SC OSCI VP VP f SC OSCO BLK BLK SC CPV CPV BSC CP CP VPCO WBLK 0 WBLK EXT/INT BF BF CP SW TEST SW VR SW EX0f H I SW 0µF + 0 SCPSW f SC SCPSW f SC OSCO f SC OSCI N/P SCPCO BGP GLBSC V DD V SS V SS V DD TEST GLSYNC HBLK TEST EXT/INT f HP LSWCONT HPCO LSW Xf H OSCI VR Xf H OSCO Xf H X X pf 0pF 0pF + D D 0µF 0 0 0kΩ 0kΩ MN0NS Ω MNS 0pF pf 0kΩ kω 00pF + 0µF X,.MHz D to SV SK 000pF D D VBS Burst Sep. Sync Sep. 0kΩ 0kΩ kω 000pF kω+.µf SK
MNS For Video Equipment Application Circuit Example. External synchronization for PAL system V 0µF + 0µF + V DD V DD V SS V SS EXf SC I SYNC SYNC f SC OSCI VP VP f SC OSCO BLK BLK SC CPV CPV BSC CP CP VPCO WBLK 0 WBLK EXT/INT BF BF LSWCONT SCBLK LSW HPCO 000pF VR f H OSCI EXf H I f H OSCO Q 0 X X pf 0pF 0pF 0 SCPSW f SC SCPSW f SC OSCO f SC OSCI N/P SCPCO BGP GLBSC V DD V SS V SS V DD TEST GLSYNC HBLK TEST EXT/INT f HP LSWCONT HPCO LSW Xf H OSCI VR Xf H OSCO Xf H 0 + D D 0µF 0kΩ 0kΩ pf.kω 0kΩ 00pF kω pf MN0PS Q MNS pf SC 0pF 0pF 0kΩ kω 00pF D to SV Q to SK X,.MHz 000pF 0kΩ 0kΩ Ω +.µf 0µF D D Q D VBS Burst Sep. Sync Sep. kω 000pF kω +.µf
For Video Equipment MNS Package Dimensions (Unit: mm) SOP0-P-0 0.. 0. 0.±0. 0.. max..±0. 0.±0. 0. Note) The package of this product will be changed to the following lead-free type (SOP0-P-0D)..0 max..±0.
MNS For Video Equipment New Package Dimensions (Unit: mm) SOP0-P-0D (Lead-free package).0±0.0 (0.) (0.) 0.0. 0.0±0.0.0±0.0.00±0.0.0 max. 0.0±0.0.0±0.0 Seating plane 0. +0.0-0.0.0±0.0 0 to 0 0.0 min. Seating plane 0
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