Infineon HYB18T512160AF-3.7 DDR2 SDRAM Circuit Analysis

March 13, 2006 Infineon HYB18T512160AF-3.7 DDR2 SDRAM Circuit Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 Fax: 613.829.0515

Some of the information in this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. 2006 Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization's corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information.

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Table of Contents Introduction... Page 1 Brief Functional Description... Page 2 List of Figures... Page 5 Device Summary Sheet... Page 24 Top Level Diagram...Tab 1 Data Path...Tab 2 Address Path...Tab 3 Control Clocks...Tab 4 Voltage Generators...Tab 5 Row Redundancy...Tab 6 Column Redundancy...Tab 7 Test/Calibration Modes...Tab 8 Mode Registers...Tab 9 Self Refresh...Tab 10 Signal Cross-Reference List...Tab 11 Signal Naming Conventions...Tab 12 Report Evaluation...Tab 13

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 5 List of Figures 0.1.1 Package Markings 0.1.2 Package X-Ray 0.1.3 Die Markings 0.2.0 Die Photograph 0.2.1 Annotated Die Photograph 0.2.2 Die Architecture 0.2.3 Pin Configuration 0.2.4 Annotated X-Ray 0.3.0 Standard Cells Definition 0.3.1 Standard Cells Definition 0.3.2 Standard Cells Definition 0.3.3 Standard Cells Definition 0.3.4 Standard Cells Definition 0.3.5 Standard Cells Definition 0.3.6 Standard Cells Definition 0.3.7 Standard Cells Definition 0.3.8 Standard Cells Definition 0.3.9 Standard Cells Definition 0.3.10 Standard Cells Definition 0.3.11 Standard Cells Definition 0.3.12 Standard Cells Definition 0.3.13 Standard Cells Definition 0.3.14 Standard Cells Definition 0.3.15 Standard Cells Definition 0.4.0 Latch Definitions 0.4.1 Latch Definitions 0.4.2 Latch Definitions 0.4.3 Latch Definitions 0.4.4 Latch Definitions 0.4.5 Latch Definitions 0.5.0 Flip-Flop Definitions

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 6 0.5.1 Flip-Flop Definitions 0.5.2 Flip-Flop Definitions 0.5.3 Flip-Flop Definitions 0.5.4 Flip-Flop Definitions 0.5.5 Flip-Flop Definitions 0.5.6 Flip-Flop Definitions 0.5.7 Flip-Flop Definitions 0.5.8 Flip-Flop Definitions 0.5.9 Flip-Flop Definitions 0.5.10 Flip-Flop Definitions 0.5.11 Flip-Flop Definitions 0.5.12 Flip-Flop Definitions 0.5.13 Flip-Flop Definitions 0.5.14 Flip-Flop Definitions 0.5.15 Flip-Flop Definitions 0.5.16 Flip-Flop Definitions 0.5.17 Flip-Flop Definitions 0.5.18 Flip-Flop Definitions 0.5.19 Flip-Flop Definitions 0.5.20 Flip-Flop Definitions 0.5.21 Flip-Flop Definitions 0.5.22 Flip-Flop Definitions 0.5.23 Flip-Flop Definitions 0.5.24 Flip-Flop Definitions 0.6.0 Symbol Definitions for Delay Line Definitions 0.6.1 Symbol Definitions for Delay Line Definitions 0.6.2 Delay Line Definitions 0.6.3 Delay Line Definitions 0.6.4 Delay Line Definitions 0.6.5 Delay Line Definitions 0.6.6 Delay Line Definitions 0.6.7 Delay Line Definitions

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 7 0.6.8 Delay Line Definitions 0.6.9 Delay Line Definitions 0.6.10 Delay Line Definitions 0.6.11 Delay Line Definitions 0.6.12 Delay Line Definitions 0.6.13 Delay Line Definitions 0.6.14 Delay Line Definitions 0.6.15 Delay Line Definitions 0.6.16 Delay Line Definitions 0.7.0 Level Shifter Definitions 1.0.0 Top Level Diagram 2.0.0 Data Path 2.1.0 Memory Cell Access 2.1.1 Cells and Bitline Sense Amplifiers 2.1.2 Local Data Bus Access 2.1.3 Data Bus Sense & Drive 2.1.4 Data Bus Sense Amplifier 2.1.5 Data Bus Write Driver 2.2.0 Data Line Latches and Drivers I 2.3.0 Data Line Switch 2.4.0 Data Line Latches and Drivers II 2.5.0 Data Output Registers 2.5.1 Data Output Register 2.6.0 Data Output Buffers 2.6.1 Data Output Buffer 2.6.2 Data Output Driver 2.6.3 Pull-Up Strength Control 2.6.4 Pull-Down Strength Control 2.7.0 {DQ} Bus On-Die Termination 2.7.1 {DQ} On-Die Termination

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 8 2.7.2 Adjustable Termination Resistors 2.7.3 Resistor Value Control 2.8.0 Data Input Buffers 2.8.1 Data Input Buffer 2.9.0 Data Input Registers 2.9.1 Data Input Register 2.10.0 Read Multibit Test 2.10.1 Multibit Test Comparators 2.10.2 Multibit Test Logic I 2.10.3 Multibit Test Logic II 2.10.4 Multibit Test Output Latch 2.10.5 Multibit Test Output Select 2.11.0 Write Multibit Test Register 3.0.0 Address Path 3.1.0 Address Input Buffers 3.1.1 Address Buffer I 3.1.2 Address Buffer II 3.1.3 Address Buffer III 3.1.4 Bank Address Buffer 3.2.0 Address Input Latch 3.3.0 Row Address Register I 3.4.0 Row Address Path 3.4.1 Row Address Register II 3.4.2 Address Bit [13] Gated Buffers 3.4.3 Block Decoder 3.4.4 Block/Row Select 3.4.5 X-Block Select 3.4.6 Row Predecoder 3.4.7 Row Factor Decoder 3.4.8 Row Factor Drivers 3.4.9 Master Row Decoder

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 9 3.4.10 Wordline Drivers 3.4.11 Sense/Precharge Select 3.4.12 Load Unlink Drivers 3.4.13 Load Unlink Driver (Edge) 3.4.14 Sense/Precharge Controls 3.4.15 Sense/Precharge Controls (Edge) 3.4.16 SP/SN~ Drivers 3.5.0 Column Address Register 3.5.1 Column Address [0] Register 3.5.2 Column Address [2:1] Register 3.5.3 Column Address [8:3] Register 3.5.4 Column Address [9] Register 3.5.5 Column Address [11] Register 3.5.6 Column Bank Address Register 3.5.7 Column Bank Address Decoder 3.5.8 Auto-Precharge Address Register 3.5.9 Address Latency Register I 3.5.10 Address Latency Register II A 3.5.11 Address Latency Register II B 3.6.0 Column Address Path 3.6.1 Column Address Latch 3.6.2 Sector Decoder 3.6.3 Sector Select 3.6.4 Column Predecoder 3.6.5 Column Factor Decoder 3.6.6 Column Decoder 3.7.0 Data Address Path 3.7.1 Read Data Address Register 3.7.2 Read Data Address Register Cell 3.7.3 Write Data Address Register I 3.7.4 Write Data Address Register II 3.7.5 Data Line Drive/Switch Enables

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 10 3.7.6 Data Line Drive Control I 3.7.7 Data Line Switch Control 3.7.8 Data Address [1,0] Predecoder 3.7.9 Data Address [13,11] Predecoder 3.7.10 X16 Switch Control Decoder 3.7.11 X16/X8 Switch Control Decoder 3.7.12 X16/X4 Switch Control Decoder 3.7.13 X8 Switch Control Decoder 3.7.14 X8/X4 Switch Control Decoder I 3.7.15 X8/X4 Switch Control Decoder II 3.7.16 X4 Switch Control Decoder 3.7.17 Data Line Drive Control II 3.8.0 Refresh Counter 3.8.1 Refresh Counter Cell 4.0.0 Control Clocks 4.1.0 Internal Clock / Power-Down System 4.1.1 Active {CK/CK~} Buffer 4.1.2 Standby {CK/CK~} Buffer 4.1.3 Clock Frequency Divider 4.1.4 Clock Gated Buffers 4.1.5 Internal Clock Generator I 4.1.6 Internal Clock Splitter 4.1.7 Internal Clock Generator II 4.1.8 {CKE} Input Buffer 4.1.9 CKE Pass Circuit 4.1.10 Power-Down / Self Refresh Controller 4.1.11 Power-Down Control Register 4.1.12 CKE Setup Timer 4.1.13 Sleep Signal Generator 4.1.14 DLL Status Monitor 4.1.15 Clock Frequency Divider

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 11 4.1.16 System Clock Input Control 4.1.17 Power-Down Mode Exit Control 4.1.18 Power-Down Mode Clocks 4.1.19 Clock Generator Options 4.2.0 Delay Locked Loop 4.2.1 DLL Control Signal Generation 4.2.2 DLL Enable Generator 4.2.3 DLL Reset Pulse Generator 4.2.4 DLL Clocks 4.2.5 DLL Clock Input Buffer 4.2.6 Internal DLL Clocks Generator 4.2.7 Clock Shape & Latch I 4.2.8 Clock Shape & Latch II 4.2.9 Phase Detector 4.2.10 Clock Jitter Filter 4.2.11 Up/Down Counter I 4.2.12 Up/Down Counter Cell 4.2.13 Up/Down Counter II 4.2.14 Start Up 4.2.15 Comparator I 4.2.16 Mode Select Decoder 4.2.17 Start Up Counter Control 4.2.18 Clock Stabilizer 4.2.19 Delay 4.2.20 Comparator II 4.2.21 Start-Up Circuit 4.2.22 Start-Up Circuit II 4.2.23 Jitter Filter Stop Generator 4.2.24 Adjustable Delay Lines Control 4.2.25 DLL Test Input Buffer 4.2.26 Counter Control 4.2.27 9-Bit Up/Down Counter

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 12 4.2.28 Fine Delay Adjust Decoders 4.2.29 Coarse Delay Adjust Decoders 4.2.30 Adjustable Delay Lines 4.2.31 Fine Delay 4.2.32 Fine Adjustable Delay Line 4.2.33 Coarse Delay 4.2.34 Counter Clock Generator 4.2.35 Feedback Delay Line 4.2.36 Clock Output Select 4.3.0 Command Controller 4.3.1 {RAS~} Input Buffer 4.3.2 {CAS~} Input Buffer 4.3.3 {WE~} Input Buffer 4.3.4 {CS~} Input Buffer 4.3.5 Command Decoder 4.3.6 Command Register 4.3.7 Test [45H] Command Decoder 4.3.8 Test [06H] Command Decoder 4.4.0 Row Activation/Refresh Controller 4.4.1 Device Initialization/Refresh Clocks 4.4.2 Bank Activation/Precharge Control 4.4.3 Single Bank Activate/Precharge 4.4.4 Single Bank Activate/Precharge Control 4.4.5 Write Recovery Delay Register 4.4.6 Auto-Precharge Pulse Generator 4.4.7 Programmable Delay Line 4.4.8 Bank Auto-Deactivation 4.4.9 Activate/Precharge Select 4.4.10 Bank Status Monitor 4.4.11 Row Activation Path 4.4.12 Sub-Bank Activation 4.4.13 Programmable Inverting Delay

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 13 4.4.14 X-Block Select Enable 4.4.15 Sense Amplifier Activation 4.4.16 Delay Line I 4.4.17 Delay Line II 4.4.18 Programmable Delay 4.4.19 Delay Control 4.4.20 Delay Line III 4.4.21 Unused Delay Line 4.4.22 Block Activation/Precharge Controls 4.4.23 Bitline Sense Delay Emulator 4.4.24 Rising Edge Delay 4.4.25 Delay Register 4.4.26 Programmable Delay Line 4.4.27 Programmable Capacitor I 4.4.28 Programmable Capacitor II 4.4.29 Refresh Disable Signal Generator 4.5.0 Read/Write Burst Controller 4.5.1 Read/Write Additive Latency 4.5.2 Additive Latency Clocks 4.5.3 R/W Command Additive Latency 4.5.4 Column Address Register Clocks 4.5.5 R/W Bank Select 4.5.6 Read/Write Clocks I 4.5.7 Write Latency Timer 4.5.8 Read/Write Active Detector 4.5.9 Write Latency Clocks 4.5.10 Write Latency Register 4.5.11 Write Burst Length Counter 4.5.12 Actual Write Start Detector I 4.5.13 Actual Write Start Detector II 4.5.14 CAC/Write Control I 4.5.15 CAC Control II

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 14 4.5.16 Local Data Line Drive Clock 4.5.17 Read/Write Clocks II 4.5.18 R/W Status Monitor I 4.5.19 R/W Column Access Enable 4.5.20 Column Address Transfer Clock 4.5.21 Column Access Enable Latch 4.5.22 R/W Status Monitor II 4.5.23 R/W Status Monitor III 4.5.24 Read Burst Trigger 4.5.25 DQ/DQS/DM Input Control 4.5.26 Input Buffer Enable 4.5.27 OCD Adjust/Write Latency 4.5.28 OCD Adjust Additive Latency 4.5.29 Auto-Precharge Feature Detector 4.5.30 Read/Write Test Clocks 4.6.0 Data Bus Sense and Drive Clocks 4.6.1 Sense and Drive Start Delay 4.6.2 Sense and Drive Enable 4.6.3 Sense and Drive Select 4.7.0 Data Path Clocks 4.7.1 Data Sense and Prefetch Emulator 4.7.2 Sense Start Delay Emulator 4.7.3 Sense Enable Emulator 4.7.4 Data Bus Sense Amplifier Emulator 4.7.5 Data Bus Write Driver Emulator 4.7.6 Data Prefetch Delay Emulator 4.7.7 Data Output Control Counters 4.7.8 Data Output Register Load Decoder 4.7.9 Data Output Register Flush Decoder 4.7.10 Double Data Rate Clocks 4.7.11 Read Latency Control 4.7.12 Latency Shift Register

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 15 4.7.13 Data Output Enable 4.7.14 Data Output Clocks 4.7.15 Data Strobe Input/Output 4.7.16 Output Strobe Generators 4.7.17 Output Strobe Generator 4.7.18 Data Strobe Output Buffers 4.7.19 Data Strobe Output Buffer 4.7.20 Data Strobe Output Driver 4.7.21 Pull-Up Strength Control 4.7.22 Pull-Down Strength Control 4.7.23 Data Strobes ODT 4.7.24 {DQS} On-Die Termination 4.7.25 Adjustable Termination Resistors 4.7.26 Resistor Value Control 4.7.27 Write Data Strobe Generator 4.7.28 Data Strobe Input Buffer 4.7.29 Write Data Strobe Driver 4.7.30 Data Strobe Input Control 4.7.31 Data Output Power-Down 4.7.32 Power-Down Delay 4.8.0 Write Data Mask Path 4.8.1 {LDM} Input Buffer 4.8.2 {UDM} Input Buffer 4.8.3 {LDM} Register 4.8.4 {UDM} Register 4.8.5 Write Data Mask Switch 4.8.6 Write Data Mask Drivers 4.8.7 Local Data Mask Select 4.8.8 {DM} On-Die Termination 4.8.9 Adjustable Termination Resistors 4.8.10 Resistor Value Control 4.9.0 On-Die Termination Control

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 16 4.9.1 {ODT} Input Buffer 4.9.2 ODT Register 5.0.0 Voltage Generators 5.1.0 Low Voltage Pump System 5.1.1 VBB Detector 5.1.2 Voltage Divider 5.1.3 Voltage Comparator I 5.1.4 Voltage Comparator II 5.1.5 VAUXL Detector 5.1.6 Voltage Divider 5.1.7 Voltage Comparator III 5.1.8 Voltage Divider 5.1.9 Voltage Comparator IV 5.1.10 Ring Oscillator 5.1.11 Low Voltage Clocks 5.1.12 Low Voltage Pump 5.1.13 VBB Pull-Up 5.1.14 VBB Test Clamp 5.1.15 VAUXL Test Clamp 5.1.16 Level Shifter 5.2.0 Sense Voltage Generators 5.2.1 Sense Voltage Generator 5.2.2 VSP Control Circuit 5.2.3 VSP Bank Generator Enable 5.3.0 VCP/VBLP Generator 5.3.1 VCP Generator I 5.3.2 VCP Generator II 5.3.3 VCP Signal Margin Voltage Generator 5.3.4 VCP Signal Margin Decoder 5.3.5 VBLP Generator 5.3.6 VBLP Signal Margin Voltage Generator

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 17 5.3.7 VBLP Signal Margin Decoder 5.3.8 VCP/VBLP Power Mode Control 5.3.9 Bias Voltage Generator 5.3.10 Bias Wake-Up Circuit 5.4.0 High Voltage Generators 5.4.1 High Voltage Generators (Bottom) 5.4.2 High Voltage Generators (Top) 5.4.3 High Voltage Pump System 5.4.4 High Voltage Pump 5.4.5 Charge Pump 5.4.6 Charge Pump Driver 5.4.7 Ring Oscillator 5.4.8 Ring Oscillator Control 5.4.9 VAUXH Level Detector 5.4.10 Hold Latch 5.4.11 VAUXH Pump Enable Latch 5.4.12 Voltage Comparator 5.4.13 VAUXH Start-Up Pull-Up 5.4.14 VPP Start-Up Pull-Up 5.4.15 Charge Pumps Control 5.4.16 VPP Level Detector 5.4.17 VPP Enable Latch 5.4.18 Voltage Comparator 5.4.19 Pulse Generator 5.4.20 Voltage Comparator 5.4.21 Voltage Divider 5.4.22 Unused VAUXH Detector 5.4.23 VPP Detector 5.5.0 DVCC Generator 5.6.0 Reference Voltage Generators 5.6.1 Bandgap Voltage Generator 5.6.2 Rest of Bandgap Voltage Generator

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 18 5.6.3 Primary Bias Voltage Generator 5.6.4 Programmable Voltage Divider 5.6.5 Bias Voltage Generator 5.6.6 Open Drain Operational Amplifier 5.6.7 Programmable Voltage Divider 5.6.8 Bias Generator 5.6.9 Variable Current Source 5.6.10 Variable Resistor 5.6.11 Load and Decoupling 5.6.12 Auxilliary Sense Voltage Generator 5.6.13 Self Refresh Bias Generator 5.7.0 Power-Up Circuitry 5.7.1 VCC Power-Up Detector 5.7.2 VREF1 Power-Up Detector 5.7.3 Power-Up Circuit 5.7.4 VCP and Low Voltages Test Circuit 5.7.5 Power-Up Sequencer 5.7.6 Redundancy Power-Up Circuitry 5.7.7 Redundancy Test Preset 5.7.8 Redundancy Power-Up MUX 5.7.9 Redundancy Power-Up Chain 6.0.0 Row Redundancy 6.1.0 Row Redundancy Fuse Programming 6.1.1 Row Redundancy Programming Cell 6.2.0 Row Address Match Detector 6.3.0 Redundant Master Row Drivers 6.4.0 Redundant Wordline Drivers 6.5.0 Normal Row Disable 7.0.0 Column Redundancy 7.1.0 Bitline Block Decoder

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 19 7.2.0 Column Redundancy Sector 7.2.1 Column Redundancy Fuse Programming 7.2.2 Column Address Match Detector 7.2.3 Redundant Column Driver 7.2.4 Normal Column Disable 8.0.0 Test/Calibration Modes 8.1.0 Test Address Buffer and Latches 8.1.1 Address Buffer 8.1.2 Test Address Latch 8.1.3 Test Address Latch 8.1.4 Test Address Latch 8.2.0 Test Mode Control 8.2.1 Input Address Buffers I 8.2.2 Input Address Register I 8.2.3 Test Address Predecoder I 8.2.4 Test Mode Registers I 8.2.5 Test Mode Register I-a 8.2.6 Test Mode Latch I-b 8.2.7 Test Mode Latch I-c 8.2.8 Test Mode Register I-d 8.2.9 Test Mode Register I-e 8.2.10 Input Address Buffers II 8.2.11 Input Address Register II 8.2.12 Test Address Predecoder II 8.2.13 Test Mode Registers II 8.2.14 Test Mode Register II-a 8.2.15 Tets Mode Register II-b 8.2.16 Test Mode Register II-c 8.2.17 Test Address Buffers III 8.2.18 Test Address Register III 8.2.19 Test Address Predecoder III

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 20 8.2.20 Test Mode Registers III 8.2.21 Test Mode Latch III-a 8.2.22 Test Mode Register III-b 8.2.23 Test Mode Register III-c 8.2.24 Test Mode Register III-d 8.2.25 Test Mode Entry 8.2.26 Test Mode Reset 8.3.0 Test Setting Registers 8.3.1 Test [2FH] Setting Register I 8.3.2 Test [40H] Setting Register I 8.3.3 Test [2FH] Setting Register III 8.3.4 Test [40H] Setting Register III 8.3.5 Test [30H] Setting Register 8.3.6 Test [8BH] Setting Register 8.3.7 Test [5FH] Setting Register 8.3.8 Test [5EH] Setting Register 8.3.9 Test [4BH] and [0CH] Setting Register 8.3.10 Test [6eh] Setting Register 8.3.11 Test [65h] Setting Register 8.3.12 Multibit Test Setting Registers 8.3.13 Test [31h] and [34h] Setting Register 8.3.14 Multibit Test Setting Register I 8.3.15 Multibit Setting Register II 8.3.16 Test Setting Register 8.3.17 Test [32H] Setting Register 8.3.18 Multibit Test Setting Register III 8.4.0 Test Mode Address Input 8.4.1 Test Mode Address Load Sequencer 8.4.2 Test Mode Address Register 8.4.3 Test Clock Buffer 8.5.0 Test Address Generator 8.5.1 Address Scrambler Logic

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 21 8.5.2 Scrambler Logic I 8.5.3 Scrambler Logic II 8.5.4 Scrambler Logic III 8.5.5 Scrambler Logic IV 8.5.6 Scrambler Logic V 8.5.7 Scrambler Logic VI 8.5.8 Address Negators 8.5.9 Register I 8.5.10 Register II 8.5.11 Register III 8.5.12 State Machine 8.5.13 Mode Register I 8.5.14 Mode Register II 8.5.15 Mode Selector Register 8.5.16 Hashing Signals Generator 8.5.17 Register Enable Generator 8.5.18 Test Address Registers 8.5.19 Scrambler First Stage 8.5.20 Scrambler & Register I 8.5.21 Scrambler & Register II 8.5.22 Output Register 8.6.0 Test Bank Address Generator 8.7.0 Multibit Test Pattern Generators 8.7.1 Multibit Control 8.7.2 Set Signal Generator 8.7.3 Delay Selector 8.7.4 Read Multibit Test Patern Generator 8.7.5 Write Multibit Test Patern Generator 8.8.0 OCD Impedance Controller 8.8.1 Self Refresh Test Output 8.8.2 Signature Control 8.8.3 Signature Circuit

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 22 8.8.4 OCD Program Decoder 8.8.5 OCD Control Logic 8.8.6 OCD Calibration Machine 8.8.7 OCD Clock Buffer 8.8.8 Data Line Signal Register 8.8.9 Calibration Step Pulse Generator 8.8.10 OCD Impedance Calibration Counter 8.8.11 Test Multiplexer 8.9.0 Programming Circuitry 8.9.1 Programming Circuitry I 8.9.2 Programming Circuitry II 8.9.3 Programming Circuitry III 8.9.4 Programming Cell I 8.9.5 Programming Circuitry IV 8.9.6 Programming Cell II 8.9.7 Programming Circuitry V 8.10.0 Memory Organization Options 8.11.0 Supply Test Output Switch I 8.12.0 Supply Test Output Switch II 9.0.0 Mode Registers 9.1.0 Mode Address Register 9.2.0 Mode Register Set 9.3.0 Basic Mode Register 9.4.0 Extended Mode Register I 9.5.0 Extended Mode Register II 9.6.0 Extended Mode Register III 9.7.0 Write Recovery Decoder 9.8.0 CAS Latency Decoders 9.9.0 OCD Adjust Mode Decoder 9.10.0 Additive Latency Decoder 9.11.0 ODT Resistance Value Decoder

Infineon HYB18T512160AF-3.7 DDR2 SDRAM Page 23 10.0.0 Self Refresh 10.1.0 Self Refresh Oscillator 10.1.1 Programmable Capacitor 10.2.0 Oscillator Frequency Divider 10.3.0 Self Refresh Timer 10.4.0 Self Refresh Pulse Generator A.1.0 Symbol Conventions - 1 A.1.1 Symbol Conventions - 2 A.1.2 Symbol Conventions - 3 A.2.0 Symbol Definitions - 1 A.2.1 Symbol Definitions - 2 A.2.2 Symbol Definitions - 3 A.2.3 Symbol Definitions - 4 A.3.0 Transistor Size Notation A.4.0 Capacitor Size Notation A.5.0 Resistor Size Notation

Infineon HYB18T512160AF-3.7 DDR2 SDRAM CAR Report Evaluation We value your business relationship at Chipworks. Your feedback is very important to help us better serve your future needs. Please take a few minutes to complete this evaluation to let us know if you were satisfied with this report. The information you provide will be used to strengthen our service quality program. Please rate Chipworks on this report at the following: On-Line Evaluation Form Or use the attached Report Evaluation Fax Back version on the next page. Rev. 1.0 - Feb. 6, 06 13:02 Y:\Reports_Public\Infineon\HYB18T512160AF-3.7\CAR-0602-205\CAR-report_evaluation.doc