ECE / COMP SCI 352 DIGITAL SYSTEMS FUNDAMENTALS Design Project 2 Spring 2003 Due: Beginning of class on Friday 5/02/2003 Projects 1 and 2 together will be the design of a simple digital stopwatch. In Project 1, you have designed five combinational circuits that are used for counting up (for stop-watch mode) and counting down (for timer mode) the digits of the watch. These circuits will be combined with storage elements and additional data and control logic in Project 2 to form the logic core of the stopwatch. The goals of this project are to: 1. Increase your familiarity with Mentor Graphics design and simulation tools, and familiarize you with CAFE (a logic simplification tool), 2. Improve your understanding of material covered in class, and Objective: This project is to be performed by teams of two students only (teams with more than two members are not allowed). Interactions between teams are to be limited to discussions of understanding of the specifications or to understanding of how to use the tools. All design and simulation work and files used are to be yours, not those of others, unless specified otherwise. I. Project Overview This semester, you will be designing and implementing the datapath and control logic for a digital stopwatch shown in Figure 1. The stopwatch is to have a five digit 7-segment LCD display and four buttons to control its operation. It can measure the elapsed time in seconds starting with 0:00:00 up to 9:59:59 (9 hours, 59 minutes and 59 seconds). It can also be set to a specified time and can count down to 0:00:00. Notice that there are labels for digits and buttons that we will be using for the references through out this description. The stopwatch has two modes, namely 1) stopwatch mode and 2) timer mode. In a stopwatch mode (a default mode), the stopwatch can be reset to 0:00:00 by pressing and releasing the RESET button. When you push START_STOP button once, it will count up and display the elapsed time in a resolution of seconds. Second push of START_STOP button will stop or pause the current clock (time count). The stopwatch counts up or pauses with each push of START_STOP button. When the mode button is pressed, the stopwatch will go to a timer mode where it counts the time in backward. In a timer mode, hour, high minute and low minute digit can be selected by pressing SET button repeatedly. The MODE_INC button will increase the selected field, which allows to be set to any desired time in a resolution of minutes. Count down starts with the push of START_STOP button. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 1
Similar to the stopwatch mode, count down can be paused or restarted with each push of START_STOP button. Table 1 describes functions of digits and push buttons. Figure 1. Stop-watch Display TABLE 1. Function(s) of digits and push buttons Name Function(s) Digits Push buttons H HM LM HS LS SET RESET MODE_INC START_STOP Hour digit Higher minute digit Lower minute digit Higher second digit Lower second digit In a timer mode, select a digit to set Reset all digits to 0, then go to stopwatch mode Switch between a stopwatch mode and timer mode Increase selected digit in a timer mode Start, stop, and resume counting The stopwatch will be designed using the hierarchical structure shown in Figure 2. The top level design will contain five logic blocks (modules) and some of theses blocks will consist of smaller sub-blocks. A brief description of each block is given below: STOPWATCH : Top level component of the stop watch PBI (Push Button Interface) : Synchronize push button signal with 10Hz clock. You will place three PBI modules for each of MODE_INC, Set, and START_STOP push buttons. CSL(Control State Logic) : Sequential State machine for control. COL(Control Output Logic) : Decodes CSL output to generate control signal for COUNT_BLK CLK_DIV(Clock divider) : Generates 1 second clock signal using 10Hz system clock. COUNT_BLK(Counter block) : 5 digit (H, HM, LM, HS, and LS) up/down counter * In this project, you will design two different COUNT_BLK modules MSCNT (Mode selectable up/down counter) : Up/Down Counter with mode select (Modulo 6 or Modulo 10) ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 2
MSINC (Mode selectable incrementer/decrementer) : In/decrement 4bit input by 1 with mode select (Modulo 6 or Modulo 10) Adder_4 : 4-bit full adder m6avg and m10avg (modulo 6 add value generator and modulo 10 add value generator) : Takes on a 4-bit BCD input and up_down signal, it generates a 4-bit offset value to be added the 4-bit BCD input. mux21_4 (4-bit 2-to-1 multiplexer): Select between a pair of 4-bit inputs using a control signal. Figure 2. Hierarchical structure of stop-watch design In project 1, you already designed following five modules: Adder_4, m10avg, m6avg, mux21_4 and MSINC. The additional modules will be completed in Project 2 using those five modules. II. Design and Project Report Guidelines You and your partner are to submit only one copy of joint project report for your group. Any project reports that do not conform following design and project report guidelines are subject to a penalty (point deduction). A late project submission carries a hefty 10% late penalty for each 24- hour period, up to 72-hours. For example, a project submitted between after lecture on Friday and same time on following Saturday will be deducted by 10 points. No project report will be accepted 72 hours after the due date. Here are some design and project report guidelines. Your are NOT to use a gated-clock design for this project. Wires must be drawn either horizontally or vertically. Never overlap symbols or gates; wires/buses should not cross symbols or gates. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 3
Always label symbols. You are to minimize the logic (gate count) whenever possible. Use the provided coversheet and your report must be in the EXACT same order as appears on the checklist. Your report must be page numbered. All schematics, symbols, trace windows, and list output files should be clearly labeled and scaled (zoomed in/out) to show all the contents. Your comments on test case should clearly demonstrate your understanding of each module s function and expected behavior. You are also required to indicate if the module is functioning properly or not. Hand-written page numbers, test cases, validations and comments are acceptable, but they should be readable. Fancy cover or binding are not required, but use a proper stable or clip to secure all pages. Finally, you are not to delete, modify or remove any of your files after the project has been submitted until you are instructed to do so. In a rare occasion, we may ask you to demonstrate your project to verify or to clarify your submitted work. III. Design of Modules 1. reg4 : 4-bit register with write enable The reg4 is a 4-bit register that stores the current value of one BCD digit. Input/output ports and functions are defined as follows: PORT NAME Function D(3:0) Input value which will be captured in 4 D FF s. If EN=1 (high), four D-FFs will capture the value on D(3:0) during IN EN the rising edge of CLK. If EN=0 (low), then 4 D FF s will not capture the value on D(3:0) and keep previous value on Q(3:0) CLK System clock RST When RST = 0, reset all D-FFs to 0 asynchronously. OUT Q(3:0) Outputs of four D-FFs. Figure 3. One bit slice of 4bit register with write enable A 1-bit register is comprised of a positive edge triggered D-FF and 1-bit 2-to-1 multiplexer to add a write enable control as shown in Figure 3. You are to use dff in gen_lib for D-FF and 2-to-1 ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 4
mux from gen_lib. Note that this flip-flop has active-low reset (CLR) and active-low set (PRE) input ports. When any of these signals are not used, you are to connect them to logic 1 (VCC in gen_lib). For the register implementation, you are to connect CLR to RST input (an active-low reset input) and PRE to VCC. Design a 1-bit register first, then design 4-bit register by making four copies of 1-bit register. Note that you are to use BUS, D(3:0) and Q(3:0) as input and output. Please refer to your Mentor Tutorial to review on how to use bus. Since this module is simple to design and test, you are to submit only your schematic for this module. However, you should verify that your register works correctly by writing your own force file and simulating with Quicksim. Generate the symbol once you have verify its correctness. The following is to be submitted in: The schematic from Design Architect 2. MSCNT : Mode Selectable Counter The module MSINC block, designed in Project 1, was a purely combinational circuit; it did not include any state or memory elements. To implement a counter, a 4-bit register (reg4) is to be added to MSINC to store the current state information. Since the RST of reg4 is active low signal, an inverter is required to implement the active-high reset (RST)of MSCNT. The up, dn and mod control input should connect directly to the same signals in the MSINC block. Also, co and bo output ports need to be connected to those from MSINC. Note that your MSINC block from Project 1 did not have use buses. First, regenerate the symbol of MSINC with buses p(3:0) and n(3:0). Then connect reg4 and other required logic to the regenerated MSINC symbol to implement MSCNT. The names for input/and output ports are given below. You have to use the same labels to make use of the provided force file. Input : CLK for clock signal, RST for reset, up and dn for up/down control Output: D(3:0) for current value of counter, co and bo for carry out and borrow out. For output of MSCNT, use a 4-bit BUS D(3:0) as output port instead of separate D3, D2, D1 and D0. The following diagram gives the basic idea for the design of this block. Figure 3. MSCNT block diagram ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 5
Use the provided force file MSCNT.force to test your module. Verify and show that your design works correctly with appropriate comments on your trace window printout. Non-annotated traces will be penalized. The followings are to be submitted in: The schematic from Design Architect The annotated test (trace window from Quicksim) of MSCNT.force Once you have verified your circuit with the force file, generate a symbol for this module and save it for later use. 3. COUNT_BLK : Counter Block Once you have the mode selectable up/down counter (MSCNT), you can build a 5-digit counter block. As shown in figure 1 and 2, five copies of MSCNT will be used as hour (H) digit, higher minute digit (HM), lower minute digit (LM), higher second digit (HS), and Lower second digit (LS). The port names and functions are described in following table. You have to use the same names to make use of force file we provide. Table 2. COUNT_BLK in/out port and function PORT NAME Function incsec When incsec is high, the current time value increase by 1 sec at rising edge of clock. decsec When decsec is high, the the current time value decrease by 1 sec at rising edge of clock. These two signal will be used while the stop watch is counting time, up or down. inch When inch is high, Hour digit increase by 1 at rising edge of clock. IN When inchm is high, Higher Minute digit increase by 1 at rising edge inchm of clock. inclm When inclm is high, Lower Minute digit increase by 1 at rising edge of clock. These three control signal will be used to preset the time for timer mode. CLK System clock that operates 10Hz RST Resets all digit to 0 when RST=0. H(3:0) Hour digit. HM(3:0) Higher minute digit. LM(3:0) Lower minute digit OUT HS(3:0) Higher second digit LS(3:0) Lower second digit all0 During timer mode, if the count down reach all 0, this signal goes high and indicate the controller to ring. This block is shown in Figure 4. MSCNT instances with shaded color should be set to modulo 6 counter. For this block, you have to figure out how to connect each block and what additional logic gates are necessary to implement the functions described in table 2. Designs with excessive number of gates will be penalized. Test your circuit using the provided force file COUNT_BLK. Verify that your circuit works correctly using Quicksim. Annotate your trace window to verify correct functionality. before you turn it in to facilitate easy grading. Non-annotated traces will be penalized. (One way of annotating could be to mark the actual input and output values for each ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 6
time interval on the trace. Also, you could put a tick under each correct output and a cross under each incorrect output.) The following should be turned in: The schematic from Design Architect The annotated test (trace window from Quicksim) of COUNT_BLK.force Figure 4. The design of COUNT_BLK Once you have verified your circuit with the force file, generate a symbol for this module and save it for later use. 4. CSL : Control State Logic The CSL is the state machine that controls the operation of the stop-watch. The state machine stores current state of stop-watch and depending on push button inputs and feedback signal from the counter block, CSL changes its current state. Port names and a brief description of each are given below in table 3. You have to use the same names to make use of the force file we provide. Table 3. CSL ports and functions PORT NAME Function all0 Input from COUNT_BLK, indicating the timer hits all 0. SET In timer mode, select a digit to set MD_INC Switch between stop-watch mode and timer mode. IN ST_SP Start, stop, or resume counting SET, MD_INC, ST_SP signals are from push button interface (PBI) of each push button. RST Resets state to stop-watch stop state. CLK 10Hz system Clock input CNT_en Count enable signal. When this signal is high, the clock divider block (CLK_DIV) will generate one second signal. OUT Ring The timer rings when this signal is high. S(2:0) Current state signal. These signals will be connected to control output logic (COL) to generate control signals to the counter block. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 7
The state transition diagram of this block is shown in the Figure 5. For simplicity, only the arrows resulting in state transitions are shown; when there is no arrow on the state diagram for an input condition, there is an implicit arrow that stays in the same state. Since there are eight states, three D-FFs are requires to build this Moore state machine. State assignment and state transition table is also provided below. State description Stop-watch stop state Figure 5. State transition diagram for CSL Table 3. CSL state assignment and transition table. Current State state assignment Input Next state Output ST_SP SW_count(1) - SW_stop 0(000b) MD_INC T_stop(2) - Stop-watch counting state SW_count 1(001b) ST_SP SW_stop(0) CNT_en ST_SP T_count(3) - Timer stop state T_stop 2(010b) SET H_set(5) - MD_INC SW_STOP(0) - Timer counting all0 Ring(4) CNT_en T_count 3(011b) state ST_SP T_stop(2) CNT_en Ringing state Ring 4(100b) - - Ring Hour setting state H_set 5(101b) SET HM_set(6) - Higher minute setting state HM_set 6(110b) SET LM_set(7) - Lower minute setting state LM_set 7(111b) SET T_stop(2) - Based on given state transition table and diagram you will need to complete the state table in order to generate a Café input file. The partially filled state table for this block is given below. Complete the state table below and be sure to consider all implicit arrows. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 8
Current state Input Next state Output S2 S1 S0 MD_INC ST_SP SET TimeOut NS2 NS1 NS0 Ring CNT_en SW_stop 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 1 X X 0 0 0 1 0 X X 0 0 0 1 1 X X 0 0 0 0 0 SW_count 0 0 1 X 0 X X 0 0 1 X 1 X X T_stop 0 1 0 0 0 0 X 0 1 0 0 0 1 X 0 1 0 0 1 0 X 0 1 0 0 1 1 X 0 1 0 0 0 0 1 0 1 0 0 X 0 1 0 1 0 1 X 0 1 0 0 0 0 1 0 1 1 0 X 0 1 0 0 0 0 1 0 1 1 1 X 0 1 0 0 0 T_count 0 1 1 X 0 X 0 0 1 1 0 1 0 1 1 X 0 X 1 0 1 1 X 1 X 0 0 1 1 X 1 X 1 0 1 1 0 1 Ring 1 0 0 X X X X 1 0 0 1 0 H_set 1 0 1 X X 0 X 1 0 1 X X 1 X HM_set 1 1 0 X X 0 X 1 1 0 X X 1 X LM_set 1 1 1 X X 0 X 1 1 1 X X 1 X A partially completed Café file (CSL.cafe) is also available. Complete CSL.cafe and generate the Café output file as you did in project 1. Implement CSL with the minimum number of gates. Designs with excessive number of gates will be penalized. Test your implementation using the provided force file CSL.force provided for this block. Comment and verify that your circuit works correctly on the trace window print out Nonannotated traces will be penalized. The following should be submitted: The completed café input file CSL.cafe The schematic from Design Architect The annotated trace windows from Quicksim of CSL.force ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 9
Once you have verified your circuit with the force file, generate a symbol for this module and save it for later use. 5. CLK_DIV : Clock Divider As described in overview section, we will assume that we will be using a 10Hz system clock. In order to count up or down every 1 second, you need to build clock divider which generates 1SEC signal once every second. This block can be built using the MSCNT block. If you set MSCNT as modulo-10 counter, the co signal of MSCNT will go high whenever it counts 10 system clocks. However, it would be very memory intensive and impractical to simulate thousands of seconds in Quicksim. Thus for a practical reason, we will simulate and test our circuit using the clock period of 10 nanosecond. In other words, for test and simulation, use the clock period of 10 ns and 1SEC signal is to be high for every 10 clock periods (100 ns). The required input and output signals for this block are shown below. Input : CLK : 10Hz system clock RST : Resets current counting to 0 state en : enable counting, if en=low, the MSCNT will hold current value. Output : 1SEC : 1 second signal. This signal will be connected to COL to generate in/decrease control for COUNT_BLK. To test this block, you have to provide your own force file. However, you have to verify following features. The clock divider can be reset by high RST signal. If en=1, the clock divider count up from current value and generates high 1SEC signal for one period of system clock cycle (rising edge to next rising edge). If en=0, the clock counter should not count system clock (hold current value). Figure 6. Example simulation for CLK_DIV An example simulation trace is given in Figure 6. Annotate and comment your tests before you turn it in. Non-annotated traces will be penalized. The following should be turned in: The schematic from Design Architect The trace window from Quicksim running your own force file ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 10
Once you have verified your design, generate a symbol for this module and save it for later use. 6. PBI: Push Button Interface. Although all the blocks you have built are synchronized with system clock, the push button input entered by the user is not synchronized with the system clock. Normally any push buttons requires a debounce circuitry requiring a carefully selected set of resistor and capacitor. Regardless of whether debounce circuitry is present or not, if the user holds a button more than 100 msec, it may be misinterpreted as two or more clicks of button. Hence, an interpreter circuit is required to interface between push buttons and rest of circuit, which will be called PBI. The PBI generates one clock period of logic 1 whenever a button is pressed no matter how long it is. The following wave form describes the function of the PBI block. Figure 7. Function of PBI Input/output port names and descriptions are as follows: Input RST : Reset PBI to its initial state. IN : Push button input CLK : 10Hz system clock input Output OUT : synchronized push button signal. Design your own state diagram and state transition table. There should be no more than 4 states to achieve this functionality and hence 2 flip-flops should be sufficient. Since there is only one input (except CLK and RST which will be directly connected to the flip-flops) and 2 flip-flops, you may not need to use Café to minimize the Boolean functions. To test this block, you have to provide your own force file. However, your simulation result should be similar to Figure7. Please annotate your trace window before you turn it in. You are to submit followings: A state transition diagram and table The schematic from Design Architect The annotated test (trace window from Quicksim of your own force file) Once you verified your circuit with the force file, generate a symbol for this module and save it for later use. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 11
7. COL: Control Output Generator. The COL is only pure combinational logic block in Project 2. This block will be placed between COUNT_BLK and CSL to generate appropriate control signals for COUNT_BLK together with synchronized button inputs, 1SEC signal and current state of state machine. In/output port names, functions and conditions are shown in table blow. PORT NAME Function S(2:0) Current state input from CSL IN MD_INC Synchronized (through PBI) push button signal of MD_INC button. 1SEC 1-Second signal from CLK_DIV block incsec Increase Second signal into COUNT_BLK decsec Decrease Second signal into COUNT_BLK OUT inch Increase Hour signal into COUNT_BLK inchm Increase Higher minute signal into COUNT_BLK inclm Increase Lower minute signal into COUNT_BLK rstall Reset COUNT_BLK to 0 The COL block can be viewed as specialized decoder with two different enable signal (MD_INC and 1SEC). This block will decode current state to generate control outputs for COUNT_BLK as follows. incsec : This signal goes high when CSL state is SW_count and 1SEC signal is high. decsec : This signal goes high when CSL state is T_count and 1SEC signal is high. inch : This signal goes high when CSL state is H_set and MD_INC signal is high. inchm : This signal goes high when CSL state is HM_set and MD_INC signal is high. inclm : This signal goes high when CSL state is LM_set and MD_INC signal is high. rstall : This signal goes high when CSL state is T_stop and MD_INC signal is high or when CSL state is SW_stop and MD_INC signal is high. Implement the COL module using a minimum logic. Designs with excessive number of gates will be penalized. No force file is provided for this module; you have to provide your own force file. One way to test this circuit is for all possible value of S(2:0), give a pulse of 1SEC signal and MD_INC signal. Any incomplete test or tests with insufficient comments will be penalized. The following should be turned in: The schematic from Design Architect The annotated test (trace window from Quicksim of your own force file) Once you verified your circuit with a force file, generate a symbol for this module and save it for later use. 8. STOP_WATCH: Top Design Module Now you will build the top module of project STOP_WATCH using symbols that you have generated. The function of STOP_WATCH is already described in the overview section. Refer to the project overview section for the functional description. If you have designed each module correctly and understood the functionalities of each module, the top level design will not be complex. However, thorough testing is important for the top module design to verify that the ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 12
modules are communicating with each other correctly. As specified in the overview section the stopwatch will have 4 push button input and 10Hz external clock signal as well as 5 BCD output for time information. The Input/output ports are described below. Figure 8. Design reference for STOP_WATCH Input Set_PB : SET push button input. MD_INC_PB : MD_INC push button input ST_SP_PB : START_STOP push button input These three push buttons will be synchronized by the PBI module RST : RESET push button input Note that RST do not have to be synchronized since the flip-flops we are using provide an asynchronous reset. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 13
CLK : 10Hz system clock input* Output H(3:0) : BCD output of hour Digit HM(3:0) : BCD output of higher minute digit LM(3:0) : BCD output of lower minute digit HS(3:0) : BCD output higher second digit LS(3:0) : BCD output lower second digit The STOP_WATCH module is built using following modules: PBI, CSL, CLK_DIV, COUNT_BLK, and COL. Use Figure 8 as reference. Test your top design with the provided force file STOP_WATCH.force. Be sure to use 3-bit bus for S(2:0) in your design or you may not be able to use provided force file. Carefully read comments in this force file and verify your circuit to see if it functions correctly. Once you have verified your trace, you need to submit five different portion of your annotated trace as follows. Schematic of your design. Print out of entire trace from 0ns to 1,200,000ns Print out of zoomed trace from 0ns to 2,000ns (should be annotated) Print out of zoomed trace from 477,000ns to 495,000ns (should be annotated) Print out of zoomed trace from 549,800ns to 551,500ns (should be annotated) Print out of zoomed trace from 1,094,000ns to ns 1,096,400ns (should be annotated) 9. COUNT_BLK2 : Sequential COUNT_BLK. In this section, you will design new COUNT_BLK which sequentially updates each digit. The COUNT_BLK you have designed in previous section used 5 instances of MSCNT. As you may notice, each MSCNT was fixed to be either modulo-6 or modulo-10 mode and one of m6avg or m10avg in MSINC instances will never be used for specific digit. Also, MSINC instances in MSCNT modules are doing similar job for each MSCNT instances. To reduce cost, it is possible to share only one MSINC to update each digit by adding an additional sequential controller. The diagram in Figure 9 illustrates how we can redesign COUNT_BLK. In the following sections, you will design the Sequential Update Logic (SUL) and a new counter block (COUNT_BLK2). ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 14
9.1 SUL: Sequential Update Control Logic. Figure 9. Redesigned COUNT_BLK The COUNT_BLK2 will use only one copy of MSINC to update all 5 digits in the counter block. In other words the MSINC should be shared in a sequential manner by control signals to update each digit. According to the control signals (inch, inchm, inclm, incsec and decsec) and the previous digit s co and bo, the SUL will change its state as well as generating up, dn and mod signal for shared MSINC block. The following table specifies input/output port names and their purposes. PORT NAME Function inch IN inchm inclm incsec decsec co bo CLK RST OUT updateh These five signals are output of COL block and invoke the state machine to update specific digit. Will be connected to co of MSCNT to indicate update of previous(lower) digit had carry out. Will be connected to bo of MSCNT to indicate update of previous(lower) digit had borrow out. System clock Resets state machine If this signal is high, the hour digit will be updated according to up/dn signal. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 15
If this signal is high, the higher minute digit will be updated according updatehm to up/dn signal. If this signal is high, the lower minute digit will be updated according updatelm to up/dn signal. If this signal is high, the higher second digit will be updated according updatehs to up/dn signal. If this signal is high, the lower second digit will be updated according updatels to up/dn signal. up Indicates whether the MSINC should count up. dn Indicates whether the MSINC should count down. mod Indicates the MSINC whether current digit is modulo-6 or modulo-10. The SUL will operate as specified in the Figure 10. There are six states. Figure 10.State transition diagram of SUL. To implement this state machine you will use One hot state encoding A.K.A one flip-flop per state design scheme to minimize complexity of combinational logic design. If you are not familiar with this design scheme you should review the textbook (Mano and Kime, page 406-410). The basic premise of the one flip-flop per state design method is that only a single state flip-flop will be high at any given time and the flip-flop with the 1 identifies the current state. So, the input logic for each state flip-flop simply reflects that there are only two conditions to place 1 in that flip-flop: 1. The flip-flop currently has a 1 and the conditions for moving to next state have not been met. 2. The previous state flip-flop has a 1, and the conditions for moving to the current state have been met. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 16
Since we have 6 different states, we will need 6 flip-flops to implement this state machine. Refer to following table for state assignment. State State flip-flops D5 D4 D3 D2 D1 D0 IDLE 0 0 0 0 0 1 UpdateLS 0 0 0 0 1 0 UpdateHS 0 0 0 1 0 0 UpdateLM 0 0 1 0 0 0 UpdateHM 0 1 0 0 0 0 UpdateH 1 0 0 0 0 0 Now you can develop the expressions for each state that correspond to the two conditions mentioned above by using the state transition diagram in Figure 11. The following table is provided to develop expressions for each state flip-flop. State IDLE (D0) Conditions required to remain the current state All control signals = 0 Conditions required to become current state UpdateLS (D1) None State = IDLE and State = UpdateH or all other state with co+bo = 0 either incsec or decsec is 1 UpdateHS (D2) None State = UpdateLS and either co or bo is 1 UpdateLM (D3) None 1. State = UpdateHS and either co or bo is 1 2. State = IDLE and inclm is 1 UpdateHM (D4) None 1. State = UpdateLM and either co or bo is 1 2. State = IDLE and inchm is 1 UpdateH (D5) None 1. State = UpdateHM and either co or bo is 1 2. State = IDLE and inch is 1 Input logic expression for each state flipflop D0= D1= D0*(incSec+decSEC) D2=D1*(co+bo) D3=D2*(co+bo) + D0*(incLM) D4= D3*(co+bo) + D0*(incHM) D5= D4*(co+bo) + D0*(incH) ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 17
Now you also have to define following expressions for outputs. updateh updatehm = D5 = D4 updatelm = D3 updatehs updatels = D2 = D1 mod = D2+D4 up = previous value of ( co + incsec + inch + inchm + inclm ) dn = previous value of ( bo + decsec ) Note that previous value can be obtained by delaying them for one clock cycle. In order to delay signals by one clock cycle, you may want to insert a DFF s between outputs (up, dn) and logics generating those outputs. Once you are done with your design, you have to test this block. Write your own force file and verify your state machine and output reflects given state transition diagram and your expression table. However, you don t have to submit your force file nor trace. Instead followings are to be submitted Completed the expressions for outputs Schematic sheet of your design 9.2 COUNT_BLK2 Now you have to combine SUL, MSINC, and reg4 to build up new COUNT_BLK. Use figure 9 as a reference to combine all modules. Each update signal from SUL will be connected to EN port of corresponding registers and also connected to tri-state buffers (buf.so3.n in gen_lib). Note that you have to specify the width of bus connected to each tristate buffer by changing N into 4 as in figure 12. This can be done by Shift-F7 as you do when changing the port names. N 4 Figure 12. Specifying width of buf.n.so3 The p(3:0) bus will be shared among 5 register s output. Since only one of update signal will be 1 at a given time, there will be no contention on p(3:0) bus. Also, n(3:0) will be captured on only one register which is currently enabled. The input/output ports are exactly the same as COUNT_BLK in section 2. Once you are done with the schematic, you can reuse COUNT_BLK.force to test this block since all the port names and function of COUNT_BLK2 are the same as COUNT_BLK. However, you will notice that each digit is updated sequentially (one at one clock cycle). Once you have verified the correct functionality of your new counter block, generate a symbol which has exactly the same shape as your COUNT_BLK. In the next section you will replace the COUNT_BLK symbol with COUNT_BLK2 symbol. The following should be turned in Completed schematic of COUNT_BLK2 Annotated trace of COUNT_BLK.force. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 18
10. STOP_WATCH2: Replacement of COUNT_BLK Now, you will replace the COUNT_BLK in your top level schematic with newly designed COUNT_BLK2. Note that at this point you have generated the symbol for COUNT_BLK2 in the same shape of COUNT_BLK. Make a copy of your top level design(stop_watch) that is named STOP_WATCH2 and then replace COUNT_BLK with COUNT_BLK2. Verify the ports are connected correctly. Again, to test your STOP_WATCH2, you can reuse STOP_WATCH.force to test your new top level design. Compare the simulation trace with your original simulation trace you obtained in Section 7. Once you have verified and compared your new trace, you need to submit the same five different portions of your annotated traces: Schematic of your design. Print out of entire trace from 0ns to 1200000ns Print out of zoomed trace from 0ns to 2000ns Print out of zoomed trace from 477000ns to 495000ns Print out of zoomed trace from 549800ns to 551500ns Print out of zoomed trace from 1094000ns to ns 1096400ns Each trace should contain meaningful annotation. Poor annotation will be penalized. 11. Extra credit options You can earn up to 30% additional points for your project by pursuing one of the following additional options. Make sure you have completed the required portion of the project before attempting any of these extra credit steps. You will not receive ANY extra credit if your base required design does not work correctly. You should not attempt more than one of the options below, as each requires significant time and effort. Additional points will be distributed relative to other groups that attempt the same extra credit choice. Here is a brief description of each option. We are also willing to entertain other extra credit options; however, you *must* discuss your idea with an instructor before attempting it. No extra credit will be granted for additional work that was not discussed with an instructor ahead of time. 1) (up to 15 points) Add a lap timer function to the stopwatch by using the SET input button as the lap timer button. Pressing the lap timer button holds the current stopwatch time on the display, while the stopwatch itself keeps running. Pressing the lap timer button again will revert the display to the current time. Also, if the user presses STOP while in the lap timer display mode, the stopwatch should stop, but continue to display the lap time until the user presses the lap timer button. You must modify the control logic state diagram appropriately, add additional flip-flops to store the frozen lap time, and modify the output function for the display. This option will be worth at most 15 points. 2) (up to 30 points) Design a code converter block that converts the BCD digits supplied by the stop watch to a Roman numeral number display. The digits must be displayed as specified in the following table. Since Roman numerals require a variable number of characters, assume that the maximum number deeded for each position is available on a display device. Hence, the display device will have the ability to display a total of ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 19
fourteen characters: HHHH:MMMMMMM:SSSSSSS. The display device will display one of five characters at each character according to the following 3-bit encoding: a blank space is represented with 000, I is represented with 001, V is represented with 010, X is represented with 011, and L is represented with 100. Hence, the display device has 18x3 = 54 bits controlling it, so your output function will have to generate these 54 bits as a function of the current BCD digits. All numbers should be aligned to the rightmost position (blanks, if any, should be on the left). Your code converter can be a purely combinational output function that uses the BCD digit values as inputs, or you can build it as a sequential state machine, similar in spirit to the sequential COUNT_BLK2. However, any sequential design must have few enough states that it can keep up with digit updates occurring once per second as a result of the timer or stop watch running or the user changing digits in timer mode. Digit Max letters Representation Hours 4 I, II, III, IV, V, VI, VII, VIII, IX Minutes 7 I-X,XI-XX,XXI-XXX,XXXI-XL,XLI-L,LI-LIX Seconds 7 I-X,XI-XX,XXI-XXX,XXXI-XL,XLI-L,LI-LIX 3) (up to 30 points) Redesign COUNT_BLK to minimize the number of gates by using dedicated next state and output functions instead of the existing functional blocks (adder, m6avg, etc.). The cost of your implementation (gate count) will be compared against all other such designs submitted by other groups, and the extra credit points you earn will be proportional to your cost relative to the other groups. 4) (up to 30 points) Build your design by purchasing discrete parts, assembling them on a proto board, and demonstrating your board to the instructors. If you choose this option, you are on your own, and the instructors will not be able to support or assist your efforts. Extra credit points will be distributed on a competitive basis, and will not exceed 30 points. All extra credit work must be documented in your report with a schematic, a textual description, state diagram (if relevant), a commented force file, and an annotated trace for each new or modified module. Also, if you pursue option (4) you must schedule a time with an instructor or TA to demo your implementation. Make sure you have completed the required portions of the project before attempting any extra credit work. The instructors will provide minimal, if any, support for extra credit work. ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 20
Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/Comp Sci 352 Digital System Fundamentals Spring 2003 DESIGN PROJECT 2: Timer/Counter Team Member Names: Student ID Numbers: Sections: Hours by each member: Percent of effort: Signatures: MODULES ITEM POINTS YOUR POINTS Reg4 Schematic 2 MSCNT Schematic 3 Trace (MSCNT.force) 3 COUNT_BLK Schematic 4 Trace 4 (COUNT_BLK.force) CSL Café file (CSL.cafe) 4 Schematic 4 Trace (CSL.force) 4 CLK_DIV Schematic 2 Test (your own) 4 PBI State diagram 3 Schematic 3 Test (your own) 3 COL Schematic 2 Test (your own) 4 STOP_WATCH Schematic 3 Multiple traces 12 (STOP_WATCH.force) SUL Expressions for outputs 3 Schematic 5 COUNT_BLK2 Schematic 4 Trace 4 (COUNT_BLK.force) STOP_WATCH2 Schematic 3 Multiple traces 12 (STOP_WATCH.force) Report quality 5 TOTAL 100 Extra Credits Total Extra Credits 30 ECE/CS 352 Spring 2003 Project 2 Document Version 1.1 21