The Case of the Closing Eyes: Is PAM the Answer? Is NRZ dead?

Similar documents
DataCom: Practical PAM4 Test Methods for Electrical CDAUI8/VSR-PAM4, Optical 400G-BASE LR8/FR8/DR4

Summary of NRZ CDAUI proposals

On Figure of Merit in PAM4 Optical Transmitter Evaluation, Particularly TDECQ

System Evolution with 100G Serial IO

100Gb/s Single-lane SERDES Discussion. Phil Sun, Credo Semiconductor IEEE New Ethernet Applications Ad Hoc May 24, 2017

CDAUI-8 Chip-to-Module (C2M) System Analysis #3. Ben Smith and Stephane Dallaire, Inphi Corporation IEEE 802.3bs, Bonita Springs, September 2015

The Challenges of Measuring PAM4 Signals

PAM4 signals for 400 Gbps: acquisition for measurement and signal processing

64G Fibre Channel strawman update. 6 th Dec 2016, rv1 Jonathan King, Finisar

100G EDR and QSFP+ Cable Test Solutions

100G and 400G Datacom Transmitter Measurements

Draft Baseline Proposal for CDAUI-8 Chipto-Module (C2M) Electrical Interface (NRZ)

Next Generation Ultra-High speed standards measurements of Optical and Electrical signals

32 G/64 Gbaud Multi Channel PAM4 BERT

Development of an oscilloscope based TDP metric

Combating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels

Combating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels

CDAUI-8 Chip-to-Module (C2M) System Analysis. Stephane Dallaire and Ben Smith, September 2, 2015

Ali Ghiasi. Nov 8, 2011 IEEE GNGOPTX Study Group Atlanta

Further Investigation of Bit Multiplexing in 400GbE PMA

A Way to Evaluate post-fec BER based on IBIS-AMI Model

CAUI-4 Chip to Chip and Chip to Module Applications

M809256PA OIF-CEI CEI-56G Pre-Compliance Receiver Test Application

Comparison of NRZ, PR-2, and PR-4 signaling. Qasim Chaudry Adam Healey Greg Sheets

40G SWDM4 MSA Technical Specifications Optical Specifications

Development of an oscilloscope based TDP metric

Component BW requirement of 56Gbaud Modulations for 400GbE 2 & 10km PMD

MR Interface Analysis including Chord Signaling Options

Practical Receiver Equalization Tradeoffs Applicable to Next- Generation 28 Gb/s Links with db Loss Channels

PAM8 Baseline Proposal

Analyzing GBaud PAM4 Optical and Electrical Signals APPLICATION NOTE

CAUI-4 Chip to Chip Simulations

SECQ Test Method and Calibration Improvements

40G SWDM4 MSA Technical Specifications Optical Specifications

50 Gb/s per lane MMF baseline proposals. P802.3cd, Whistler, BC 21 st May 2016 Jonathan King, Finisar Jonathan Ingham, FIT

Proposed reference equalizer change in Clause 124 (TDECQ/SECQ. methodologies).

100G PSM4 & RS(528, 514, 7, 10) FEC. John Petrilla: Avago Technologies September 2012

100G-FR and 100G-LR Technical Specifications

Measurements and Simulation Results in Support of IEEE 802.3bj Objective

Presentation to IEEE P802.3ap Backplane Ethernet Task Force July 2004 Working Session

LOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES. Masum Hossain University of Alberta

100G SR4 Link Model Update & TDP. John Petrilla: Avago Technologies January 2013

Architectural Consideration for 100 Gb/s/lane Systems

Brian Holden Kandou Bus, S.A. IEEE GE Study Group September 2, 2013 York, United Kingdom

Clause 74 FEC and MLD Interactions. Magesh Valliappan Broadcom Mark Gustlin - Cisco

Application Space of CAUI-4/ OIF-VSR and cppi-4

Technical Feasibility of Single Wavelength 400GbE 2km &10km application

Need for FEC-protected chip-to-module CAUI-4 specification. Piers Dawe Mellanox Technologies

100GBASE-DR2: A Baseline Proposal for the 100G 500m Two Lane Objective. Brian Welch (Luxtera)

Open electrical issues. Piers Dawe Mellanox

Approach For Supporting Legacy Channels Per IEEE 802.3bj Objective

COM Study for db Channels of CAUI-4 Chip-to-Chip Link

100 Gb/s per Lane for Electrical Interfaces and PHYs CFI Consensus Building. CFI Target: IEEE November 2017 Plenary

PAM8 Gearbox issues Andre Szczepanek. PAM8 gearbox issues 1

BRR Tektronix BroadR-Reach Compliance Solution for Automotive Ethernet. Anshuman Bhat Product Manager

Performance comparison study for Rx vs Tx based equalization for C2M links

Exceeding the Limits of Binary Data Transmission on Printed Circuit Boards by Multilevel Signaling

Measurements Results of GBd VCSEL Over OM3 with and without Equalization

Thoughts on 25G cable/host configurations. Mike Dudek QLogic. 11/18/14 Presented to 25GE architecture ad hoc 11/19/14.

400G-FR4 Technical Specification

CAUI-4 Application Requirements

N4917BACA Optical Receiver Stress Test Solution 100 Gb/s Ethernet

Ali Ghiasi. Jan 23, 2011 IEEE GNGOPTX Study Group Newport Beach

100GBASE-SR4 Extinction Ratio Requirement. John Petrilla: Avago Technologies September 2013

Product Specification 100m Multirate Parallel MMF 100/128G QSFP28 Optical Transceiver FTLC9551SEPM

Further Clarification of FEC Performance over PAM4 links with Bit-multiplexing

SMF Ad Hoc report. Pete Anslow, Ciena, SMF Ad Hoc Chair. IEEE P802.3bm, Geneva, September 2012

Systematic Tx Eye Mask Definition. John Petrilla, Avago Technologies March 2009

50 Gb/s per lane MMF objectives. IEEE 50G & NGOATH Study Group January 2016, Atlanta, GA Jonathan King, Finisar

40GBd QSFP+ SR4 Transceiver

PAM-2 on a 1 Meter Backplane Channel

100GBASE-FR2, -LR2 Baseline Proposal

100G CWDM Link Model for DM DFB Lasers. John Petrilla: Avago Technologies May 2013

802.3bj FEC Overview and Status IEEE P802.3bm

Receiver Testing to Third Generation Standards. Jim Dunford, October 2011

TDECQ update noise treatment and equalizer optimization (revision of king_3bs_01_0117) 14th February 2017 P802.3bs SMF ad hoc Jonathan King, Finisar

Baseline Proposal for 200 Gb/s Ethernet 40 km SMF 200GBASE-ER4 in 802.3cn

More Insights of IEEE 802.3ck Baseline Reference Receivers

Refining TDECQ. Piers Dawe Mellanox

Optical transmission feasibility for 400GbE extended reach PMD. Yoshiaki Sone NTT IEEE802.3 Industry Connections NG-ECDC Ad hoc, Whistler, May 2016

40GBASE-ER4 optical budget

Comment #147, #169: Problems of high DFE coefficients

Investigation of PAM-4/6/8 Signaling and FEC for 100 Gb/s Serial Transmission

100G MMF 20m & 100m Link Model Comparison. John Petrilla: Avago Technologies March 2013

802.3cd (comments #i-79-81).

500 m SMF Objective Baseline Proposal

Investigation of PAM-4/6/8 Signaling and FEC for 100 Gb/s Serial Transmission

Techniques for Extending Real-Time Oscilloscope Bandwidth

DesignCon Pavel Zivny, Tektronix, Inc. (503)

Baseline proposal update

DSA8300 Datasheet Digital Serial Analyzer Sampling Oscilloscope

Further information on PAM4 error performance and power budget considerations

DSA8300 Datasheet Digital Serial Analyzer Sampling Oscilloscope

Duobinary Transmission over ATCA Backplanes

Proposal for 400GE Optical PMD for 2km SMF Objective based on 4 x 100G PAM4

The EMC, Signal And Power Integrity Institute Presents

100G QSFP28 SR4 Transceiver

Features: Compliance: Applications: Warranty: 49Y7928-GT QSFP+ 40G BASE-SR Transceiver IBM Compatible

QSFP+ 40GBASE-LR4 Fiber Transceiver

AMI Simulation with Error Correction to Enhance BER

Transcription:

The Case of the Closing Eyes: Is PAM the Answer? Is NRZ dead?

Agenda Introductions Overview Design Engineering Perspective Test & Measurement Perspective Summary Audience Discussion

Panelists Cathy Liu Director, Broadcom Ltd Ransom Stephens, PhD Principal, Ransom s Notes Pavel Zivny Domain Expert, Tektronix, Inc. Mike Li, PhD Fellow, Intel Corporation Greg LeCheminant Sr. Applications Engineer, Keysight Technolo Mark Marlett Principal Engineer, Inphi Corporation Marty Miller Chief Scientist, Teledyne-LeCroy Corporati 3

PAM4 Impact on Communications Network Ethernet Central Office CFP8 CDAUI-8, CDAUI-16 CEI-56G-VSR-PAM4 400GBASE-SR16 400GBASE-FR8 400GBASE-CLR8 400GBASE-DR4 Blade Servers Flex Ethernet, 400GBASE-LR8 To 40km 400GBASE-DR4 400GBASE-FR8 Router Backplane, chip to module City OIF/ITU Long Haul Coherent 400G-PM-QPSK CDAUI-8 400GBASE-KR8 CEI-56G-VSR-PAM4 CEI-56G-LR-PAM4 2017/05 V 1.3 cjl, prz Optical test: mask, hit ratio, TDEC, TDECQ

400G 100G

Distance Standard Modulation/signaling e.g. X,000 km OIF, OTN, ITU Complex optical DP-QPSK 100M (MMF) Ethernet PAM2 at 25 GBd 400GBASE-SR16 10 km Ethernet PAM4 at 25 GBd 400GBASE-LR8 2 km Ethernet PAM4 at 25 GBd 400GBASE-FR8 500 m Ethernet PAM4 at 56 GBd 400GBASE-DR4 Backplane < 1m OIF CEI PAM4 at 25 GBd CEI LR Interconnect module to chip, chip to chip Ethernet OIF CEI NRZ PAM4 CDAUI-16, CDAUI-8 CAUI-4 CEI VSR

Is NRZ Dead? Ransom Stephens, PhD, Ransom s Notes

The problem Frequency dependent loss ISI (inter-symbol interference) Equalization is not enough Closed eyes IL( f ) = S dd21 (f) (db) NRZ: 14 GHz 28 Gb/s f (GHz) 28 GHz 56 Gb/s

The problem Frequency dependent loss ISI (inter-symbol interference) Equalization is not enough Closed eyes IL( f ) = S dd21 (f) (db) Need PAM4 f (GHz) PAM4: 14 GHz 56 Gb/s

PAM4 vs NRZ bits, symbols, baud NRZ bits are really PAM2 symbols T NRZ 0 1 V 1 V 0 2 symbols T PAM4 0 0 0 1 1 1 1 0 V 3 V 2 V 1 V 0 4 symbols NRZ bit rate = symbol rate (Gb/s = Gbaud) PAM4 bit rate = 2 symbol rate (Gb/s = 2 Gbaud) PAM4 28 Gbaud = 56 Gb/s

NRZ is dead PAM4 development 3 slicers, 4-level DFE, mushy clock recovery Disruptive Receiver Improvements DSP-based Receivers PAM8, PAM16,, PAMn RIP NRZ

But PAM4 makes everything gets harder Every signal degradation has greater impact on PAM4 than it had on NRZ SNR at least 9.5 db worse 16 symbol transitions 6 different rise and fall times, t rise & t fall 75% transition density Crosstalk, reflections cause more trouble AND Forward error correction, FEC BER < 10-5 costs power, latency, space 10 10 10 11 10 01 10 00 11 10 11 11 11 01 11 00 01 10 01 11 01 01 01 00 00 10 00 11 00 01 00 00

Long live NRZ! I m not dead yet!

Long live NRZ! I m not dead yet! Yes you are.

Path from 56G to 112G Mike Peng Li, Intel

NRZ vs PAM4 vs Reach at 56G Is NRZ dead? No!! 16

FPGA 58 Gbps PAM4/30 Gbps NRZ Transceiver Measurements PAM4: BER of <1e-9 observed at 58 Gbps with channel insertion loss (BGA-to-BGA) < -30dB NRZ: Error free at 30 Gbps with channel insertion loss (BGA-to-BGA) < -40dB TX and RX exceed the Ethernet and CEI 28G NRZ and 56G PAM4 spec 17

112G Feasibility PAM4: Feasible for 30 db (at Nyquist) channel, backward compatibility insured, great value proposition PAM4 and PAM8 comparison analysis has been done for BP/LR channels, and PAM4 out-performs PAM8 in general Advanced medium (e.g., better PCB materials, cable backplane) needed to be considered to achieve practical reach objectives for BP and DAC Constraints are in how much power the system can afford, which affects the SERDES implementation choices CEI-112G-VSR 14dB BGA-to-BGA IL (db) ILD (db) RL (db) ICR (db) ICN* (mv-rms) 31-2/2-7 10 0.91 CEI-112G-LR 30dB BGA-to-BGA 18

RX Architecture vs RS(544, 514) (i.e., KP FEC) vs Performance If the RX does not have DFE, then the main burst error source is eliminated. A RX dominated with FFE can compensate reflections without introducing burst errors Post FEC BER < 1e-25 achieved with FFE dominate RX, exceeding all system requirements.

FEC and 112G Outlook Cathy Liu, Broadcom Limited

Landscape of FEC Technology 21

Post-FEC Measurements Error free over 68hr Max. symbol in error = 4 22

56G PAM4 KP4 FEC Test Results Error statistic (10 hr) Channel loss and crosstalk tolerance improvement (post-fec BER < 1e-15) 23

112G Outlook 24

112G Design Challenges OIF CEI 112G projects are already underway PAM4 is likely signaling format for VSR application o NRZ is out o Industry has digested PAM4 and FEC challenges through 56G design and production o So the biggest challenge of 112G PAM4 design is the doubling bandwidth (component, package, device, T&M ) What if PAM4 is not good enough for long reach application? o PAM8, PAM16, or QAM? (d) 16QAM 25

Optics & PAM4 Mark Marlett, Inphi

DSP enables PAM4 optical channels Multi-tap TAP FFE + adaptation of many timing and voltage parameters Optical Sensitivity Limit Histogram Optical mid power Histogram

Optical Communications future Higher Data rate (400G+) Modules More DSP New FEC Higher baud rates (56Gbaud) More wavelengths on the same fiber Fitting more data in these bandwidth limited channels So where does NRZ (PAM2) fit in? NRZ is in legacy (<28 Gb/sec) What is the future of Modulation? PAM4 -> PAM? ->?? PAM4+ -> DSP

Receiver test has some big challenges beyond just the PAM4 issues! Greg LeCheminant, Keysight

Use of FEC allows for a much higher SER for the hardware. (Shouldn t SER/receiver testing be a lot easier now?) High coding gain FEC means that a simple SER analysis does not exactly predict the overall link integrity Pre-FEC SER could be within the required limit, but if there is a long burst of errors, frames can be lost We (T&M) need to do a better job of showing the signature of errors, whether they are random or bursty

Frame loss analysis (counting errors within the FEC frame block) would be helpful If the data is striped across multiple lanes, all lanes need to be monitored simultaneously. Is it practical? Standards/T&M challenge: Consider new ways to account for long bursts of errors other than frame loss ratio when there are many parallel lanes

Acquisition for PAM4 transmitter characterizaton Pavel Zivny, Tektronix

Acquisition for PAM4 transmitter characterizaton Pavel Zivny, Tektronix

Traditional link design. The receiver rule: more BW is better (keeps the eye more open) + Pre-Emphasis + - - + - Equalizer The links as we know them from lower loss systems. Equalization was low key or (optical systems) none 34

What s the DUT doing: the Receiver for PAM4 at 53 GBd (aka 100 Gb/s) does sample at Nyquist. The extra bandwidth beyond that is not that useful* as it s past Nyquist. D/A or analog TX + - + - + + + - - - - - - + + CR Nyquist Low Pass A/D FFE 1-T Today the receivers for 53+ GBd are an A/D that samples at the symbol rate (53 GS/s for a 53 GBd signal) and the Nyquist is then 26 GHz energy beyond 26 GHz is aliased* and thus not fully in control of the DSP For this and other reasons, the receiver is rolled of just past Nyquist. Thus the measurement system should not measure past what the receivers will be able to see. i.e. the measurement bandwidth ought to be similar to what the Rx does. *Since we sample in-phase the alias is not as bad as in asynchronous systems. And: there s (typically) is an analog boost (CTLE) before sampling not aliased. 35

Ethernet changed the measurement bandwidth significantly to match what the RX sees: to measure a 26 GBd signal, use 13 GHz scope BW 4 th order Bessel-Thomson filter, with controlled roll-off) And you have to get the bandwidth right! Since: - Higher bandwith will improve the eye opening. You might get false good on bad DUT. - Lower bandwidth than the required ½ of the symbol-rate-frequency is (i.e. 13 GHz for 26 GBd of the 50 Gb/s link) will worsen the TDECQ, and increase the number of false fail DUTs. - Opposite will happen for the RX test (where the oscilloscope measures up the stressors) 36

Conclusion - The measurement bandwidth is critical for correct TDECQ measurement. - Unlike in NRZ, where the measuring device (oscilloscope) doesn t close the eye*, the bandwidth of the oscilloscope limits the - This is true for the measurent of the TX, and - the measurement of the RX, since the stressed eye source is measured with the same (oscilloscope) measurement bandwidth *about 1% closure is due to the B-T in NRZ (0.75x filter) 37

SNDR as a good SI Indicator? Marty Miller, Teledyne-LeCroy

Signal to Noise and Distortion Calculated from a QPRBS13 linear fit -> Pulse Errors across whole UI RMS noise 4 settled levels

Why not a SNDR (mid) using error at center? Jitter affects RMS fit error at 0 & 1UI (500fs and 50fs Rj)

Panel Discussion