utophasers and frame synchronizers GEP00 - HEP00 3Gb/s, HD, SD embedded domain Dolby E systems to PCM Video timing in SDI decoder with audio shuffler product application note Quad speed Upgradable to 3Gb/s Embedded Metadata S00 COPYRIGHT 0 XON DIGITL DESIGN B.V. COPYRIGHT 0 LL RIGHTS RESERVED NO PRT OF THIS DOCUMENT MY BE REPRODUCED IN NY FORM WITHOUT THE PERMISSION OF XON DIGITL DESIGN B.V.
Introduction It is a common misconception that because broadcast systems use the serial digital interface (SDI) to transport video from one device to another it is no longer necessary to consider timing in the design of a system. Many devices in the production and transmission process, especially those with advanced video processing (vision mixers and Master Control switchers), can successfully handle limited discontinuities in their input signals with little or no noticeable effect on the output. With the simplification of the transmission process many systems do not use these types of devices and switch directly between sources simply by making different routes in a central router. Even if the two video sources are suitably time-aligned this will present a non-coherent SDI to down-stream devices. Large timing errors between sources can produce very badly formatted SDI streams with too many (or too few lines) in the frame in which the switch took place, this often results in picture and/or sound disturbances. Even minor timing differences between two sources, as small as a few samples, may be sufficient to trigger these disturbances. Within the Synapse range of modular interfacing products there is an array of modules which provide the functionality to retime video signals or to normalize transitions. This pplication Note sets out to high-light some of the issues relating to timing in SDI systems and to show how Frame Synchronizers and utophasers can provide assistance in solving some of these issues. Digital video system - nalog timing reference Bi-level and Tri-level syncs Many SD and HD digital broadcast systems continue to use a bi-level, analogue signal, such as Black and Burst, as the source of the timing reference to lock internal clocks within the various origination and processing equipment used in a broadcast center. In a 5-frame per second environment Black and Burst provides a timing event (sync pulse) every 64µS this has a timing accuracy of ±40nS; this equates to a possible variation in the timing reference of approximately ±3 HD video samples. 65 line 50Hz systems have a line frequency of 5,65Hz, and therefore 5,65 sync pulses will be generated every second, however 080i50 produces 8,5 lines per second, this means that only every 5th SD sync pulse will coincide with the start of an HD line. 9 HD lines (35.55µS) = 30µS 5 SD line (64µS) = 30µS This accuracy can be greatly improved by the use of Tri-Level Syncs for HD systems; these have a direct : relationship to the line frequency of the video signal. Video router references Video routers use a reference signal to determine the point in time when cross-point switches are made. This an area where considerable errors can occur, SD signals should switch at the mid-point of the active section of line 6 and HD switch at the mid-point of the active section of line 7. The table below shows where a SD or HD would switch if the router was being fed with a reference from the other standard (this information relates to 50Hz environments). Whilst it is unusual for a SD router to use a HD reference it is common for a HD or mixed standard router to use only SD Black and Burst as the reference source for both HD and SD signal switching. Therefore the HD signals will not be switched on the correct line, instead they will switch very near to the start of Line, an area which could be carrying ncillary data. Video standard of signal to be switched Target switching point Time from start to Equivalent point in a signal frame of the other video standard SD (65-50) Line 6 358µS Start of HD line HD (080i50) Line 7 36µS Mid-point of SD line 4 Timing of video sources to the router input Because a router s cross-point switch timing is determined by the external reference signal it is critical that the source of the video feeding the router is correctly timed in order that switching between sources occurs at the correct position in both of the signals. Failure to align the source video with the external reference may result in switches taking place within the active picture area. Example, below, shows how mis-timing of router sources compared to the switching reference can introduce large errors into the output picture. page
Example : Switching of co-timed video sources not timed to router reference End of Frame / Start of Frame Router Reference Signal Start of Frame Router Switching Point End of Frame Current Video Source Start of Frame End of Frame New Video Source Current video source Router switching point Example. Switching of co-timed video sources not timed to router reference Corruption on the line following switch New video source This example shows that although the two video sources are correctly timed in relation to each other because they are timed considerably later than the router s reference switch is visible. End of Frame the / Start of Frame Note: only one field is shown. Router Reference Signal Router Switching Corruption of video data following a switch unable to descramble and decode the video until Point Start of Frame End of Frame the next video line starts. If the switch has taken Before transmitting the video data along a video Video Source cable an SDI device mustcurrent encode the video data place within the active picture area this failure to according to the appropriate standard. This successfully decode the SDI stream is seen as a Start of Frame Endline of Frame corruption for the remainder of the following encoding process ensures that the serial bitstream the switch. Newthe Video receiving Source has sufficient transitions for device to recover the data and clock from the bitstream. Monitoring of switch line and position The receiving device must reverse the encoding Several of the advanced frame synchronizers in process to produce the original video data. the Synapse range have the facility to detect and SDI encoding is a two stage process; each stage measure the position in a video frame where a uses a generator polynomial to convert the signal. switch occurs. If the switch occurs on a blanked In stage the video is scrambled its output is line system can the exact pixel in which Example. andswitching of co-timed videothe sources not timed to detect router reference referred to as Scrambled non-return-to-zero (NRZ), the switch occurred. However if the switch takes the second stage converts the NRZ to polarity- place during active picture, or during a line carrying free Scrambled NRZ-inverted (NRZI). NRZI is DC data, the system is unable to determine when the balanced, if the bitstream is inverted between scrambled video changes and therefore can only transmitter and received the polarity free nature indicate the line in which the switch occurred. of the signal allows the decoder to successfully The example below shows the information from a recover the original data. HFS00 module indicating a correct switch occurred Because the video signals arriving at the router on (HD) line 7 at approximately the mid-point of are scrambled when a switch occurs from one the line. source to another the receiving device no longer receives a coherent set of data and is therefore page 3
Example : Output status from a frame synchornizer I/O Delay shows total delay through the frame synchronizer in ms Because switch line length is longer than standard (640 pixels) the card detects a switch has occurred, and because the switch occurred on a blanked line the module was able to detect the corruption following the switch and indicate the pixel where the corruption started the switching point. Correction of timing errors Timing errors can be divided into two main categories; a. Where the all of the signals share a common clock reference and therefore have exactly the same line repartition rate but where pictures may be displaced with respect to each other. b. Where video sources have a different reference clock from the local video feeds and therefore the pictures could be displaced with respect to local sources and the amount of displacement is changing. n example of (a) is when all video sources originate in the same facility, the difference in timing is caused by varying cable lengths and processing delays through equipment. Situation (b) commonly occurs when a video feed from an external source arrives at a TV station. The originating OB vehicle is locked to its own SPG and the equipment at the TV station is referenced to the local SPG. It is common for SPGs to use signals received from a GPS satellite as the source of the reference for their master clocks however GPS is normally only accurate to part in million, which equates to a variation of more than 74 HD-SDI pixels. Therefore even if both remote and local SPGs are locked to a GPS signal there still no absolute timing relationship between them. There are three common techniques for correcting timing issues within a broadcast facility a. Individually timing all devices so that are perfectly aligned at a single switching point. b. Providing a buffer which is sufficient to accommodate the largest variation in timing between the signals to be switched. c. Timing the sources so that are closely aligned (within -line) and then providing a device which automatically corrects any errors that still exist in the picture following the switch. Individual timing of all devices Even in a simple installation it is a very difficult task to accurately align the output timing of a number of devices. Some equipment does not provide sufficient degrees of accuracy in their internal adjustments, adding even simple additional equipment into a signal path will require the source to be re-timed and if a device has to feed two different switching points these have to be in exactly the same timing plain or timing adjustments would need to made by varying the level of the cables between the device and one of the switching points. This process is not, however, impossible but needs a great deal of care and considerable time to achieve the desired result. Since the introduction of affordable devices to correct timing errors this method of timing has become almost redundant. Correcting large timing variations using a frame synchronizer Frame Synchronizer has sufficient storage capacity to hold a complete frame of video in memory. The incoming signal s horizontal and vertical syncs and the frame timing data is used to determine which memory locations the incoming video should be written to and the local reference signal is used to lock the read-clock cycles so that the output the stored information in the correct sequence to generate an output picture timed to the local station reference. lthough this method of timing signals can accommodate large differences in picture timing between the source material and the local station timing reference it cannot permanently mask a large difference in clock rates. For example if the Sync Pulse Generator (SPG) at a remote location, which is providing the source picture, is running 0.0% faster than the local SPG then after 0,000 frames (less than 7 minutes in a 50Hz system) it will have generated one more frame than the local system has had time to read page 4
from memory. If this occurs the additional frame is dropped from the output of the Frame Synchronizer which may result in slight jump-in-time in the output. similar situation would occur if the source location s SPG was running slower than the local device and therefore not generating as many frames as the local system requires to read from memory. In this case the Frame Synchronizer would need to display a repeated frame on its output in order to maintain the correct output rate. The timing of the pictures being written into the Frame Synchronizer s memory are determined by the clocks contained within the input video signal. If a switch between source and source B does not occur at a frame boundary or the two sources are not co-timed at least one output frame will contain material from two, or more, input frames, and this material may be displaced vertically compared to the original frame, e.g. it is possible for the end of the frame from the video source that has just been switched too to appear in the center of the previous frame until the next full frame is written into the Frame Synchronizer s memory. Because a Frame Synchronizer can store a complete frame of information it is possible to set the output timing to meet the facilities requirements no matter how far the source is displaced in time relative to the local timing reference. It should be noted that there is a small in built delay through a Frame Synchronizer module and therefore if the incoming video and the local timing reference are closely matched the Frame Synchronizer may need to introduce almost a frame s delay to bring the picture back into alignment. Below are three examples showing the likely output from a Frame Synchronizer if the input switch occurs during the current frame to the start of a new frame (Example 3), during the current frame to very near the end of a new frame (Example 4), and during the current frame to soon after the start of the new frame (Example 5). FRME SYNC Example 3: Frame synchronizer output when source B delayed with respect to source (switch occurs at the start of frame ) is followed by frame until the point where the switch to source B occurred The input to the Frame Synchronizer changed during the mid-point of frame to the start of frame t the switching point the Frame Synchronizer started to write to the beginning of the memory block and only therefore the information available for output was from the previous frame () Because is at the start of a frame the synchronizer starts writing the video information to the first memory location The next output frame is completely formed of data from source B () Example 3 Example 4 Example 3 page 5
FRME SYNC Example 4: Frame synchronizer output when source B is advanced with respect to source (switch occurs near the end of frame ) The input to the Frame Synchronizer changed from the mid-point of frame to near the end of frame Because is near the end of a frame (and therefore there is only line-timing information available from the incoming video) the synchronizer starts writing the incoming video from the point the switch occurred Example 3 arrives When frame the synchronizer starts writing the incoming video at the start of the memory block Because frame did not have vertical timing information the frame synchronizer wrote the information into the next available lines however this placed the section of video in the wrong place within the frame Because frame was very short there was insufficient information to re-write all of the memory locations and therefore information remained from frame The next output frame will be completely formed of data from source B () FRME SYNC Example 43 ExampleSynchronizer Example switch 4 Example 5with respect Example 5: Frame memory use during of sources (Source B delayed to Source. Switch occurs at a point near the end of frame and the beginning of Frame ) The input to the Frame Synchronizer changed during the mid-point of to an earlier point in frame Because is not at the start of a frame (therefore Example 3 there is only line timing information) the synchronizer starts writing the incoming video at the point the Example 5 switch occurred Information from frame was written into memory until the memory was full Because frame did not have vertical timing information the frame synchronizer wrote the information into the next available lines however this placed the section from near the top of frame at the bottom of the output frame. Because the start of frame occurred after the start of the output frame another frame of corrupted video will be played out. Note: there is no corruption to the output timing information Example 4 3 The Frame Sync detects the start of frame and commences writing to the start of memory Example 4 Example 5 Example 5 page 6
Seamlessly switching closely timed signals using Line Synchronizer (utophaser) Line Synchronizer (utophaser) is designed to mask the switching between two closely timed signals. xon s utophasers have sufficient memory to store up to 44 pixels (an 080i50 HD line has 640 samples) therefore the two signals being switched should be timed to within a maximum variance of +/- 0.8 of a line. It should be noted this is the extreme variation the module can accommodate and a smaller difference in timing should be considered to be the maximum in realworld situations. utophasers are normally used to mask disruptions to the SDI signal caused by switching signals in routers. Following the switch the utophaser will adjust the amount of delay through the device to effectively align the two video signals, ensuring the correct amount of data is output on the switching line. The utophaser masks the discontinuity in the polynomial produced data in the SDI stream caused by a switch by always inserting blanking into the whole of the line nominated to contain the switching point e.g. in a 65 line 50Hz signal the whole of Line-6 is blanked on the output of the utophaser. n utophaser can provide a small amount of output timing adjustment however this will also affect the range of the correction the device is able to use. Below are examples showing the way in which an utophaser reads incoming video into its video memory store and adjusts its internal delay to compensate for slight timing differences between the two sources. LINE SY During the switch line the utophaser blanks the output for the total duration of the line. B-7 Blanked Output of utophaser delayed to correct for slight system timing error -7 B-7 Input to utophaser switches at the midpoint of HD line 7-7 Example 6: utophaser used to mask the switch between two correctly timed sources Delay Increased Example 6 Example 7 page 7
LINE SYNC The utophaser increases the amount of delay to compensate for Source B being slightly advanced Blanked During the switch line the utophaser blanks the output for the total B-7 duration of the line. -7 B-7-7 lthough Line 7 from Source B was not sufficient to fill the utophaser s memory when it detects the beginning of Line 8 it starts to write that into the correct memory location Delay Increased Delay Increased Example 7 Blanked B-7-7 Example 7 The utophaser will continue to write information from Source B into memory until the memory allocated for one line is full. The remaining information will be lost Example 6 Blanked Input to utophaser switches at the midpoint of Source line 7. Source B is delayed with respect to Source and therefore there is more than ½-line remaining from Source B, resulting in a long Line 7 Example 8: utophaser used to mask switch between two sources, where source B is delayed with respect to source 8 Insufficient video information to fill all memory locations 7 Input to utophaser switches at the midpoint of Source line 7. Source B is advanced with respect to Source and therefore there is less than ½-line of line 7 remaining from Source B to be rear into memory, resulting in a short Line 7 LINE SY Example 7: utophaser used to mask the switch between two sources, where source B is advanced with respect to source 6 During the switch line the utophaser blanks the output for the total duration of the line. The utophaser reduces the amount of delay to compensate for Source B being slightly delayed Delay Decreased Example 8 page 8
xon Modules There are a large range of Synapse modules which have either utophaser or Frame Synchronizers, these can be found as specific modules such as the HFS00 HD-SDI frame synchronizer or the signal timing block is combined with other functionality such as in the GDL00 3G legalizer. Some further examples of Synapse modules with utophaser or Frame Synchronizer functionality are shown below. Example 9: GEB/HEB990 - "Twins" single/dual channel embedder G/HEB990 G/HEB950 - G/HEB900 G/HEB550 G/HEB500 utophaser on each input = SINGLE CHNNEL B = DUL CHNNEL 3Gb/s, HD, SD IN 3Gb/s, HD, SD IN UTO PHSER Eq UTO PHSER Eq x OR x DJUSTBLE OFFSET 0-500ms B EMB B EMB B 3Gb/s, HD, SD OUT S00 INSERTION UTO MUX DJUSTBLE OFFSET 0-500ms B EMB C B EMB D 3Gb/s, HD, SD OUT METDT UDIO INPUT UDIO INPUT UDIO INPUT 3 UDIO INPUT 4 4 Ch 4 Ch UP TO 3X6 CHNNEL PRESET BSED INPUT MULTIPLEXER OPTION BORD (NLOG OR ES/EBU) UDIO INPUT 5 UDIO INPUT 6 UDIO INPUT 7 UDIO INPUT 8 4 Ch 4 Ch GPI/O OPTION BORD (NLOG OR ES/EBU) µp PLL 4 Ch 4 Ch 4 Ch 4 Ch UDIO INPUTS FROM SYNPSE BUS REFERENCE INPUTS 3 RCK CONTROLLER 4 INTERNL SYNPSE BUS Example 0: GXT/HXT0 - Up/down/cross converter designed for transmission usage Frame Synchronizer in each processing path. GXT00 - HXT00 - GXT0- HXT0 3Gb/s, HD, SD IN 3Gb/s, HD, SD OUT LOW LTENCY UP-DOWN-CROSS CONVERSION - RC - VIDEO BYPSS - EQ GPI INPUT SELECT 3Gb/s, HD, SD IN [QUD SPEED] FRME SYNC COLOR CORR. FD S06 WSS VI 4 GROUP EMBED 3Gb/s, HD, SD OUT WSS-VI-S06 DETECTION 3Gb/s, HD, SD OUT B LOW LTENCY UP-DOWN-CROSS CONVERSION - RC - VIDEO BYPSS - EQ FRME SYNC FD S06 WSS VI 4 GROUP EMBED 3Gb/s, HD, SD OUT B SHUFFLING 6X6 MUX 0 ONLY UDIO GIN 0 ONLY UDIO V-FDE & TRCK 6 CHNNEL DEEMBEDDING COLOR CORR. BY-PSS QUD SPEED MODE 0 ONLY NORML DD-ON MODE GPI #5 OUT # REFERENCE INPUTS 4CH 4CH 4CH 4CH IN IN IN IN 3CH IN TO DD-ON RCK CONTROLLER 3CH OUT QUD SPEED MULTIPLEXING UDIO BUS TDM DE-MUX FROM DD-ON PLL μp [LINUX] TDM MUX OR 3 4 NORML DD-ON UDIO BUS INTERNL SYNPSE BUS Example : GFS/HFS0 - Frame synchronizer utophaser and Frame Synchronizer on the input of the module GFS00 GFS0 - HFS00 - HFS0 SFS00 SFS0 3Gb/s, HD, SD OUT 3Gb/s, HD, SD IN CVBS IN 3Gb/s, HD, SD IN EQ CVBS DEC. 3Gb/s. HD, SD OUT FRME SYNC & OFFSET UTOPHSER COLOR CORR. EMB EMB B EMB C EMB D 3Gb/s, HD, SD OUT 3 EQ 3Gb/s, HD, SD OUT 4 PRESET BSED NNEL UDIO GIN, PHSE CONTROL ( 0 ONLY) 6 CHNNEL DEEMBEDDING PRESET BSED NNEL UDIO GIN, PHSE CONTROL ( 0 ONLY) PRESET BSED SHUFFLING 48X6 MUX ( 0 ONLY) -UDIO - 6 CHNNEL DEEMBEDDING PRESET BSED NNEL UDIO GIN, PHSE CONTROL ( 0 ONLY) PRESET BSED NNEL UDIO GIN, PHSE CONTROL ( 0 ONLY) GPI #5 OUT # 6 CH ΜP [LINUX] RCK CONTROLLER PLL REFERENCE INPUTS BUS MULTIPLEXER EMBEDDING OR DE-EMBEDDING 3 TRCKING OUT 4 INTERNL SYNPSE BUS page 9
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