CCD Delay Line Series MN390S NTSC-Compatible CCD H Video Signal Delay Element Overview The MN390S is a H image delay element of a f SC CMOS CCD and suitable for video signal processing applications. It contains such components as a frequency-doubler circuit, a shift register clock driver, a 90-stage CCD analog shift register, and a resampling output amplifier. The MN3S drives and samples the 90-stage analog shift register using a redoubled version of the supplied clock signal with a frequency 7. MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces a delay of H (the horizontal scan period). Features Single.0 V power supply Energy-saving design based on CMOS process Low EMI levels from clock during driving Applications VCRs, Video cameras Structure and Operation The MN390S consists of the operational s shown in the diagram. Frequency-doubler circuit When the 7. MHz of the doubled NTSC color signal subcarrier frequency is ted from the clock pin XI,.3 MHz clock of fourfold frequency of color signal subcarrier is generated by this circuit. Clock driver This generates two transfer clock signals, ø and ø, synchronized with the.3 MHz clock signal from the frequency-doubler circuit. It also generates the sampling clock signals øs and øs', resampling clock signal øsh, and reset clock signal ør that have adjusted timing relations with ø and ø. CCD analog shift register This first converts the analog signal from the signal pin into a voltage signal, and s it into 90-stage analog shift register. Pin Assignment V BB V DD V SS 3 ( TOP VIEW ) SOP00-P-0A The shift register samples the shift register with the sampling clock øs, and converts the results to charges, and uses transfer clocks ø and ø to transfer the results to the following, the charge detection, where the charges is converted into a voltage signal. Resampling output amplifier In the output amplifier, this voltage signal is done Sample-and-Hold by resampling, and Y-signal as it is outputted at Vo. Operation The following is an explanation of delay line operation. The waveforms driving the shift registers are as shown in the timing chart on page. The signal voltage sampled during the interval between t=0 and t=τc (where τc is one-half the sampling interval) appears at the output pin at the point t=3τc. 7 V GC PCOUT & VCOIN XI includes following four Product lifecycle stage. SDB00077BEM
MN390S CCD Delay Line Series Block Diagram 3 V DD 7 V GC Bias circuit Booster circuit XI amplifier Phase comparator Timing PCOUT & VCOIN /nd frequency doubler VCO CCD 90 stages ø driver ø driver V SS detection øs driver ør driver Resampling output amplifier Substrate bias generator includes following four Product lifecycle stage. V BB
CCD Delay Line Series MN390S Pin Descriptions Pin No. Symbol Function Description Remarks Signal pin V BB Substrate connection pin Negative voltage pin 3 V DD Power supply V SS Ground XI 7. MHz clock pin PCOUT & VCOIN Phase comparator output and voltage controlled oscillator 7 V GC Output gate connection pin Signal output pin Operating Conditions Parameter Symbol min typ max Unit Power supply voltage V DD.7.00. V Input clock frequency f ck 7.909 MHz Signal bandwidth Input clock amplitude (sine wave) V ck 0. 0.3.0 V P P Ambient temperature Ta 0 0 C Electrical Characteristics V DD =.0V, V ck =0.3V P-P (sine wave), V in =0.V P-P (sine wave), f ck =7.909MHz, f sig =00kHz, Ta= C Parameter Symbol Conditions min typ max Unit Power supply current I DD 3 ma Signal bandwidth BW 3 db for 00 khz value.. MHz Insertion gain IG f sig =00kHz... db Total harmonic distortion THD f sig =00kHz. % Signal-to-noise ratio S/N Signal output (V P-P )/noise output (rms) db Clock leak NC 7. MHz component/main output signal 0 0 db Clock leak NC.3 MHz component/main output signal 0 0 db Delay τ D 3.3 µs Output impedance Zo 0. 0.9 kω Input bias voltage V BIN Applied to from signal pin. V Output bias voltage V BO Applied to output from signal output pin. V Substrate voltage V BB. V includes following four Product lifecycle stage. 3
MN390S CCD Delay Line Series Timing Chart 90 stages t=0 t=τc t=3τc ø ø øs øsh ør A A includes following four Product lifecycle stage. A A
CCD Delay Line Series MN390S Application Circuit Example V 3 V DD + 0µF 0.µF 7 V GC 0.0µF Signal Clock + 0.7µF XI 000pF amplifier PCOUT & VCOIN 0.0µF 0Ω Timing Phase comparator Bias circuit /nd frequency doubler VCO 700pF CCD 90 stages ø driver ø driver V SS Booster circuit detection øs driver ør driver Resampling output amplifier Substrate bias generator V BB 0.0µF Signal output 330Ω includes following four Product lifecycle stage.
MN390S CCD Delay Line Series Package Dimensions (Unit: mm) SOP00-P-0A.7 0.±0. 0. 0.±0. 0.3.±0.3.±0.3 New Package Dimensions (Unit: mm) SOP00-P-0G (Lead-free package) 0. 0..±0. Note) The package of this product will be changed to the following lead-free type (SOP00-P-0G). (0.0).7.0±0.0 Seating plane 0.0 +0.0-0.0 0.0.30±0.0 0.0±0.0.±0.0.0±0.0.7 max. 0. +0.0-0.0.0±0.3 (.0) 0.0±0.0 Seating plane 0 to 0 includes following four Product lifecycle stage.
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