University of Maiduguri Faculty of Engineering Seminar Series Volume 6, december 2015 4-BIT SERIAL ADDER WITH ACCUMULATOR: MODELLING AND DESIGN USING SIMULINK, HARDWARE REALIZATION USING SPARTAN 6 FPGA P. Y. Dibal and C. U. Ngene Department of Computer Engineering, University of Maiduguri yoksa77@gmail.com; +2348036273666 Abstract A serial adder with accumulator is an important digital electronic component used extensively in addition operations. In this paper, the modelling and design of a 4-bit serial adder with an accumulator is carried presented using Simulink, and then realized using the Spartan-6 FPGA. Modelling of electronic components is usually a challenging task, as it involves the use of equations which describe the component to be modelled and imagination about what the behaviour of the component should look like. The paper begins with the introduction, in which the length and breadth of the application of the serial adder with accumulator is discussed. The paper then presents the methodology of the design, which involves the use Simulink the block based modelling of MATLAB. Each sub-section of the serial adder with accumulator, which includes the control circuit, shift registers, full adder, and the D-flip flop are then analyzed and then modelled using Simulink. Using a data set in a table, the operation of the serial adder with accumulator is described analytically by considering four clock cycles. Using the model achieved in Simulink, the design is then realized in Hardware Description Language, from which a bitstream file is generated and then applied to the Spartan-6 FPGA. The results of the modelling in Simulink are compared with that of the Spartan-6 FPGA, and a conclusion is finally drawn, which confirms that stated objective of the paper has been realized. Keywords: FPGA (Field Programmable Gate Array), LED (Light Emitting Diode), SI (Serial Input), Sh (Shift) 1.0 Introduction Addition is an important operation in digital electronics, digital signal processing, control system, and biomedical image processing. The performance of a digital system in terms of speed and accuracy is greatly determined by the performance of the adders in that digital system. Adders are very critical components in digital systems because of the fact they are extensively used in fundamental digital operations such as multiplication, division, and subtraction. Most DSP algorithms perform multiplication and accumulation processes; the multiplication processes rely heavily on adders. Hence, the performance of a digital adder greatly affects the performance of circuits that execute binary operations. Adders come in various flavors and complexity, and the choice of what type of adder to use depends on the performance required and the speed with which the binary operation is to be performed. For instance, the Kogge-stone adder (Rahda, M. et al, 2013) also called a parallel prefix adder is a high-performance adder with a very fast computation time. Other types of adders are the ripple carry adder, carry look ahead adder, carry save adder, and carry select adder (Illakiya, P. et al, 2014). Serial binary addition is a binary Seminar Series Volume 6, 2015 Page 39
operation that is achieved using a flip-flop and a full adder. The carry-out signal from the full adder is fed to the flip-flop on each clock cycle. The serial adder with accumulator (Karris, 2007) shown in figure 1 is a special type of adder that uses two shift registers, a D flip-flop, a full adder, and a control circuit to achieve serial binary addition. Figure 1.1: Serial Adder with Accumulator 2.0 Methodology In order to achieve successful modelling and design implementation of the serial adder with accumulator, the paper presents a 4-bit serial adder with accumulator in figure 2.1 as shown below. Figure 2.1: 4-bit Serial adder with accumulator Figure 2.1 shows the 4-bit serial adder with accumulator, comprising four sub-sections, i.e. the control circuit, the two shift registers, the full adder and the D flip-flop. 2.1 Control circuit The control circuit is designed such that when it receives a start signal N, it will output another signal Sh = 1 for four clock cycles. In each of the clock cycles, the value of the start signal N determines the value of Sh as shown by the state graph in figure 2.2 Seminar Series, Volume 6, 2015 Page 40
Figure 2.2: State graph of control circuit The state graph shows that when the control circuit is in state S0, the control circuit remains in that state as long as N = 0. However, as soon as N = 1, the control circuit transits to state S1, outputting Sh=1. From state S1 to S3, the control circuit outputs Sh = 1 regardless of the value of N. From the foregoing description, the state graph is clearly a Mealy machine. 2.2 Shift registers The shift register (Anil, 2007) is used for data storage, and data transfer. The shift register usually forms an important bridge between main digital systems and an input/output channel; hence, the data appearing at the output of the shift register could be data of an encoding matrix, or data present at the output of a microprocessor waiting to be fed to the driver circuitry of output devices. The two shift registers shown in figure 2.1 are 4-bit serial-in serial-out shift registers implemented using D flip-flops. Figure 2.3 below shows the structure (Anil, 2007) of this type of shift register. Figure 2.3: Serial-in Serial-out shift register The operation of the shift-register is such that when a CLEAR signal is asserted, all the flip-flop resets their Q outputs to 0s. The flip-flops shown in figure 2.3 respond to the LOW-to-HIGH transition of the clock pulses as indicated by their logic symbols. In figure 2.4, during the first clock transition, the QA output transits from 0 to 1 ; the outputs of the other flip-flops remain Seminar Series, Volume 6, 2015 Page 41
Figure 2.4: Waveform analysis of 4-bit Serial-in Serial-out shift register in the logic 0 state as their D inputs were in the logic 0 state at the time of clock transition. During the second clock transition, the QA output goes from 1 to 0 and QB output goes from 0 to 1. In the third clock transition, QC output goes from 0 to 1, QB output goes from 1 to 0. In the fourth clock cycle, QD output goes from 0 to 1, QC output goes from 1 to 0. Hence, a logic 1 bit present at the data input prior to the occurrence of the first clock, reaches the QD output at the end of four clock transitions. The design shown in figure 2.1 has two 4-bit shift registers that will hold the two 4-bit numbers to be added. At the left of each shift register is a box, which has three inputs, namely Shift (Sh), Serial Input (SI), and the clock input. The mechanism of operation of the shift registers is such that when Sh = 1 and the clock is pulsed, SI goes into x3 (or y3) as the contents of the register are shifted right one position. The accumulator, which is the X register has its content replaced by the sum of X and Y after four bits. The addend, which is the Y register is connected in a cyclic fashion such that its original content is restored after four bits. 2.3 Full adder The full adder (Anil, 2007) shown in figure 2.5, is a digital circuit that adds three bits (xi, yi, ci) to produce a SUM and a CARRY output. The operation of the full adder is characterized (Brown and Vranesic, 2009) by the following equations and truth table. Seminar Series, Volume 6, 2015 Page 42
Table 2.1: Truth table for a full adder Figure 2.5: Full adder In the design shown in figure 2.1, the SUM output of the full adder is fed into the SI input of the accumulator, while the CARRY output of the full adder is fed into the D-input of a D flip flop, which is then clocked out as the ci input of the full adder. 2.4 Carry D flip-flop The D flip-flop used in this design is a carry D flip-flop because the D input of the flipflop obtains its signal from carry output of the full adder. The clock input of the carry D flip-flop is connected in such a way that only when Sh = 1 AND the clock is pulsed that the D flip-flop will transfer the content of its D input to the Q output. 2.5 Design operation The operation of the 4-bit serial adder with accumulator is illustrated by table 2.2 below. Table 2.2: Data operation of a 4-bit serial adder At time t0, the full adder has the inputs x0 = 1, y0 = 1, and ci = 0; hence sum0 = 0 and ci+1 = 1. When the first clock occurs, sum0 is shifted into the accumulator, whereas the Seminar Series, Volume 6, 2015 Page 43
remaining digits in the accumulator are shifted right one position. The same shift pulse stores c1 in the carry flip-flop and cycles the addend register right one position. The next pair of bits, x1 = 0 and y1 = 1, are now at the full adder input, and the adder generates the sum and carry, sum1 = 0 and c2 = 1. The second clock pulse shifts sum1 into the accumulator, stores c2 in the carry flip-flop and cycles the addend register right. Bits x2 and y2 are now at the adder input, and the process continues until all bit pairs have been added. After four clocks (time t4), the sum of X and Y is in the accumulator, and the addend register is back to its original state. 3.0 Design/modelling The design and modelling of the 4-bit serial adder with accumulator is executed using Simulink. The Simulink tool is the graphical version of MATLAB, and it is very powerful and versatile. The design is broken into parts, starting from the control circuit right through to the full adder. 3.1 Control circuit design/modelling Figure 3.1 below shows the design/modelling of the control circuit in Simulink. Figure 3.1: Simulink Design/Model of Control circuit 3.2 Shift register design/modelling The Accumulator, and the Addend are both 4-bit shift registers. The design of the 4-bit shift register was realised in Simulink as shown in figure 3.2: Seminar Series, Volume 6, 2015 Page 44
Figure 3.2: Simulink Design/Model of Shift Register 3.3 Full adder design/modelling The full adder as shown in figure 2.5, is characterized (Anil, 2007) by the following equations: The design of the full adder in Simulink is shown in figure 3.3 below: Figure 3.3: Simulink Design/Model of full adder The complete design/model of the system is shown in figure 3.4. Figure 3.4: 4-bit Serial Adder with Accumulator Design/Model in Simulink Seminar Series, Volume 6, 2015 Page 45
4.0 Simulation results and analysis Upon simulation the following results were obtained as depicted in figure 4.1 Figure 4.1: Simulation results of 4-bit Serial Adder with Accumulator As can be seen in figure 4.1 at t0, the Accumulator has the value 0101, while the Addend has the value 0111; this confirms the data value shown in table 2.2. At time t4, the Accumulator has the value 1100, while the Addend has the value 0111; this again confirms the data value in table 2.2 5.0 Hardware realisation using spartan-6 FPGA Having successfully designed and modelled the 4-bit serial adder with accumulator in Simulink, the next step is to effect the hardware realization using the Spartan-6 FPGA, which is housed on the Nexys-3 board, a product of Digilent Inc. Figure 5.1 shows the Spartan-6 FPGA (Nexys-3 Manual, 2013). Figure 5.1: The Spartan-6 FPGA Seminar Series, Volume 6, 2015 Page 46
The Spartan-6 FPGA is connected to 8 LEDs, as shown in figure 5.1. Hence we will connect the Addend register from LD7 to LD4, and the Accumulator from LD7 to LD0. With this configuration, the hardware realization is shown in figure 5.2. Figure 5.2: Spartan-6 FPGA hardware realization 6.0 Conclusion The modelling/design of a 4-bit serial adder with accumulator was achieved using Simulink, and the hardware realization using Spartan-6 FPGA was also realized. From the results obtained, it was seen clearly that the 4-bit serial adder with accumulator functioned exactly as was described in the data operation table of the design. References Anil, K.M., 2007. Digital Electronics: Principles, Devices, and Applications. West Sussex. John Wiley & Sons Brown, S., Vranesic, Z., 2009. Fundamentals of Digital Logic with VHDL Design. 3 rd Ed. New York. McGraw-Hill Digilent Inc. 2013. Nexys 3 Board Reference Manual. Illakiya, P., Somasundareshwari, D., Babukannan, D., 2014. Design of Low Power Fir Filter with Differnt type of Adder and Multiplier Analysis Based on Distributed Arithmetic. Journal of NanoScience and NanoTechnology. Vol 2(5) pp 582-586 Karris, S,T.,2007. Digital Circuit Analysis and Design with Simulink Modelling. 2 nd Ed. California. Orchard Publications Rahda, M., Srinivasarao, C,H., Rao, S, M., 2013. A novel Approach of an Efficient High BIT Serial Multiplier Design using Ripple Counters and Full Adder. International Journal of software & Hardware Research in Engineering. Vol 1(2) pp. 1-6 Seminar Series, Volume 6, 2015 Page 47