YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in an S-R latch, the rising and falling edge-triggered nature of various flip-flops, and the effects of switch bounce are observed. Introduction to ripple counters, learning the use of J-K flipflops in the design of a simple ripple counter. General Information: The output of a combinational circuit is only a function of the present inputs. The output of a sequential circuit is a function not only of the inputs but also of the state. Sequential circuits form the basis of registers, memories, and state machines, which in turn are vital functional units in digital design. The most basic sequential unit is the S-R latch. From this basic circuit flip-flops are constructed, and from flip-flops, the registers, memories, and state machines can be made. The basic S-R latch has two inputs, S and R, and two outputs, Q and Q I. Q I is the complement of Q. The S input is used to set Q to 1 and R input is used to reset Q to 0. As can be seen, the NOR implementation has active-high input. This indicates that the set or reset operation is performed by temporarily raising the set or reset line to 1. The NAND implementation has active-low inputs. Because of the feedback to the inputs of the OR forms, the output will remain set or reset even after the set or reset is gone thus the memory capability of the latch. 7-1
The output of the S-R latch changes at the same instant the input dictates a change. This is referred to as asynchronous operation. But in most digital circuits, the timing of events is critical. Typically a clock is used to synchronize the operation of the various functional units in the circuit. To perform this environment, the latch must only change state when a clock signal indicates that it is the time. This is refered to as synchronous operation. Latches modified to operate synchronously are called flip-flops. Note: Q+ indicates the next state of the output 7-2
The J-K flip-flop is simply an S-R flip-flop that has been modified so that both inputs can be activated at the same time. Altough in the S-R flip-flop this condition was considered to be invalid, in the J-K flip-flop this condition toggles the output on successive clock cycles. J-K Flip Flop The D or Data flip-flop has just one control input, D. The output of the flip-flop is set to whatever the D input is on each clock cycle. D Flip Flop In general, a counter is a sequential circuit that goes through a set of given states on successive clock cycles. Usually they are sequential binary states. A state is simply the binary value represented by the outputs of the counter. A counter to sequence from 0 through 15 requires four outputs to represent the four bit positions. Counters are useful in many applications, including timing, multiplexing, and, of course, counting. Asynchronous Ripple Counters If a J-K flip-flop is used as a T flip-flop (by tying J and K high), the output changes state on each clock cycle. Therefore, after two clock cycles the output of the flip-flop completes one cycle. If the output of this flip-flop were then used as the clock input to a second T flip-flop, the output of the second flip-flop would cycle at half the rate of the first flip-flop. Each additional flip-flop added in this manner would cycle at half the rate of the preceding flip-flop. 7-3
As can be seen, by considering the output of the first flip-flop (Q a ) as the 1s digit and the output of the second flip-flop (Q b ) as the 2s digit, we have simply binary counter sequencing from 0 through 3 and then repeating. J and K inputs are to be 1. Note that, state transitions occur on the falling edge of the clock. Actually this isn t true, it takes time from the falling edge of the clock until the output of the flip-flop changes state. For the 7476 flip flop this delay is approximately 40ns. For the 2-bit ripple counter, the 1s digit (Q a ) changes 40ns after the falling edge of the clock. Since Q a is the clock input for the second flip-flop, the 2s digit (Q b ) changes 40ns after the falling edge of the Q a and 80ns after the original clock edge. Since each flip-flop does not change state on a common clock signal, it is not considered a synchronous device. Generating Clock Signals with Ripple Counters A ripple counter can be used to divide the rate of one clock cycle to generate another clock signal of the desired frequency. Assume a digital circuit has a clock running at 10 KHz. In addition to the 10 KHz signal, the circuit also requires a 5 KHz clock. Instead of having separate clock circuits for each of these frequencies, we can obtain the 5 KHz clock by dividing the 10 KHz signal by 2. The output of a T flip-flop cycles at half the rate of the input clock. If a 10 KHz signal clocks the flip-flop, the output cycles at one-half that rate, or 5 KHz. Thus a 1-bit ripple 7-4
counter performs a divide-by-2 operation. If a second T flip-flop is added, it cycles at half of the rate of the first flip-flop, one-fourth rate of the original clock. Thus a 2-bit ripple counter performs a divide-by-4 operation. So far the number of states in a ripple counter s sequence has always been a power of 2. Obviously to divide a clock cycle by 5, the counter must have five states. To do this, we use a regular ripple counter, but with additional gating, we force it to reset to 0 after five states. In this case, the counter will count 0, 1, 2, 3, 4 and then repeat. Somehow, instead of going from state 4 to state 5, the ripple counter must be forced to go from state 4 to state 0. using the asynchronous-clear inputs on the J-K flip-flop, the ripple counter can be reset to 0 when needed. In this example, it must be reset to 0 when the ripple counter attempts to switch to state 5. As can be seen, state 5 is detected by a NAND gate when (Q c ) and (Q a ) are both 1. At this instant the NAND gate turns on and resets the counter to state 0. This operation results in the complex timing diagram. 40ns after the falling edge of the clock, Q a goes to 1, leaving the counter in state 5. At this instant, both inputs to the NAND gate are 1, and 10ns later (switching delay of the NAND gate), the output of the NAND gate goes to reset the flip-flops. The clear operation on a 7476 J-K flip-flop takes a maximum of 40ns. Thus the output is finally reset to 0, 90ns after the falling edge of the clock. The resulting square wave generated by the divide-by-5 counter is not symmetric. It is 0 for four input-clock cycles (000 thru 011) and 1 for one input-clock cycle and divide-by-5 output taken from Q C. Generating clock signal is not the only applications of counters. Counters are used in many applications, frequency measurement, and analog-to-digital converters. Divide-by-5 Output Lab Equipments : 7-5
74LS00 2 input NAND 74LS04 Hex Inverter 74LS76 Dual JK FF 74LS74 Dual JK D Procedure : 1) Wire the NAND implementation of the D latch. Verify proper operation of the latch by alternately setting and resetting the output using the D input and changing the clock input. 2) a. Wire a JK Flip Flop, and verify its operation for different inputs and clock rates. b. Wire a D Flip Flop, and verify its operation for different inputs and clock rates. Questions : 1) Using D Flip-flop, design a simple 2-bit counter sequencing from 0 through 3. Draw its state and logic diagram. 7-6