TW98 NTSC/PAL Analog Video to Digital Video Decoder

Techwell, Inc. TW98 NTSC/PAL Analog Video to Digital Video Decoder Preliminary Data Sheet 11/19/99

Introduction Features Techwell s TW98 is a high quality NTSC and PAL video decoder that is designed for multimedia applications. TW98 uses the mixed-signal 3.3V CMOS technology to provide a low-cost and low-power integrated solution. Minimum external components are required due to its integrated analog front-end containing AGC, clamping, and two high speed ADCs. Adaptive comb filter and Y/C processing based on proprietary technologies produce exceptionally high quality pictures. An internal scaling engine offers arbitrarily filtered down scaling of the output picture. Built-in Close Caption decoder and VBI data pass-through support data applications such as Intercast. The TW98 can interface with major GUI accelerator ICs without glue logic. Supports NTSC (M) and PAL (B, D, G, H, I) Four software selectable composite video inputs, or three composite and one S-video inputs Internal automatic gain control and clamping Two 1-bit ADCs Proprietary 2-line adaptive comb filter Y/C separation Adaptive color demodulation with high color bandwidth Proprietary nonlinear image enhancement and noise suppression Digital subcarrier PLL with <.1 degree phase error Advanced synchronization processing for VCR fast forward, backward, and pause mode Programmable hue, brightness, saturation, contrast, sharpness control, and noise suppression Automatic color control and color killer Horizontal and vertical filtered scaling with arbitrary scale down ratio Programmable output cropping VMI 1.4 compatible 8-bit or 16-bit pixel interface CCIR-61 compatible YCrCb (4:2:2) output format Closed caption decoding VBI data pass through, raw ADC data output for Intercast Two wires MPU serial bus interface Power-down mode Typical power consumption.4w Single 55 MHz, 54MHz or 27MHz crystal 5V tolerant I/O 3.3 V power supply 1-pin PQFP or LQFP package

Applications! Multimedia PC! Desktop video! Video conferencing! Interactive video! Image processing Functional Description TW98 ADC data VBI data passthrough Cin Buffer ADC Yin DC suppression VD[15:8] MXOUT Adaptive demod VD[7:] MUX MUX1 MUX2 MUX3 MUX Clamp / AGC ADC 2H adaptive comb Y/C separation C Y CbCr Luma/ Chroma processing VSYNC HSYNC FIELD Analog control Sync processing Skew corrector / scalar Sync Video interface HACTIVE DVALID VCLK CBFLAG VACTIVE LVALID CLKx2 CLKx1 PDN Clock MPU Serial Interface Closed Caption decoder Test Logic OE SDA SCL TRST TCK TMS TDI TDO CCVALID 55MHZ Figure 1 Detailed block diagram of TW98 TECHWELL 2

Overview Analog Front-end Techwell s TW98 is a high quality NTSC/PAL video decoder that is designed for multimedia applications. It uses the mixed-signal 3.3V CMOS technology to provide a lowpower integrated solution. Its analog front-end contains a MUX that can select from four composite video sources or three composite videos and one S-video. The front-end contains all the necessary circuits such as AGC and clamping to simplify the system design. Two 1-bit ADCs convert inputs into digital signals for processing. The TW98 uses proprietary technique like adaptive comb filter for chroma and luma processing to achieve high video quality. The image enhancement uses a nonlinear method to enhance picture sharpness with little overshooting. It can also effectively suppress noise. The advanced synchronization processing can produce stable pictures for non-standard signal such as those produced by VCR during fast forward, backward or pause. The high quality scaling-engine uses multi-tap polyphase decimation filter to reduce aliasing effects. It can be programmed to scale-down the output picture to an arbitrary ratio with cropping. The TW98 supports flexible pixel interface. It outputs YCrCb (4:2:2) data stream over 8-bit or 16-bit data path. The output is VMI 1.4 compatible. A 2-wire serial MPU interface is used to simplify system integration. All the functions can be controlled through this interface. The analog front-end converts analog video signals to the required digital format. It contains an analog multiplexer, Clamping and AGC circuits, two analog-to-digital converters (ADC), and related control logic. Video Source Selection The analog multiplexer selects one of the four inputs MUX, MUX1, MUX2, and MUX3. MUX-3 can be connected to four composite video inputs or three composite inputs and the Y signal of an S-Video input. All the signals should be AC-coupled to MUX-3. When decoding a S-Video input, the Y signal should connect to one of the MUXs and the C signal to Cin. The C signal should also be AC-coupled to Cin. It is possible that the input video signals are momentarily connected together through the equivalent of 2 Ω during multiplexer switching. Therefore, the multiplexer cannot be used on a real-time pixel-by-pixel basis. TECHWELL 3

Clamping and Automatic Gain Control The composite signal or the Y signal of the S-video is connected to the Clamping circuit that restores its DC level. The Analog Control logic generates control signal to the Clamping circuit so that the back porch of the digitized video signal will be always at a desired level. The Automatic Gain Control (AGC) adjusts input gain so that the sync tip is at a desired level. Peak protection logic is used to prevent saturation for abnormal signals. Analog to Digital Converter Video Format TW98 contains two 1-bit pipelined ADCs that consume less power than conventional flash ADC. The output of the Clamp and AGC connects to one ADC that digitizes the composite input or the Y signal of the S-Video input. The second ADC digitizes the C signal when decoding S-video signal. TW98 supports several composite video input formats as shown in Table 1. The video decoder needs to be programmed appropriately for each of the composite video input formats. Table 1. Video Input Formats Supported by the Tw98 Sync Processing NTSC-M 525 6 3.58 MHz U.S., many others NTSC-Japan (1) 525 6 3.58 MHz Japan PAL-B 625 5 4.43 MHz Many PAL-D 625 5 4.43 MHz China PAL-G 625 5 4.43 MHz Many PAL-H 625 5 4.43 MHz Belgium PAL-I 625 5 4.43 MHz Great Britain, others Notes: (1). NTSC-Japan has IRE setup. The sync processor of TW98 detects horizontal synchronization and vertical synchronization signals in the composite video or in the Y signal of an S-video. The processor contains a phase-locked-loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals such as those from VCR fast forward or backward. Horizontal sync processing The horizontal synchronization processing contains a horizontal sync detector, a phaselocked-loop (PLL), and the related decision logic. The horizontal sync detector detects the presence of a horizontal sync tip by counting lowpass filtered input sample whose level is lower than a threshold (specified in register TECHWELL 4

SYNCL). If the count reaches a programmable value (specified in register HSCOUNT), a horizontal sync is detected. Additional logic is also used to avoid false detection. The PLL has two working modes, fast mode and slow mode. The fast mode is for tracking unstable signals such as those from VCR fast forward or backward. In this mode, the PLL can track on the detected sync signal within a few lines. Together with other logic, it produces effective synchronization in diverse situations. The slow mode is for obtaining precise location of horizontal sync when TW98 is decoding stable signals such as those from broadcast TV station or a DVD player. The dynamic characteristics of the PLL can be modified by register settings. TW98 automatically switches between these two modes according to the long-term average of the PLL phase error. If it exceeds a defined threshold, the PLL switches to the fast mode. Otherwise, it goes to the slow mode. In case the horizontal sync is missing, a free-wheel mechanism keeps generating horizontal sync signal until horizontal sync is detected again. Only after missing 96 consecutive sync signal does TW98 reinitializes its sync processor and begin a new hunt for synchronization signal. Vertical sync processing Color Decoding The vertical sync processing detects vertical synchronization in the input video signals. When the location of the vertical sync is close to a horizontal sync, it indicates a frame start or the odd field. Otherwise, it indicates an even field. The odd/even field bit toggles every field automatically. Only when inconsistency is detected for more than a specified number be the odd/even field bit adjusted. The TW98 separates luma (Y) and chroma (C) using a proprietary 2H adaptive comb filter. The filter uses a two-line buffer. An adaptive logic combines the upper-comb and the lower-comb results based on the signal changes among the previous, current and next lines. This technique leads to satisfactory Y/C separation with small cross luma and cross color at both horizontal and vertical edges. The demodulator also uses an adaptive technique. After mixing the subcarrier signal, the color difference signal goes through an adaptive low-pass filter whose characteristics vary according to the color changes in horizontal direction. This technique leads to both small color noise and sharp color edges. The Y/C separation and demodulation process applies to both NTSC and PAL signals. During S-video operation, the Y signal bypasses the comb filter. The C signal connects directly to the adaptive demodulation. TECHWELL 5

Component Processing Brightness, Contrast, and Black Luma Processing The TW98 adjusts brightness by adding a programmable value (in register BRIGHTNESS) to the Y signal. It adjusts the picture contrast by changing the gain (in register CONTRAST) of the Y signal. The TW98 video decoder also performs a coring function, in which it forces all values below a programmed level (in register CORING) to zero. This is useful because the human eyes are more sensitive to variations in black images. By taking near black images and turning them into black, the image appears clearer. The luma signal goes through a luma processor that contains a FIR filter, a non-linear edge synthesizer, and a noise suppression circuit. The FIR filter is 2-dimensional with 9 horizontal taps and 3 vertical taps. Its frequency response can be programmed to increase or decrease the luma sharpness in both horizontal and vertical directions. This filter can increase the perceived sharpness of the output picture when programmed as a high-pass filter. One problem of using linear high-pass filter for sharpness is the overshooting effect at strong edges. When a proper amount of overshoot is produced, the picture looks sharp. However, the picture quality suffers when large overshoot appears. To resolve this problem, TW98 employs a non-linear edge synthesizer that is capable of synthesizing sharp edges without overshooting. Combined with the FIR filter, it can substantially increase picture sharpness. The FIR filter and the non-linear edge synthesizer can all be programmed through control registers. A high frequency coring logic is incorporated in the luma processing to suppress background noise. The coring level can be adjusted through a control register. The Hue and Saturation When decoding NTSC signals, TW98 can adjust the hue of the chroma signal. The hue is defined as a phase shift of the subcarrier with respect to the burst. This phase shift can be programmed through a control register. The color saturation can be adjusted through changing the gain of Cb and Cr signals for both NTSC and PAL formats. The Cb and Cr gain can be adjusted independently for flexibility. Automatic Chroma Gain Control The Automatic Chroma Gain Control (ACC) compensates for reduced amplitudes caused by high-frequency loss in video signal. The color-burst amplitude is calculated and TECHWELL 6

compared to nominal. The chroma (C) signals are then increased or decreased in amplitude accordingly. The range of chroma gain is.8 2 times the original amplitude. This function can be enabled or disabled through control register CKILL. Low Color Detection and Removal If color-burst amplitude is smaller than a threshold, specified in register CKILL, for two frames, TW98 can turn off the color by setting the gains of Cb and Cr to zero. This function can be enabled or disabled through control register CKILL. Color edge sharpening A nonlinear color edge synthesizing circuitry is used to produce sharp color edges. The effect can be controlled through registers. Back-End Processing Noise Suppression Scaling Skew Compensation The back-end of TW98 consists of an IIR filter, a noise level detector, an image-scaling engine, and related logic. They can be programmed to achieve noise suppression, filtered scaling and temporal decimation, and skew compensation. After Luma and Chroma processing, both luma (Y) and color signal (U, V) go through a two dimensional IIR low-pass filter. This filter is an adaptive filter with two sets of coefficients. One set has stronger low-pass filtering ability to preserve edges. An adaptive logic detects edges and automatically chooses the proper set of coefficients. In addition, TW98 contains a noise detection logic that can compute video signal noise level. This value is available from register NOISE. By reading this register, the controller, such as software driver, can automatically determine the noise level in the current signal and program the IIR filter accordingly. In this way, noise suppression that automatically adapts to noise level can be implemented. The TW98 can independently reduce the output video image size in both horizontal and vertical directions using arbitrary scaling ratios. The horizontal scaling employs a 4-tap polyphase decimation filter while the vertical scaling is implemented with linear interpolation. In order to reduce aliasing, the luma processing should be programmed to achieve proper low-pass filtering effect according to the down scaling ratio. The sync processor of TW98 can provide horizontal sync signal in sub-pixel accuracy. A skew between the sync signal and pixel clock can be computed for each horizontal line. The skew value is then passed to the scaling engine as a phase shift, which will be used to offset the first pixel when the scaling engine resamples the output horizontally using linear interpolation. TECHWELL 7

Closed Caption Decoding TW98 has a built-in Closed Caption (CC) and Extended Data Services (EDS) decoder that adhering to the EIA-68 standard. This decoder can be enabled or disabled independently on line 21 and line 284 for NTSC. The decoded data is made available through CC_DATA and CC_STATUS registers that can be accessed through the 2-WIRE SERIAL MPU interface. VBI Data Pass-through The TW98 provides Vertical Blanking Interval (VBI) data pass-through capability. TW98 captures the ADC raw data of the VBI region and makes it available to the system for later software processing. The TW98 may operate in a VBI Line Output mode, in which the VBI data is only made available during selected lines. This mode of operation is intended to enable capture of VBI lines containing ancillary data as well as processing of normal YCrCb video image data. In addition, the TW98 supports a VBI Frame Output mode, in which every line in the video signal is treated as if it was a vertical interval line and no image data is output. This mode of operation is designed for use in still-frame capture/processing applications. Power Management Control Interface The TW98 can be put into power-down mode in which its clock is turned off for most of the circuits. The Y and C path can be separately powered down. The TW98 registers are accessed via 2-WIRE SERIAL MPU interface. It operates as a slave device. Serial clock and data lines, SCL and SDA, transfer data from the bus master at a rate of 4 Kbits/s. Chip select and reset signals are also available to select one of two possible TW98 devices in the same system and to set the registers to their default values. TECHWELL 8

Output Interface The TW98 supports a synchronous 8-bit or 16-bit YCrCb 4:2:2 data output stream. The interface consists of VD [15:], HSYNC, VSYNC, HACTIVE, VACTIVE, DVALID, LVALID, VCLK, FIELD, CBFLAG, and OE# as shown in Fig 2. TW98 HSYNC VSYNC HACTIVE VACTIVE DVALID LVALID VCLK FIELD CBFLAG CLKx1, CLKx2 OE# VD [15:] Figure 2. TW98 pixel output interface The TW98 outputs all pixel data and control signals synchronous with CLKx1 for the 16-bit format or CLKx2 for the 8-bit format. There are two basic output modes supported allowing interface to various GUI accelerators. Mode selections are controlled by the state of the OPFORM register (x3). Mode 1 format is YCrCb 4:2:2 with separate syncs and flags. Mode 2 format is YCrCb 4:2:2 that complies with the ITU-R-656 standard. Mode 1 allows both 8 and 16 bits format. Mode 2 can only be 8-bit format. The mapping of various formats is shown in Table 2. When the output is configured for an 8-bit format, the data is output on pins VD [15:8] with 8 bits of chrominance data preceding 8 bits of luminance data for each pixel output. The data output is synchronous to the rising edge of CLKx2. When the output is configured for a 16-bit format, the luminance data is output on VD [15:8], and the chrominance data is output on VD [7:]. In 16-bit mode, the data output is synchronous with the rising edge of CLKx1. Mode 1 output The default output format of TW98 is a synchronous 8-bit YCrCb 4:2:2 data format with separate syncs and flags. Video data is compliant with CCIR61 format. TECHWELL 9

HSYNC, VSYNC and FIELD The HSYNC and VSYNC output timing is VMI v1.4 compliant. The leading edge of HSYNC depends on the input video signal. The pulse width of HSYNC is programmable from -255 CLKx1 cycles. The leading edge of VSYNC also depends on the video input. It typically occurs on the low period of first serration pulse of the video signal. The trailing edge of VSYNC follows the HSYNC in order to be VMI compliant. For the start of the odd field, it occurs 64 CLKx2 cycles after the trailing edge of HSYNC that follows the last equalization pulse of the input. For the indication of the even field, the trailing edge of VSYNC occurs 64 CLKx2 cycles after the leading edge of HSYNC that follows the last equalization pulse of the input. In this latter case, the HSYNC width has to be set at least 64 CLKx1 cycles. The FIELD output indicates the input video source field state as determined by the decoder. It changes state at the leading edge of VSYNC to reflect the state of following field. If the field cannot be determined due to video source noise, it will toggle its state for each field until it can be corrected by the source. The video timing of these outputs is illustrated in Figure 3a and 3b. HACTIVE and VACTIVE The HACTIVE is asserted at the start of the active video synchronous to the CLKx1 or CLKx2 depending on the format. When the horizontal count of CLKx1 cycles matches the setting of HDELAY register, HACTIVE is asserted. It will be asserted for a period matches the setting of HACTIVE register before it is de-asserted. During the blanking period, HACTIVE is de-asserted for the whole scan line. VACTIVE is used to indicate the start of active video line. When the line count in each field matches the VDELAY register setting, VACTIVE is asserted. It will remain asserted for the number of scan-lines that matches the set in the VACTIVE register before it is de-asserted. 1 INPUT HSYNC VSYNC FIELD ODD INPUT 264 HSYNC VSYNC FIELD EVEN Figure 3a. HSYNC, VSYNC and FIELD timing for NTSC field transition TECHWELL 1

1 INPUT HSYNC VSYNC FIELD ODD INPUT 314 HSYNC VSYNC FIELD EVEN Figure 3b. HSYNC, VSYNC and FIELD timing for PAL (B, D, G, H, I) field transition DVALID and LVALID In a rectangular pixel format, the active video resolutions are either 72 x 48 for the 525/6 video systems or 72 x 576 for the 625/5 systems. In a square pixel operation, the active video resolutions are either 64 x 48 for the 525/6 video systems or 768 x 576 for the 625/5 systems. The DVALID is used to indicate the valid active pixels data output during a scan line. The LVALID is used to indicate the valid active scan lines during a field. The DVALID can be configured to output in three different formats. This is determined by the OPFORM (x3) register. In the first format, the DVALID output is asserted for valid pixel during the active pixel time on active scan line. The VCLK is gated in this case for proper pixel data strobing. For 8-bit output mode, VCLK is the gated CLKx2 to indicate valid pixel data. For 16-bit output mode, VCLK is the gated CLKx1. The DVALID is always de-asserted during blanking period. In the second format, the DVALID output is toggled during the active pixel time on active scan line to indicate valid pixel data. In this case, the VCLK is continuously running based on CLKx1 or CLKx2 in 16-bit or 8-bit output mode, respectively. In the third format, the DVALID has the same timing as the VCLK in the first format. The result is a gated CLKx1 or CLKx2 signal during the active video time on active scan lines. This is illustrated in Figure 4a, 4b and 4c for the 8-bit mode. The timing is similar for 16-bit output mode with all signals referencing to CLKx1. TECHWELL 11

CLKx2 VCLK VD [15:8] Cb Y Cr Y1 Cb2 Y2 Cr2 Y3 DVALID FIGURE 4a. Output timing for 8-bit YCrCb mode in the first format CLKx2 VCLK VD [15:8] Cb Y Cr Y1 Cb2 Y2 Cr2 Y3 DVALID FIGURE 4b. Output timing for 8-bit YCrCb mode in the second format CLKx2 VCLK VD [15:8] Cb Y Cr Y1 Cb2 Y2 Cr2 Y3 DVALID FIGURE 4c. Output timing for 8-bit YCrCb mode in the third format TECHWELL 12

Pin Name VD15 VD14 VD13 VD12 VD11 VD1 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD CK1 2N Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb 2N+1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr 4N Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb 4N+1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y CK2 4N+2 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr 4N+3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y Mode 2 SAV and EAV sequence, YCrCb data, Ancillary data and blanking data Mode 2 Output Table 2. Output data mapping between various formats. At this mode, the TW98 outputs ITU-R-656 compatible data sequence. This is an 8-bit output mode, and all outputs follow every rising edge of CLKx2. HSYNC, VSYNC, HACTIVE, VACTIVE, DVALID, LVALID and FIELD are still valid at this mode. The SAV and EAV sequences are inserted into the data stream to indicate the active video time. Their timing can be programmed through related registers. At this mode, the CLKx2 frequency should be exactly two times the output rate. Otherwise, invalid data may appear on the output data stream. During the blanking time, the YCrCb outputs have a value of x1 for Y and x8 for Cr and Cb, unless ancillary data is present. It is noted that the number of active pixel samples per line is constant in this mode regardless of the actual incoming line length. The blanking time will be automatically adjusted to match the varying line length. The output timing is illustrated in Fig 5. The SAV and EAV sequences are shown in Table 3. TECHWELL 13

CLKx2 VCLK VD [15:8] HACTIVE EAV CODE SAV CODE FFh h h XY 8h 1h 8h 1h FFh h h XY Cb Y Cr Y1 Cb Y2 DVALID FIGURE 5. Output timing for 8-bit ITU-R-656 mode VD15 VD14 VD13 VD12 VD11 VD1 VD9 VD8 First word 1 1 1 1 1 1 1 1 Second word Third word Forth word 1 F V H P3 P2 P1 P Video Scaling Down-scaling H: - SAV, 1 - EAV V: 1 - blanking, - elsewhere F: - field 1, 1 - field 2 P3: V XOR H; P2: F XOR H; P1: F XOR V; P: F XOR V XOR H Table 3. ITU-R-656 SAV and EAV code sequence The TW98 provides three methods to reduce the amount of output video pixel data. They are downscaling, cropping, and temporal decimation. The downscaling provides full video image at lower resolution. The cropping provides only portion of the video image output. The temporal decimation provides full video image at reduced frame rate. All these mechanisms can be controlled independently to yield maximum flexibility in the output stream. This is achieved by programming the horizontal scaling ratio register (HSCALE) and vertical scaling register (VSCALE). When outputting unscaled NTSC video, the TW98 will output 768 pixels per line. This corresponds to the pixel rate of 4*Fsc. When doing TECHWELL 14

CCIR61 compatible output, only 72 samples per line are required. The 16-bit HSCALE register, which is the concatenation of two 8-bit registers HSCALE_HI and HSCALE_LO, is used to reduce the output pixels to the desired number. Following is an example using pixel ratio to determine the horizontal scaling ratio. These equations should be used to determine the scaling ratio to be written into the 16-bit HSCALE register: NTSC: HSCALE = [766/N pixel_desired ] * 256 PAL: HSCALE = [(946/N pixel_desired )] * 256 Where: N pixel_desired is the nominal number of pixel per line. For example, to output a CCIR61 compatible NTSC stream, the HSCALE value can be found as: HSCALE = [(766/72)] * 256 = 272 = x11 The vertical scaling determines the number of vertical lines output by the TW98. The vertical scaling register (VSCALE) is a 13-bit register, which is the concatenation of a 5-bit register VSCALE_HI and an 8-bit register VSCALE_LO. The maximum scaling ratio is 32:1. Following equations should be used to determine the scaling ratio to be written into the 13-bit VSCALE register. 6Hz system: VSCALE = [48/ N line_desired] * 256 5Hz system: VSCALE = [576/ N line_desired] * 256 Where: N line_desired is the number of active lines output per frame. The scaling ratios for some popular formats are listed in Table 4. Cropping Cropping allows only subsection of a video image to be output. The VACTIVE signal can be programmed to indicate the start and stop position on the video frame, and the HACTIVE signal can be programmed to indicate the start and stop position on the video line. The start of the field or frame in the vertical direction is indicated by the leading edge of VSYNC. The start of the line in the horizontal direction is indicated by the leading edge of the HSYNC. The sizes of the active video are determined by HDELAY, HACTIVE, VDELAY, and VACTIVE registers. These registers are 1-bit wide, with their lower 8-bit respectively in HDELAY_LO, HACTIVE_LO, VDELAY_LO, and VACTIVE_LO. Their upper 2-bit shares the same register CROP_HI. The Horizontal delay register (HDELAY) determines the number of pixels delay between the leading edge of HSYNC and the leading edge of the HACTIVE. Note that this value is referenced to the unscaled pixel number. The Horizontal active register (HACTIVE) TECHWELL 15

determines the number of active pixels to be output after the delay from the sync edge is met. This value is referenced to the scaled pixel number. Therefore, if the scaling ratio is changed, the number of active pixels output remain unchanged as set by the HACTIVE register. In order for the cropping to work properly, the following equation should be satisfied. HDELAY/scaling_ratio + HACTIVE < Total number of scaled pixels. For NTSC output at 4*Fsc rate (unscaled), the total number of pixels is 91. The HDELAY should be set to 135 and HACTIVE set to 754. For PAL output at 4*Fsc rate (unscaled), the total number of pixels is 1135. The HDELAY should be set to 186 and HACTIVE set to 922. The Vertical delay register (VDELAY) determines the number of lines delay between the leading edge of the VSYNC and the start of the active video lines. It indicates number of lines to skip at the start of a frame before asserting the VACTIVE signal. This value is referenced to the incoming scan lines before the vertical scaling. The number of scan lines is 525 for the 6Hz systems and 625 for the 5Hz systems. The Vertical active register (VACTIVE) determines the number of lines to be used in the vertical scaling. Therefore, the number of scan lines output is equal or less than the value set in this register depending on the vertical scaling ratio. Temporal Decimation Temporal decimation provides a mechanism for frame rate reduction in a consistent manner instead of depending on external bandwidth availability. The temporal decimation can be done on either field or frame basis. The allowed decimation values are 1 to 6 for NTSC or 1 to 5 for PAL since this value indicates the number of fields or frames to be skipped during the output sequence. Skipped frames are considered inactive. The HACTIVE pin will be driven low during these inactive frames to indicate it. Scaling Ratio Format Total Resolution Output Resolution HSCALE values VSCALE (frame) 1:1 NTSC SQ NTSC CCIR61 PAL SQ PAL CCIR61 2:1 (CIF) NTSC SQ NTSC CCIR61 PAL SQ PAL CCIR61 4:1 (QCIF) NTSC SQ NTSC CCIR61 PAL SQ PAL CCIR61 78x525 858x525 944x625 864x625 39x262 429x262 472x312 432x312 195x131 214x131 236x156 216x156 64x48 72x48 768x576 72x576 32x24 36x24 384x288 36x288 16x12 18x12 192x144 18x144 x12a x11 x133 x15 x255 x21f x267 x2a x4aa x44 x4cf x541 x1 x1 x1 x1 x2 x2 x2 x2 x4 x4 x4 x4 Table 4. HSCALE and VSCALE value for some popular video formats. TECHWELL 16

VBI DATA PROCESSING Overview A frame of video is composed of 525 lines for NSTC and 625 for PAL. The time required for the electron beam to move from the bottom to the top of the screen is the vertical blanking period, and it requires the equivalent of 21 horizontal active video scan lines. This portion is normally not seen. The video image data is contained in the ODD and EVEN fields within lines 21 to 262 and lines 284 to 525, respectively. During vertical blanking period, line 1 through 9 and 263.5 through 272 are used for equalizing and synchronization. Lines 1 through 21 and 273 through 284 (1 through 21 of the even field) can be used for sending embedded information or ancillary data, and is normally regarded as the Vertical Blanking Interval or VBI portion of the video signal. In the default configuration of the TW98, the VBI region of the video signal is treated the same way as the real image signal. It will decode this region of signal as if it was video by Y/C separation and horizontal scaling. The TW98 can also be configured in a mode known as VBI raw data mode. In this mode, the raw VBI region ancillary data can be captured for later processing by software. It is done as follow. First, the analog composite video signal is digitized. Then, it is converted to 8-bit data stream at half of the connected crystal rate. In this case, it is 27.5MHz for a 55MHz crystal connected. Finally, the data is output to the VD [15:8] data pins. It can also be output as a 16-bit data stream on pins VD [15:] at half of the crystal rate. There are three modes of operation for the VBI raw data output feature. 1) VBI raw data output disabled. This is the default mode of operation. In this mode, the decoder decodes composite video signals and output YCrCb stream. 2) VBI line output mode. The device outputs connected crystal rate VBI data stream only during vertical interval between the trailing edge of VSYNC and the leading edge of VACTIVE. If a trailing edge of VSYNC occurs after the horizontal active period has already started as in the case of odd field, the VBI active period starts on the following line. When VACTIVE is high, the TW98 is outputting normal standard YCrCb data. Therefore, this mode can be used to allow capturing of both ancillary data and normal YCrCb video data simultaneously. 3) VBI frame output mode. In this mode, the device takes every scan line of the signal as a vertical interval line and outputs only the crystal rate raw data on every line. Therefore, no video image data is outputted. This can be used as raw data capturing and saved for later processing. When the device is set to VBI line output mode, the VBI data is output during HACTIVE signal period. The DVALID or gated VCLK are used during VBI as in the normal video data output mode to indicate valid VBI data. A video/graphic controller should be able to do the following to capture VBI data output. It should keep track of the line count in order to select specific lines for VBI data processing. It must be able to use DVALID or VCLK for ancillary data qualification, and load only the valid data. TECHWELL 17

VBI Frame Output Mode In VBI frame output mode the TW98 is generating VBI data all the time (i.e., there is no VBI active interval). In essence, the TW98 is acting as an ADC continuously sampling the entire video signal at half of crystal rate. The TW98 generates HSYNC, VSYNC and FIELD timing signals in addition to the VBI data, but the DVALID, HACTIVE, and VACTIVE signals are all held high during VBI frame output operation. The behavior of the HSYNC, VSYNC, and FIELD timing signals is the same as normal YCrCb 4:2:2 output operation. The HSYNC, VSYNC, and FIELD timing signals can be used by the video processor to detect the beginning of a video frame or field, at which point it can start to capture a full frame/field of VBI data. Closed Captioning and Extended Data Services A Closed Caption (CC) scan line (line 21 on odd field) or an Extended Data Services (EDS) scan line (line 21 on even field) on an NTSC-based system is made of 25 bit periods at a.53mhz rate. The data is an analog signal beginning with a packet header. It contains a Clock Synchronization Code consisting of 14 bits of double-frequency run-in clock at 1.6 MHz, a 2-bit framing code. The data of 16 bits/2 bytes follows the packet header. Each of these 2 bytes is a 7 bit + odd parity ASCII character which represents text or control characters for positioning or display control. For the purposes of CC or EDS, only the Y component of the video signal is used. Therefore, the input composite video has to go through the Y/C separation to extract Y component for further decoding. The TW98 can be programmed to decode CC or EDS data by setting register x1b. Since the CC and EDS are independent, there could be one or both in a particular frame. A typical waveform is shown in Figure 6. In the CC/EDS decode mode, the decoder monitors the appropriate scan lines looking for the clock run-in and start bits pattern. It found, it locks to the clock run-in, the caption data is sampled and loaded into shift registers, and the data is then transferred to the caption data FIFO. The TW98 provides a 16 x 1 location FIFO for storing CC/EDS data. Once the video decoder detects the start signal in the CC/EDS signal, it captures the low byte of CC/EDS data first and checks to see if the FIFO is full. If the FIFO is not full, then the data is stored in the FIFO, and is available to the user through the CC_DATA register (x1a). Clock run-in Frame Code 2-byte character data Figure 6. Typical CC/EDS scan line waveform TECHWELL 18

The high byte of CC/EDS data is captured next and placed in the FIFO. Upon being placed in the 1-bit FIFO, two additional bits are attached to the CC/EDS data byte by TW98 s CC/EDS decoder. These two bits indicate whether the given byte stored in the FIFO corresponds to CC or EDS data and whether it is the high or low byte of CC/EDS. These two bits are available to the user through the CC_STATUS register bits CC_EDS and LO_HI, respectively. As stored in the FIFO, LO_HI is bit 8 and CC_EDS is bit 9. Additionally, the TW98 stores the results of the parity check in the PARITY_ERR bit in the CC_STATUS register. The 16-location FIFO can hold eight lines worth of CC/EDS data, at two bytes per line. Initially when the FIFO is empty, bit Empty in the CC_STATUS register (x1a) is set low and indicates that no data is available in the FIFO. Subsequently, when data has been stored in the FIFO, the Empty bit is set to logical high. Once the FIFO is half full, the CC_VALID interrupts pin signals to the system that the FIFO contents should be read in the near future. The CCVALID pin is enabled via a bit in the CC_STATUS register (x1a). The system controller can then poll the CCVALID bit in the STATUS register (x) to ensure that it was the TW98 that initiated the CCVALID interrupt. This bit can also be used in applications where the user disables the CCVALID pin. When the first byte of CC/EDS data is decoded and stored in the FIFO, the data is immediately placed in the CC_DATA and CC_STATUS registers and is available to be read. Once the data is read from the CC_DATA register, the information in the next location of the FIFO is placed in the CC_DATA and CC_STATUS registers. If the controller in the system ignores TW98 s CCVALID interrupts pin for a sufficiently long period of time, then the CC/EDS FIFO will become full and the TW98 will not be able to write additional data to the FIFO. Any incoming bytes of data will be lost and an overflow condition will occur; bit Overflow in the CC_STATUS register will be set to a logical one. The system may clear the overflow condition by reading the CC/EDS data and creating space in the FIFO for new information. As a result, the overflow bit is reset to a logical zero. There will routinely be asynchronous reads and writes to the CC/EDS FIFO. The writes will be from the CC/EDS circuitry and the reads will occur as the system controller reads the CC/EDS data from TW98. These reads and writes will sometimes occur simultaneously, and the TW98 is designed to give priority to the read operations. In the case where the CC_DATA register data is specifically being read to clear an overflow condition, the simultaneous occurrence of a read and a write will not cause the overflow bit to be reset, even though the read has priority. An additional read must be made to the CC_DATA register in order to clear the overflow condition. As always, the write data will be lost while the FIFO is in overflow condition. The FIFO is reset when both CC and EDS bits are disabled in the CC_STATUS register; any data in the FIFO is lost. SCLK SDAT Device ID (1-7) R/W Index (1-8) Data (1-8) Start pulse Acknowledge Acknowledge Stop pulse Figure 7. MPU interface serial data flow TECHWELL 19

Serial MPU Interface The two wire serial MPU interface consists of SCLK and SDAT signals. SCLK is the serial clock and SDAT is the data line. Register data can be written to or read from the TW98 through this interface between bus master and slave device. The TW98 is operated as a slave device. For both read and write, each byte is transferred MSB first, and the data bit is valid when the SCLK is high. The relationship between SCLK and SDAT is decoded to determine the start and stop condition on the bus. To read from or write to the salve device, the host initiates a transfer cycle with a start pulse. The start pulse is a high to low transition on the SDAT line while the SCLK is held high. The host should only generate a start pulse at the beginning of the cycle, or after the transfer of a data byte to or from the salve device. The host then sends a byte consisting of the 7-bit slave device ID and a in the R/W bit. This is shown in Figure 7. SIAD is the configuration pin used to configure TW98 to use one of the two addresses. The TW98 ID address is listed in Table 5. After transmitting the address, the master must release the SDAT line during the low phase of SCLK, and wait for an acknowledgement from the slave. If the address matches the selected slave address, the slave should respond by driving the SDAT line low to acknowledge the condition. The master will sample the data line at the rising edge of the clock line, and continue with the cycle. If no device on the bus responds, the master transmits a stop pulse and ends the cycle. If a slave device responded, the second byte the host sends is the base register index, MSB first. Again, the selected slave device will acknowledge the transfer and load the data into its internal index register. To write to the slave device, the master can then send an 8- bit data, MSB first, to be loaded to the register pointed by the internal index register. Again, the slave should acknowledge the transfer and automatically increment the index in preparation for the next data transfer. Therefore, the host can do multiple writes to the slave if they are in sequential order. The host may issue a stop pulse, a start pulse or another 8-bit data to be loaded into the next register location. A stop pulse is a low to high transition while the clock line is held high. Each byte transfer consists of 9 clocks. When write to TW98, an acknowledge signal is created during the 9 th clock. A read cycle takes two start-stop phases. The first phase is a write to the internal index register. The second phase is the read from the data register. The host initiates the first phase by sending the start pulse. It then sends the slave device ID together with a in the R/W bit position for writing the index register. The index is then sent followed by the stop pulse. The second phase starts with the start pulse. It then sends the slave device ID with a 1 in the R/W bit position to indicate a read operation. The slave will transfer the content of the desired register. The host then uses the SCLK to shift data out from the slave device. 1 1 SIAD R/W Table 5. TW98 slave device ID and R/W byte TECHWELL 2

Test Modes The TMODE input pin selects the test mode. If this pin is de-asserted (low), the TW98 is in its normal operating mode. When this pin is asserted (high), the TW98 is in test mode, and the mode is controlled by TEST1 and TEST2 input pins as shown in Table 6. Test mode TEST2 TEST1 Description Reserved Pin tri-state 1 In this mode, all pin output drivers are tri-stated. Pin leakage current parameters can be measured. Outputs high 1 In this mode, all pin output drivers are forced to the high output state. Pin output high voltage, V OH and I OH, can be measured. Outputs low 1 1 In this mode, all pin output drivers are forced to the low output state. Pin output high voltage, V OL and I OL, can be measured. Table 6. Test mode selection and description TECHWELL 21

Control Registers TW98 Register SUMMARY Index (HEX) Control Register Reset value ID Ch 1 CSTATUS h 2 INFORM h 3 OPFORM 6h 4 HSLEN 4h 5 POLARITY h 6 ACNTL h 7 CROP_HI 12h 8 VDELAY_LO 18h 9 VACTIVE_LO Eh A HDELAY_LO h B HACTIVE_LO Dh C VSCALE_HI 1h D VSCALE_LO h E HSCALE_HI 1h F HSCALE_LO 1h 1 BRIGHTNESS B6h 11 CONTRAST 3h 12 SHARPNESS 14h 13 SAT_U 71h 14 SAT_V 5h 15 HUE 2h 16 CKILL Dh 17 CORING h 18 Reserved h 19 VBICNTL h 1A CC_STATUS 4h 1B CC_DATA X 1C AGCGAIN h 1D GPIO h 1E TEST h 1F NOISE X 2 - BF Reserved C - FF Supplement TECHWELL 22

x Product ID Code Register (ID) 7-3 ID R The TW98 Product ID code is 11. 18h 2- Revision R The revision number. x1 Chip Status Register (CSTATUS) 7 Video Detect R = Video not present. (Sync is not detected in 31 consecutive line periods) 1 = Video detected. 6 H-lock R = Horizontal sync PLL is locked to the incoming video source. 1 = Horizontal sync PLL is not locked. 5 S-lock R = Sub-carrier PLL is locked to the incoming video source. 1 = Sub-carrier PLL is not locked. 4 Field R = Odd field is being decoded. 1 = Even field is being decoded. 3 Reserved 2 CCVALID R This bit indicates that valid closed caption or extended data service data pairs have been stored in the CC_DATA register and the FIFO is half full. 1 Reserved Reserved 1 1 TECHWELL 23

x2 Input Format (INFORM) 7 Reserved 6 SEL27 R/W 1 = Input crystal clock is either 54MHz or 27MHz. = Input crystal clock is 55MHz. 5 CLK27 R/W 1 = Input crystal clock is passed through. = Input crystal clock is divided by 2. 4 SVIDEO R/W 1 = S-video decoding = Composite video decoding 3-2 INSEL R/W These two bits control the input video selection. It selects between all composites source, or three composites and one S-video source. = Route MUX input to MXOUT 1 = Route MUX1 input to MXOUT 1 = Route MUX2 input to MXOUT 11 = Route MUX3 input to MXOUT 1- FORMAT R/W These two bits determine the video formats that the decoder is set to decode. Formats supported are as follow. = NTSC (M) 1 = PAL (B, D, G, H, I, N) 1 = Reserved 11 = Reserved The setting of these bits is allowed only when register x18 bit is set to. I.E. the manual mode. These bits are read only when the register x18 bit 1 is set to 1, i.e. auto-detection mode. A reading of 11 in the auto-detection mode indicates format detection in progress. After detection is done, these bits indicate the format setting. x3 Output Format Control Register (OPFORM) 7 Mode R/W = CCIR61 compatible YCrCb 4:2:2 format with separate syncs and flags. 1 = ITU-R-656 compatible data sequence format. 6 Length R/W = 8-bit YCrCb 4:2:2 output format based on CLKx2. 1 = 16-bit YCrCb 4:2:2 output format based on CLKx1. 5-4 DVALID format R/W = DVALID is in the first format with VCLK used as data strobe. 1 = DVALID is in the second format with DVALID indicating the valid data period. 1 = DVALID is in the third format with DVALID used as data strobe. 3 YUV R/W This bit is for output format selection between YUV and YCrCb. 1 = YUV, = YCrCb 2 OEN R/W = Enable outputs. 1 = Tri-state outputs defined by Tri-state select bits of this register. 1- Tri-state select R/W These bits select the outputs to be tri-stated when either the OE# pin is asserted high or the OEN bit is asserted high. There are three major groups that can be independently tri-stated: timing group (HSYNC, VSYNC, HACTIVE, VACTIVE, CBFLAG, DVALID, LVALID, FIELD), data group (VD [15:]), and clock group (CLKx1, CLKx2, VCLK). = Timing and data group only. 1 = Data group only. 1 = All three groups. 11 = Clock and data group only. 1 1b TECHWELL 24

x4 Horizontal Sync Length Register (HSLEN) 7- HSYNC Length R/W These bits control the active period length of the HSYNC pin output. It ranges from to 255 CLKx1 cycle. 4h x5 Output Polarity Register (POLARITY) 7 Lvalid R/W = LVALID pin is active high. 1 = LVALID pin is active low. 6 Dvalid R/W = DVALID pin is active high. 1 = DVALID pin is active low. 5 Vactive R/W = VACTIVE pin is active high. 1 = VACTIVE pin is active low. 4 Cbflag R/W = CBFLAG pin is active high. 1 = CBFLAG pin is active low. 3 Field R/W = FIELD pin is low for the odd field. 1 = FIELD pin is low for the even field. 2 Hactive R/W = HACTIVE pin active high. 1 = HACTIVE pin active low. 1 Hsync R/W = HSYNC pin active low. 1 = HSYNC pin active high. Vsync R/W = VSYNC pin active low. 1 = VSYNC pin active high. x6 Analog Control Register (ACNTL) 7 SRESET W A 1 written to this bit resets the device to its default state but all register content remain unchanged. This bit is self-resetting. 6 IREF R/W = Internal current reference 1. 1 = Internal current reference 2. 5 VREF R/W = Internal voltage reference. 1 = external voltage reference using VCOM, VREFP and VREFN. 4 AGC_EN R/W = AGC loop function enabled. 1 = AGC loop function disabled. Gain is set to 1. 3 CLK_PDN R/W = Normal clock operation. 1 = System clock in power down mode, but the MPU INTERFACE module and output clocks (CLKx1 and CLKx2) are still active. 2 Y_PDN R/W = Luma ADC in normal operation. 1 = Luma ADC in power down mode. 1 C_PDN R/W = Chroma ADC in normal operation. 1 = Chroma ADC in power down mode. EXAGCC R/W = Internal AGC capacitor is used. 1 = External AGC capacitor connected to CAGC is included. TECHWELL 25

x7 Cropping Register, High (CROP_HI) 7-6 Vertical Delay MSB 5-4 VACTIVE MSB 3-2 Horizontal Delay MSB 1- HACTIVE MSB R/W These bits are bit 9 to 8 of the 1-bit Vertical Delay register. R/W These bits are bit 9 to 8 of the 1-bit VACTIVE register. 1b R/W These bits are bit 9 to 8 of the 1-bit Horizontal Delay register. R/W These bits are bit 9 to 8 of the 1-bit HACTIVE register. 1b x8 Vertical Delay Register, Low (VDELAY_LO) 7- Vertical Delay LSB R/W These bits are bit 7 to of the 1-bit Vertical Delay register. The two MSBs are in the CROP_HI register. It defines the number of half lines between the trailing edge of VSYNC and the start of the active video. 18h x9 Vertical Active Register, Low (VACTIVE_LO) 7- Vertical Active LSB R/W These bits are bit 7 to of the 1-bit Vertical Active register. The two MSBs are in the CROP_HI register. It defines the number of active video lines per frame output. Eh xa Horizontal Delay Register, Low (HDELAY_LO) 7- Horizontal Delay LSB R/W These bits are bit 7 to of the 1-bit Horizontal Delay register. The two MSBs are in the CROP_HI register. It defines the number of scaled pixels between the start of the active video and the start of the image cropping. h xb Horizontal Active Register, Low (HACTIVE_LO) 7- Horizontal Active LSB R/W These bits are bit 7 to of the 1-bit Horizontal Active register. The two MSBs are in the CROP_HI register. It defines the number of active pixels per line output. Dh xc Vertical Scaling Register, High (VSCALE_HI) 7-5 Reserved 4- Vertical Scale MSB R/W These bits are bit 12 to 8 of the 13-bit vertical scaling ratio register. 1h xd Vertical Scaling Register, Low (VSCALE_LO) 7- Vertical Scale LSB R/W These bits are bit 7 to of the 13-bit vertical scaling ratio register h TECHWELL 26

xe Horizontal Scaling Register, High (HSCALE_HI) 7- Horizontal Scale MSB R/W These bits are bit 15 to 8 of the 16-bit horizontal scaling ratio register. 1h xf Horizontal Scaling Register, Low (HSCALE_LO) 7- Horizontal Scale LSB R/W These bits are bit 7 to of the 16-bit horizontal scaling ratio register. 1h x1 BRIGHTNESS Control Register (BRIGHT) 7- Brightness R/W These bits control the brightness. They have value of 128 to 127. Larger value increases brightness. A value of `111_11` for NTSC or `11_` for PAL has no effect on the data. B6h x11 CONTRAST Control Register (CONTRAST) 7-6 Reserved 5- Contrast R/W These bits control the contrast. They have value of (`_`) to 1.96875 (`11_1111`). A value of 1 (`1_`) has no effect on the video data. 3h x12 -- SHARPNESS Control Register (SHARPNESS) 7-6 Reserved 5- Sharpness R/W These bits control the amount of gain control of high frequency luminance signals. They have value of (``) to 3.9375 (`111111`). A value of 1 (`1`) has no effect on the data. The default is 1.25 (`11`). 14h x13 Chroma (U) Gain Register (SAT_U) 7- U_gain R/W These bits control the gain adjustment to the U component of the video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can also be adjusted independently to provide greater flexibility. The range of adjustment is to 2%. 71h x14 Chroma (V) Gain Register (SAT_V) 7- V_gain R/W These bits control the gain adjustment to the V component of the video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can also be adjusted independently to provide greater flexibility. The range of adjustment is to 2%. 5h TECHWELL 27