DisplayPort and HDMI Protocol Analysis and Compliance Testing

Agenda DisplayPort DisplayPort Connection Sequence DisplayPort Link Layer Compliance Testing DisplayPort Main Link Protocol Analysis HDMI HDMI Protocol Analysis HDMI Protocol Compliance Testing

quantumdata 980 Test Platforms 980B Front View 980R Front View

DisplayPort Protocol Analysis and Compliance Testing

980B Advanced Test Platform Features / DisplayPort Modules 980B Test Platform Standard Features: 15 inch touch screen 1280 x 768 resolution. Operates through embedded touch display or remote GUI from host PC. Accommodates up to five (5) 980 series modules. Command line control via telnet. Software upgradable. Modules: HDMI 1.4 300MHz Protocol Analyzer module. HDMI 2.0 600MHz Video Generator module. HDMI 2.0 600MHz Protocol Analyzer module. DisplayPort 1.2 Video Generator / Analyzer module. DisplayPort 1.4 Video Generator / Analyzer module. 12G-SDI Video Generator / Analyzer module. Phy & Protocol Aux Channel Analyzer module.

980B DisplayPort Compliance Tests Supported 980B Test Platform DisplayPort Link Layer: DP 1.2 Core Sink Tests DP VESA Draft Tests, including reduced lane count fallback tests DisplayPort HDCP: HDCP 2.2 Source Tests HDCP 2.2 Sink Tests HDCP 2.2 Repeater Tests

DisplayPort Anatomy DisplayPort Source Main Link (Video/Audio/Control/Framing - Isochronous Streams 4 lanes) Lane 0 Lane 1 Lane 2 Lane 3 Aux Channel Link/Device Management Hot Plug Detect Interrupt Request DisplayPort Cable DisplayPort Sink (Monitor/TV) Main Link: Unidirectional, highbandwidth channel used to transport video, audio and metadata and protocol control elements. Main Link 1, 2 or 4 Lane Configurations. Main Link 4 link rates: 1.62Gbps (Reduced Bit Rate) 2.7Gbps (High Bit Rate) 5.4Gbps (High Bit Rate 2) 8.1Gbps (High Bit Rate 3) introduced in DisplayPort 1.3/4. No clock channel. Sink recovers clock using link transitions. Aux Channel: Bidirectional, half duplex channel with a data rate of 1Mbps. Link Training, DPCD Register status, HDCP authentication & EDID. Hot plug lead: Connection Detection. Interrupt mechanism in cases where there is a failure.

DisplayPort Connection Sequence

DisplayPort Connection Sequence DisplayPort Source DisplayPort Cable Event(s) Link Training Clock Recovery DisplayPort Sink (Monitor/TV) Hot Plug Read EDID Capabilities of Sink Device Read DPCD Link Capabilities of Sink Link Training Channel Equalization, Symbol Lock, Lane Alignment HDCP Authentication For content protection) Hot Plug. Indication to the Source that there is a Display device connect to it. EDID read. EDID is a data structure provided by a DisplayPort display that describe its capabilities to a DisplayPort video source. Link Training. Link training establishes the physical link parameters (number of lanes, link rate, voltage swing, pre-emphasis, equalization) used for transmission of video and audio over the main link. Link Training has two phases: Clock Recovery and Channel Equalization which includes Symbol Lock and Inter-Lane alignment. If the video/audio content is flagged for content protection, the High-bandwidth Digital Content Protection (HDCP) authentication protocol is used.

980 Auxiliary Channel Analyzer Panels DPCD Event Transaction Log Panel Link Training Direction (< >) Time Write Msg Read Msg Detail Panel Two panels: 1) Transaction Log Panel 2) Details panel. Details of the highlighted transaction in the Log panel appears in the Details panel. Time goes from top to bottom on the Transaction Log panel. Direction of transaction is provided (< >). Read and Write is indicated (R W). Message type indicated (e.g. DPLT for DisplayPort Link Training). Color coding also used to distinguish between transaction types.

Connection Sequence EDID Read DisplayPort Source Source Function Transaction DisplayPort Sink Hot Plug Send EDID over Aux Chan Sink Function Read Request for Sink DPCD Capabilities over Aux Chan Returns DPCD Capability Registers over Aux Chan Writes Link Configuration Parameters over Aux Chan Source selects Voltage Swing and Pre- Emphasis for TPS1 Transmit Training Pattern 1 symbols over Main Link Write current drive settings to Rx DPCD over Aux Chan > 100us If CR not Done, then adjust Voltage Swing and Pre-Emphasis Read Request on DPCD - CR Done over Aux Chan Returns CR Status from DPCD over Aux Chan Transmit Training Pattern 1 symbols over Main Link Repeat if CR if not done; Otherwise: Channel EQ. Checks if CR is achieved Checks if CR is achieved Source Reads EDID from Sink

Connection Sequence Read Sink DPCD Capabilities DisplayPort Source Source Function Transaction DisplayPort Sink Hot Plug Send EDID over Aux Chan Sink Function Read Request for Sink DPCD Capabilities over Aux Chan Returns DPCD Capability Registers over Aux Chan Writes Link Configuration Parameters over Aux Chan Source selects Voltage Swing and Pre- Emphasis for TPS1 Transmit Training Pattern 1 symbols over Main Link Write current drive settings to Rx DPCD over Aux Chan If CR not Done, then adjust Voltage Swing and Pre-Emphasis Read Request on DPCD - CR Done over Aux Chan > 100us Returns CR Status from DPCD over Aux Chan Transmit Training Pattern 1 symbols over Main Link Repeat if CR if not done; Otherwise: Channel EQ. Checks if CR is achieved Checks if CR is achieved Source Reads Sink DPCD Capability Registers

Connection Sequence Link Training Clock Recovery Sequence DisplayPort Source Source Function Transaction DisplayPort Sink Hot Plug Send EDID over Aux Chan Sink Function Read Request for Sink DPCD Capabilities over Aux Chan Returns DPCD Capability Registers over Aux Chan Writes Link Configuration Parameters over Aux Chan Source selects Voltage Swing and Pre- Emphasis for TPS1 Transmit Training Pattern 1 symbols over Main Link Write current drive settings to Rx DPCD over Aux Chan If CR not Done, then adjust Voltage Swing and Pre-Emphasis Read Request on DPCD - CR Done over Aux Chan > 100us Returns CR Status from DPCD over Aux Chan Transmit Training Pattern 1 symbols over Main Link Repeat if CR if not done; Otherwise: Channel EQ. Checks if CR is achieved Checks if CR is achieved Source Writing Link Rate (8.1Gbps) to Sink DPCD Registers to Begin Link Training

Connection Sequence Link Training Clock Recovery Sequence DisplayPort Source Source Function Transaction DisplayPort Sink Hot Plug Send EDID over Aux Chan Sink Function Read Request for Sink DPCD Capabilities over Aux Chan Returns DPCD Capability Registers over Aux Chan Writes Link Configuration Parameters over Aux Chan Source selects Voltage Swing and Pre- Emphasis for TPS1 Transmit Training Pattern 1 symbols over Main Link Write current drive settings to Rx DPCD over Aux Chan If CR not Done, then adjust Voltage Swing and Pre-Emphasis Read Request on DPCD - CR Done over Aux Chan > 100us Returns CR Status from DPCD over Aux Chan Transmit Training Pattern 1 symbols over Main Link Repeat if CR if not done; Otherwise: Channel EQ. Checks if CR is achieved Checks if CR is achieved Source Writing Voltage Swing and Pre-Emphasis Levels that will be used for Link Training to Sink DPCD Registers

Connection Sequence Link Training Channel EQ, Symbol Lock, Interlane Alignment DisplayPort Source Source Function Source selects Voltage Swing and Pre- Emphasis for TPS2/3/4 Transaction Transmit Training Pattern 2/3/4 symbols over Main Link DisplayPort Sink Sink Function Write current drive settings to Rx DPCD over Aux Chan If CE, SL, LA not Done, then adjust Voltage Swing and Pre- Emphasis Read Request on DPCD CE, SL, LA Done over Aux Chan Returns CE, SL, LA Status from DPCD over Aux Chan Transmit Training Pattern 2/3/4 symbols over Main Link Repeat if CE, SL, LA not done; Otherwise: Link Training done. Checks if CE, SL, LA are achieved Checks if CE, SL, LA are achieved Source Writing Training Pattern Set 4 to Sink DPCD Registers

Connection Sequence Link Training Channel EQ, Symbol Lock, Interlane Alignment DisplayPort Source Source Function Source selects Voltage Swing and Pre- Emphasis for TPS2/3/4 Transaction Transmit Training Pattern 2/3/4 symbols over Main Link DisplayPort Sink Sink Function Write current drive settings to Rx DPCD over Aux Chan If CE, SL, LA not Done, then adjust Voltage Swing and Pre- Emphasis Read Request on DPCD CE, SL, LA Done over Aux Chan Returns CE, SL, LA Status from DPCD over Aux Chan Transmit Training Pattern 2/3/4 symbols over Main Link Repeat if CE, SL, LA not done; Otherwise: Link Training done. Checks if CE, SL, LA are achieved Checks if CE, SL, LA are achieved Source Reads Status of Channel Equalization, Symbol Lock and Inter-Lane Alignment Link Training All Done!

Connection Sequence Link Training Symbol Lock Failure DisplayPort Source Source Function Source selects Voltage Swing and Pre- Emphasis for TPS2/3/4 Transaction Transmit Training Pattern 2/3/4 symbols over Main Link DisplayPort Sink Sink Function Write current drive settings to Rx DPCD over Aux Chan If CE, SL, LA not Done, then adjust Voltage Swing and Pre- Emphasis Read Request on DPCD CE, SL, LA Done over Aux Chan Returns CE, SL, LA Status from DPCD over Aux Chan Transmit Training Pattern 2/3/4 symbols over Main Link Repeat if CE, SL, LA not done; Otherwise: Link Training done. Checks if CE, SL, LA are achieved Checks if CE, SL, LA are achieved Clock Recovery and Channel Equalization completed, but Symbol Lock not completed.

Connection Sequence Link Training Symbol Lock Failure Reset Drive Voltages DisplayPort Source Source Function Transaction DisplayPort Sink Hot Plug Send EDID over Aux Chan Sink Function Read Request for Sink DPCD Capabilities over Aux Chan Returns DPCD Capability Registers over Aux Chan Writes Link Configuration Parameters over Aux Chan Source selects Voltage Swing and Pre- Emphasis for TPS1 Transmit Training Pattern 1 symbols over Main Link Write current drive settings to Rx DPCD over Aux Chan If CR not Done, then adjust Voltage Swing and Pre-Emphasis Read Request on DPCD - CR Done over Aux Chan > 100us Returns CR Status from DPCD over Aux Chan Transmit Training Pattern 1 symbols over Main Link Repeat if CR if not done; Otherwise: Channel EQ. Checks if CR is achieved Checks if CR is achieved Sink requests that the Source adjusts Voltage Swing level and pre-emphasis on all four lanes.

Auxiliary Channel Analyzer (ACA) Link Maintenance DisplayPort Source Main Link (Video/Audio/Control/Framing - Isochronous Streams) Lane 0 Lane 1 Lane 2 Lane 3 Aux Channel Link/Device Management Hot Plug Detect Interrupt Request DisplayPort Cable Interrupt Request DisplayPort Sink (Monitor/TV) If Link Training is successful, then Link Maintenance mode. Link Training does not guarantee that the link will behave without errors. In Link Maintenance mode, the Link Policy function may force a retrain if there is a failure on the link. Link retraining is necessary when there is a loss of Clock Lock, Symbol Lock or Inter-Lane Alignment. Failure results in an IRQ interrupt using the Hot Plug Detect lead. The interrupt is a low-going pulse. Source re-initiates Link Training.

Auxiliary Channel Analyzer (ACA) Link Maintenance IRQ Request DisplayPort Source Source Function Source selects Voltage Swing and Pre- Emphasis for TPS2/3/4 Transaction Transmit Training Pattern 2/3/4 symbols over Main Link DisplayPort Sink Sink Function Write current drive settings to Rx DPCD over Aux Chan If CE, SL, LA not Done, then adjust Voltage Swing and Pre- Emphasis Read Request on DPCD CE, SL, LA Done over Aux Chan Returns CE, SL, LA Status from DPCD over Aux Chan Transmit Training Pattern 2/3/4 symbols over Main Link Repeat if CE, SL, LA not done; Otherwise: Link Training done. Link Maintenance Mode IRQ HPD Interrupt Request Checks if CE, SL, LA are achieved Checks if CE, SL, LA are achieved Link Training Mode Link Training has been completed. Link failure occurs; Interrupt generated Link Training re-initiated

Link Layer Compliance Test

Link Layer Compliance Testing Selecting the Tests Access the Test Selection tab. Choose the Test Category tabs. Select the specific tests.

Link Layer Compliance Testing Viewing the Link Layer Test Results Compliance Test Results window. Shows Test File name. Lists each test. Provides Pass/Fail status for each test. HTML Report available. Explode out each test to see details. Let s look at some examples

Link Layer Compliance - Failure Clock Recovery (Example 5.3.1.3 test) Double Click on any record to open ACA Trace File Sample Link Layer Compliance test results. Let s look at a failure on 5.3.1.3 test. Explode out the test to see the details. Double click on any record to open up the associated ACA trace file for that test.

Link Layer Compliance - Failure Clock Recovery (Example 5.3.1.3 test) Example: Link Layer 5.3.1.3 test failure. Test Fails because the sink (display) under test achieves Clock Recovery on Lane1 even though the reference source (980 DP Source) is sending an invalid video stream on Lane 1.

Link Layer Compliance - Symbol Error Count (Example 7.2.1.4 Test) Double Click on any record to open ACA Trace File Sample Link Layer Compliance test results. Let s look at a failure on 7.2.1.4 test. Explode out the test to see the details. Double click on any record to open up the associated ACA trace file for that test.

Link Layer Compliance - Symbol Error Count (Example 7.2.1.4 Test) Example: Link Layer 7.2.1.4 Test. Test Fails because the sink (display) under test DPCD value for Symbol Error Count is not 1 for the 5.4Gb/s, 4 Lane test.

DisplayPort Main Link Protocol Analysis

DisplayPort Capture Viewer Event Plot Panel Data Decode Panel Time Time Data Decode Panel (Details) Link Symbol Panel Time There are 3 separate panels in the Capture Viewer: 1) Event Plot, 2) Data Decode, 3) Link Symbol panel (all lanes). The panels are all in sync with one another. Transaction details are shown in Data Decode Details panel. Event time is left to right (or top to bottom on the Link Symbol Panel). You can search for events and specific control characters. You can filter the list to gain a specific view of any one event type or set of event types.

DisplayPort Main Link Protocol One Video Frame Lines VERTICAL BLANKING Video packets occur during the active video period. Metadata: Main Stream Attributes (MSA) and Secondary Data Packets (SDP) occur during the vertical blanking period and are identified with Framing control characters. Fill characters are zeros for filling up (stuffing) the unused link symbols. Video Fill Characters Lines Metadata Audio samples Control Symbols

Vertical Blanking Vertical Blanking Vertical Blanking Vertical Blanking DisplayPort Main Link Protocol Video and Vertical Blanking Structure Blue areas are the vertical blanking. Greenish areas are the video, stuffing and control characters. Video Video Video

DisplayPort Main Link Protocol Video and Horizontal Blanking Structure Empty areas are horizontal blanking. Greenish areas are the video, stuffing and control characters. Video Horizontal Blanking Video

DisplayPort Main Link Protocol Framing Control Symbols Framing control symbols are used to identify the beginning and end of: 1) Vertical Blanking, 2) Fill characters, 3) Secondary Data packets.

DisplayPort Main Link Protocol Framing Control Symbols Showing end of Video Display Frame, beginning of vertical blanking. Also showing the horizontal blanking region.

Fill Chars DisplayPort Main Link Protocol Horizontal Blanking Horizontal Blanking Fill Characters Horizontal blanking is stuffed with fill characters. Fill characters are zeros as indicated on the Link Symbol panel. Fill Chars

DisplayPort Main Link Protocol Horizontal Blanking Horizontal blanking is preceded by the four (4) character sequence of Blanking Start (BS), Blanking Fill (BF) followed by the VBID. The VBID data indicates that this blanking period is not Vertical Blanking.

DisplayPort Main Link Protocol Framing Control Symbols Showing end of Video Display Frame, beginning of vertical blanking.

DisplayPort Main Link Protocol Framing Control Symbols Showing end of Video Display Frame, beginning of vertical blanking. Fill regions are visible as are some of the protocol elements in the vertical blanking region.

DisplayPort Main Link Protocol Main Stream Attributes Main Stream Attribute (MSA) data also appears once per frame in the Vertical blanking. MSA details shown in Data Decode Details panel. MSA data indicates the timing parameters and video attributes such as video type (YCbCr), sampling (4:4:4), color depth (10 bit), etc. MSA includes the Mvid and Nvid parameters for stream clock regeneration. MSA packets are demarcated by the Secondary Data Start (SS) and Secondary Data End (SE) protocol control packets.

DisplayPort Main Link Protocol Audio Sample Packets Audio Sample Packets are interspersed in the Vertical Blanking (and the horizontal blanking). The control elements in the Vertical Blanking (BS,BF,BF,BS,VBID) follow a cadence. From a distance we can see where the sample packets are.

DisplayPort Main Link Protocol Audio Sample Packets (2 Channel) Audio Sample Packets occur in the Vertical Blanking and the horizontal blanking. Audio sample data shown in Data Decode Details panel. Audio sample packets include the audio and header information about what the audio format is. Audio Sample packets are demarcated by the Secondary Data Start (SS) and Secondary Data End (SE) protocol control packets.

DisplayPort Main Link Protocol Audio Timestamp Audio Timestamp packets occur once per video frame in the Vertical Blanking. Audio Timestamp values shown in the Data Decode Details panel. Maud and Naud values in the Audio Timestamp packet data are used to reconstruct the audio stream s sampling frequency. Audio Timestamp packets are demarcated by the Secondary Data Start (SS) and Secondary Data End (SE) protocol control packets.

DisplayPort Main Link Protocol Audio CTA Infoframe Audio (CTA) Infoframe packets occur once per video frame in the Vertical Blanking. Audio Infoframe values shown in the Data Decode Details panel. Include values for audio format (e.g. LPCM) audio sampling rate (e.g. 48kHz), number of channels and audio bit depth (e.g. 16 bits). Audio Infoframe packets are demarcated by the Secondary Data Start (SS) and Secondary Data End (SE) protocol control packets.

DisplayPort Main Link Protocol High Dynamic Range (HDR) Infoframe High Dynamic Range (HDR) infoframe, when required, occurs once per frame in the Vertical Blanking. HDR values are shown in the Data Decode Details panel. HDR parameter values enable a UHD display to put itself in the correct mode to produce the intended High Dynamic Range video and imagery. HDR Infoframes are demarcated by the Secondary Data Start (SS) and Secondary Data End (SE) protocol control packets.

HDMI Protocol Analysis and Compliance Testing

980B Advanced Test Platform Features / HDMI Modules 980B Test Platform Standard Features: 15 inch touch screen 1280 x 768 resolution. Operates through embedded touch display or remote GUI from host PC. Accommodates up to five (5) 980 series modules. Command line control via telnet. Software upgradable. Modules: HDMI 1.4 300MHz Protocol Analyzer module. HDMI 2.0 600MHz Video Generator module. HDMI 2.0 600MHz Protocol Analyzer module. DisplayPort 1.2 Video Generator / Analyzer module. DisplayPort 1.4 Video Generator / Analyzer module. 12G-SDI Video Generator / Analyzer module. Phy & Protocol Aux Channel Analyzer module.

980B HDMI Compliance Tests Supported 980B Test Platform HDMI Protocol Compliance: HDMI 1.4b Source Tests HDMI 1.4b Sink Tests HDMI 2.0 Source Tests HDMI 2.0 Sink Tests CEC 2.0 Tests HDMI HDCP: HDCP 1.4 Source Tests HDCP 2.2 Source Tests HDCP 2.2 Sink Tests HDCP 2.2 Repeater Tests

HDMI Anatomy HDMI Source Video Audio HDMI Transmitter TMDS Channel 0 (R V/H sync) TMDS Channel 1 (G Control) TMDS Channel 2 (B Control) HDMI Sink HDMI Receiver Video Audio The Capture data is primarily TMDS but the Aux Channel data is also in the capture (such as the DDC HDCP transactions). Control/Status TMDS Clock Channel Control/Status HDCP CEC HEAC (HEC/ARC) Detect Display Data Channel (DDC) CEC Bus Utility Line/+5V Hot Plug Detect Line HDCP & EDID CEC HEAC (HEC/ARC) High / Low

HDMI Video Raster TMDS Video and Timing Elements All the data elements on this illustration can be viewed through the Capture data utility and some more that are not shown.

980 GUI Manager Viewing 980 Capture HDMI Structure / Arrangement

HDMI Capture Analysis HDMI Video / Structure Arrangement We look at the captured video frames to determine how many frames there were (this is one way of doing it). Notice there are 14 video frames. The Frames are blue because the data is encrypted with HDCP and we are not allowed to show the actual video frames as it would be a violation of HDCP rules.

HDMI Capture Analysis HDMI Video / Structure Arrangement You can also determine the number of video frames by looking at the number of Vsyncs (again 14). Notice also that there are 14 HDCP encryption enable pulses; one for each frame We can zoom in to see the frame boundaries.

HDMI Capture Analysis HDMI Video / Structure Arrangement You can see two of the frame boundaries (indicated).

HDMI Capture Analysis HDMI Video / Structure Arrangement We can zoom into see the metadata in the vertical blanking (next slide).

HDMI Capture Analysis HDMI Video / Structure Arrangement We can now see a video data elements and the Hsync pulses. We can also see the entire Vsync. The Hsync pulses are also visible (Hsyne pulses occur per line of video). We have measured the Vsync pulse using the measuring tool (43972 pixels in length).

HDMI Capture Analysis HDMI Video / Structure Arrangement We zoom in more and surround some of the metadata in the vertical blanking (next slide).

HDMI Capture Analysis HDMI Video / Structure Arrangement We can now see an audio sample packet, a Vendor Specific InfoFrame and an AVI InfoFrame. The AVI InfoFrame is selected and we can see the values in the Data Decode panel details below. There is only one AVI InfoFrame per video frame. We can also see an Hsync for horizontal blanking (per line) pulse and measure that if desired.

HDMI Capture Analysis HDMI Video / Structure Arrangement We have panned to the right and now we can see some more data islands in the Vertical Blanking (during Vsync). The Source Product Descriptor (SPD) and the Audio InfoFrame which is selected and we can see the values in the Data Decode panel details below.

980 GUI Manager Viewing 980 Capture Data Video Frames

HDMI Video Pixel Data Analysis Click on one of the image frames. See results next slide.

HDMI Video Pixel Data Analysis Essential video data on the top panel. You can view the color values of the cursor location and a marker location. Navigate around the image using the arrow keys at the bottom.

980 GUI Manager Viewing 980 Capture Data Timing Data

HDMI Video Timing Analysis General timing data is shown in the Video Format sub panel; this shows the format and the pixel rate among other things. The Frame timing statistics are shown in the second panel. The Line timing parameters (of the frame that you have highlighted) are shown in the lower panel. Timing errors will be highlighted.

980 GUI Manager Viewing 980 Capture Data Protocol Data

HDMI Video, Audio and Metadata Capture Notice the protocol elements (preamble and guard band). Let s Zoom in (next slide). Special Note: Our competitors cannot show this protocol data.

HDMI Protocol Capture After zooming in. Same searching and filtering tools apply to the protocol data capture. Closer zoom next slide.

HDMI Protocol Capture After zooming in more. Notice the timing elements (Hsync [horizontal] and Vsync [vertical]). DI means there are data islands packets such as Infoframe packets that are not shown in the protocol data capture.

HDMI Protocol Capture After zooming in more in a different location. Notice that you can see how the protocol data is aligned and interspersed with the video data and the timing data.

HDMI Protocol Compliance Testing

HDMI Protocol Compliance Testing HDMI 1.4b source DUT testing 7-16 ~ 7-40 HDMI 1.4b sink DUT testing 8-1 ~ 8-31 HDMI 2.0 source DUT testing HF1-10 ~ HF1-55 HDMI 2.0 sink DUT testing HF2-5 ~ HF2-58 CEC 2.0 testing HF4-1-3 ~ HF4-3-2 HDCP 1.4 source DUT testing 1A-01 ~ 1B-06 HDCP 2.2 source DUT testing 1A-01 ~ 1B-10 HDCP 2.2 sink DUT testing 2C-01 ~ 2C-05 HDCP 2.2 repeater DUT testing 3A-01 ~ 3C-25

HDMI 2.0 Source Protocol Compliance Testing The name is shown on the top. The results show pass or fail (pass in this case). Note the extensive details are provided for each test. The paragraph notations (e.g. 4.3.1) map to the sections in the HDMI 2.0 Compliance Test Spec. Details are useful for identifying the root cause of failures when they occur. (In this case there were no failures).

HDMI 2.0 Source Compliance Testing You can open up the HTML report (results next slide).

HDMI 2.0 Source Compliance Testing Test Report When you run the report you can elect to include the CDF or not. Here we show the CDF in the report. The results are on the next slide.

HDMI 2.0 Source Compliance Testing Test Report Test results. Notice the detail in the reports.

HDMI 2.0 Source Video Compliance Test You can explode out the tests to reveal the details for any subtest that you want. Note the details provide for each test. Each iteration and each subtest in each iteration maps to the sections in the HDMI 2.0 Compliance Test Specification. And of course you can always run the HTML report.

HDMI 2.0 Source Video HDR Compliance Test You can explode out the tests to reveal the details for any subtest that you want. Notice here we have some failures. You can view the details to pinpoint the cause of the failure. You could then view the data in the associated capture file (next slide). And of course you can always run the HTML report.

HDMI 2.0 Source Video HDR Compliance Test Let s see if we can find the failure by searching and filtering through the capture file associated with the failure in the HDR test. The failure is with the HDR InfoFrame so let s filter on that (results next slide).

HDMI 2.0 Source Video HDR Compliance Test We can look at the HDR InfoFrame consult the spec and determine the reason for the failure. The associated capture data enables an engineer to confirm that the problem exists. You can export and disseminate the entire report data to colleagues or other subject matter experts or HDMI, LLC or even TLC customer support.

HDMI 2.0 Sink HDR Compliance Test Here we see there is a failure in the EDID data wrong value in one of the fields related to HDR. With the 980 Video Generator you could access the byte in the EDID (see next slide).

HDMI 2.0 Sink HDR Compliance Test Here we see EDID decode. From this we could determine the incorrect data in the HDR compliance test failure on the previous slide.

Thank you for attending Questions? Please contact me, Moon Ki Cho at: MoonKi.Cho@teledyne.com if you have any questions.