Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217 (Digital Logic Design), which is a prerequisite for taking this course. The slides of chapter 2 are mainly provided for students to review, and will be briefly discussed in class. 1
Digital Signal To obtain typical digital signal: LOW or 0 = 0~+0.8V HIGH or 1 = 2~5V A such 1 or 0 can be one bit of a binary number, one bit of a binary code (ASCII,BCD, ), a control signal state, etc. 2
Parallel and Serial Transmission Parallel transmission: multiple transmission lines Serial transmission: single transmission lines 3
Logic Gates AND gate OR gate NOT gate NAND gate NOR gate XOR gate XNOR gate 4
Tri-State Logic Output X has three states: high low high-impedance state. 5
Flip-Flops D Flip-flop JK Flip-flop D-type Latch 6
Synchronous and Asynchronous FF Inputs J, K, D, and T are synchronous inputs since they are synchronized to the clock signal The preset PRE and clear CLR inputs are asynchronous These inputs respond to dc levels not transitions used to set FF output to HIGH or LOW as desired immediately or to hold the FF in a particular state 7
Setup and Hold Times Two timing requirements must be met if a clocked FF is to respond reliably to its control inputs when a clock transition occurs: ts(5-50ns), th(0-10ns) 8
FF Registers A register: a group of memory circuits used to store binary information. More complex registers may also modify the information, e.g. counters, shift registers 9
IC Registers Data-Latching Registers Use D-type latches Edge-Triggered Registers Use edge-triggered D FFs Tri-State Registers If multiple devices are connected to one bus, then the devices may need to have tri-state buffers 10
Data Busing Microprocessor is connected to several devices over a 8 line bus The bus is simply a set of conducting paths (wires) To avoid bus contention problems (more than one signal tied to the same bus active at once) tri-state outputs or buffers are used Only one enable signal should ever be active at any given time 11
Data Bus Operation Contents of any register can be parallel-transferred over the bus to any of the others E.g. to transfer [A] [C]: Only register A should have enabled outputs. So, This will cause the contents of A to appear on the data bus lines Next only C should have its inputs enabled. So, On the next rising clock edge C will accept the data from the bus 12
Bus Signals To transfer the data 1011 from register A to register C: Prior to t0 all output enable lines are high, thus all bus lines are high-z At t0 the outputs of A are enabled and its data appears on the bus At t1 the rising edge of CLK latches valid data from the bus into C At t2 the outputs of A are disabled and the bus lines return to high-z Simplified way (Fig. 2.23, p.58) 13
Encoders and Decoders Encoder: Takes a 2N binary code as input and generates an identifying output signal unique to each possible code Decoder: Generates a 2N binary output code corresponding to activation 14
Multiplexers Accepts several input signals and selects one to pass through to the output according to SELECT or ADDRESS inputs 15
Multiplexers Accepts several input signals and selects one to pass through to the output according to SELECT or ADDRESS inputs 16
Troubleshooting Digital Circuits Internal IC Faults Malfunction in internal circuitry Inputs or outputs shorted to ground or VCC Inputs or outputs open-circuited Short between two pins (other than ground or VCC ) External IC Faults Open signal lines Shorted signal lines Faulty power supply Output loading 17