SMPTE 292M EG-1 Color Bar Generation, RP 198 Pathological Generation, Grey Pattern Generation IP Core - AN4088 January 18, 2005 Document No. 001-14938 Rev. ** - 1 -
1.0 Introduction...3 2.0 Functional Blocks...3 2.1 SMPTE 292M Pattern Generation Set-Up... 3 2.2 SMPTE 292M Color Bar Test Pattern... 5 2.3 RP 198 Pathologicals Test Pattern... 7 2.3.1 Equalizer Test... 7 2.3.2 PLL Test... 7 2.4 Grey Pattern Generation... 7 3.0 IP Core Features...8 4.0 Resource Usage...8 4.1 EG-1 Color Bar Resource Usage... 8 4.2 RP 198 Pathologicals Resource Usage... 8 4.3 Grey Pattern Resource Usage... 8 5.0 Block Diagrams...9 6.0 Signal Descriptions...10 6.1 SMPTE 292M Color Bar Generation Signal Descriptions...10 6.2 SMPTE 292M RP 198 Pathologicals Test Pattern Generation... 10 6.3 SMPTE 292M Grey Pattern Generation... 10 January 18, 2005 Document No. 001-14938 Rev. ** - 2 -
1.0 Introduction The Society of Motion Picture and Television Engineers (SMPTE) specifies several test patterns to verify the integrity of a video system. There are three test patterns which comply with SMPTE 292M High Definition (HD) standards documented in this application note. The color bar test pattern conforms to the standards of SMPTE s Engineering Guideline 1 (EG-1). The purpose of the color bars is to have a standard to adjust chroma gain, chroma phase, and black level monitor controls. The Recommended Practice 198 (RP 198) test pattern is named as the pathological test pattern. RP 198 test patterns are meant to stress parts in the system such as the equalizer and Phase Lock Loop (PLL). The final test pattern discussed in this document is the grey pattern. The grey pattern is a pattern specified by Cypress Semiconductor to test the video systems. All of the above test patterns comply with SMPTE 292M standards. 2.0 Functional Blocks Each test pattern generation has one HDL module. The EG-1 color bars are generated with eg1_292.vhd; the RP 198 Pathologicals are generated with RP198.vhd; and the grey pattern is generated with grey.vhd. Although each test pattern is generated in a separate module, the initial test pattern set up is common to all the HD test patterns. 2.1 SMPTE 292M Pattern Generation Set-Up SMPTE 292M requires two sets of data to be generated in parallel, the Luminance (Y) data and the Color difference (C B, C R ) data. Hence for all HD applications there will be two sets of data. Regardless of the video data being transmitted, HD signals need to have blanking intervals and Timing Reference Signals (TRS). According to SMPTE 292M, HD interlaced scanning vertical timing is carried out according to Figure 1. There are three vertical blanking intervals, and two fields of active video. Field 1 consists of the odd lines to displayed on the screen and Field 2 consists of the even lines to be displayed on the screen. Horizontal timing references also exists for each line. Each line contains information regarding Start of Active Video (SAV) timing reference, Horizontal line blanking, End of Active Video timing reference (EAV), and the active video data. Figure 2 displays the horizontal line data. EAV + LN + CRC LINE 1 FIELD 1 (F = 0) ODD LINE 583 FIELD 2 (F = 1) EVEN LINE 1125 H = 1 EAV H = 0 SAV BLANKING FIELD 1 ACTIVE VIDEO BLANKING FIELD 2 ACTIVE VIDEO BLANKING LINE 1 (V = 1) LINE 21 (V=0) LINE 561 (V = 1) LINE 584 (V = 0) LINE 1124 (V = 1) LINE 1125 (V = 1) Figure 1. SMPTE 292M Digital Vertical Timing Horizontal Blanking Interval SAV Active Video Data 1920 1928 2196 0 1919 Figure 2. Horizontal Line Data SMPTE 292M specifies 2200 Total Samples per Line (TSL), and of the 2200 TSL, there are 1920 Active Samples per Line (ASL) for the 1080i resolution. The TSL count for the HD test pattern generators starts at 0, and ends at 2199. The first packet of information generated is the EAV, Line, and Cyclic Redundancy Code (CRC) information. The EAV consists of four words. The first three words are ancillary header data and are set at 3FF h, 000, and 000. The only word which varies is the last word, XYZ. The 10-bit XYZ word contains information according to Table 1. January 18, 2005 Document No. 001-14938 Rev. ** - 3 -
Table 1. XYZ Word Word 1923 and Bit 2199 Description 9 1 Fixed 8 F F = 0 during field 1 F = 1 during field 2 7 V V=0 during active video V=1 during vertical blanking 6 H H=1 for EAV H=0 for SAV 5 S S=0 for GBR signals S=1 for Y, C b, C r signals 4 P4 Dependent on bits 8-6 3 P3 Dependent on bits 8-6 2 P2 Dependent on bits 8-6 1 P1 0 0 P0 0 Table 2 contains the values for S, and P2-P4 based on bits 6 through 8. The EAV words are inserted into the Y_DATA and C_DATA vectors and transmitted. Table 2. Bits 5 to 2 for the XYZ Word Bit 8 Bit 7 Bit 6 S P4 P3 P2 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 OTHER 0 0 0 1 After the EAV, there are two words for the line information followed by 2 words for the CRC information. The Line word requires 11 bits, and video data is only 10 bits. Hence, the Line data is separated into two words: LN0 and LN1. Table 3 shows where the Line bits are allocated between the two words. The polynomial used to generate CRC information is as follows: X 18 + X 5 + X 4 + 1 Once the CRC numbers are generated, the data is inserted into words 1926 and 1927. Two separate 10-bit words are required because the CRC checkword is 18 bits in length. Since the luminance and color difference data are generated in parallel, two separate CRC calculations exist for luminance and color difference. Therefore, there is a total of 4 CRC checkwords. Table 4 displays the allocation of the CRC data bits. For more information on CRC calculations please refer to the, SMPTE 292M Cyclic Redundancy Code (CRC) IP Core application note. The horizontal blanking interval has values of 0x40 and 0x200 for Y_DATA and C_DATA respectively.the next packet generated is the SAV packet. The SAV information occupies the last 4 words in a video line. Once again, there are three ancillary header words, 3FF h, 000, and 000. he final word is once again the XYZ word. After generating the EAV, horizontal blanking interval, and SAV data, the active video data is generated. Table 3. Line Bits Allocation Word Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LN0 b8 L6 L5 L4 L3 L2 L1 L0 0 0 LN1 1 0 0 0 L10 L9 L8 L7 0 0 Table 4. CRC Bits Allocation Word Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 YCR0 b8 CRC8 CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 YCR1 b8 CRC17 CRC16 CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CCR0 b8 CRC8 CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 CCR1 b8 CRC17 CRC16 CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 January 18, 2005 Document No. 001-14938 Rev. ** - 4 -
2.2 SMPTE 292M Color Bar Test Pattern The active video data generation is the information which distinguishes ones test pattern from another. Figure 3 shows the color bar pattern in terms of the amount of active line time that each color bar requires. The first row of color bars requires 67% of the active line time, the second row requires 8% of the active line time, and the final row requires 25% of the active line time.the active video data generated according to the R,G,B, and Y, C B, C R as displayed in Table 5. The Y, C B, and C R numbers in Table 5 are generated according to the following formulas: Normalized formulas: Y = 0.2126R + 0.7152G + 0.0722B P B = 0.114572R 0.385428G + 0.5B P R = 0.5R 0.454153G 0.045847B Scaling for 10-bit data: Y = 186.2376R + 626.5152G + 63.2472B + 64 C B = 448R 406.921088G 41.078912B + 512 C R = 102.656512R 345.343488G + 448B + 512 The color bars are generated in sections. The first section generated is the row of color bars which require 67% of the line time. The color bars in the first row are evenly spaced horizontally. Therefore, each bar requires ASL/7 words in each line. For example, in the HDL module a test condition is placed on the current word. If the word is between 0 and ASL/7-1, the grey bar data is placed into the output data. The Y value from Table 5 is placed into the Y_Data vector and transmitted. The Color difference data is placed into the D_Data vector and transmitted. The C B data is transmitted on the even words, and the C R data is transmitted on the odd words. After the first row of bars are generated, the second row of bars is generated in a similar fashion. The difference for the second row is that it only requires 8% of the line time. The final row to be generated is not evenly spaced horizontally. This is easily accounted for by the different test conditions on the current word number. All of the test pattern data is only generated on the rising edge of the clock source. b b b b b b b GRAY YELLOW CYAN GREEN MAGENTA RED BLUE 67% 100% BLUE BLACK MAGENTA BLACK CYAN BLACK GRAY 8% -I WHITE +Q BLACK BLK BLK BLK BLACK 5/4b 5/4b 5/4b 5/4b b 3 b = 1/7 Active Line Time b 3 b 3 Figure 3. Color Bar Test Signal January 18, 2005 Document No. 001-14938 Rev. ** - 5 -
Table 5. SMPTE 292M Active Video Data for Color Bars Color Bar R G B Y C B C R 100% White 1 1 1 940 512 512 75% White 0.75 0.75 0.75 721 512 512 75% Yellow 0.75 0.75 0 674 176 543 75% Cyan 0 0.75 0.75 581 589 176 75% Green 0 0.75 0 534 253 207 75% Magenta 0.75 0 0.75 251 771 817 75% Red 0.75 0 0 204 435 848 75% Blue 0 0 0.75 111 848 481 black 0 0 0 64 512 512 black - 4% 0.04 0.04 0.04 29 512 512 black +4% 0.04 0.04 0.04 99 512 512 -I (legal RGB) 0.0000 0.2456 0.4125 244 612 395 +Q (legal RGB) 0.2536 0.0000 0.4703 141 697 606 2.3 RP 198 Pathologicals Test Pattern In digital communications systems, it is desirable to have an equal number of ones and zeros. Digital video systems employ scramblers to optimize systems for such a scenario. There are, however, three cases in which the scrambler does not optimize the video data and there is a poor ratio of ones to zeros. The special cases which cause poor ones to zeros ratios are called pathologicals. The equalizer test, and the Phase-Locked Loop (PLL) test are two of the pathologicals. The third pathological occurs during the vertical blanking interval, and rarely occurs, therefore it is not included in the test pattern generator. To set up for the equalizer test, if standard alternation is desired, the first active data in the line after the vertical blanking interval is set to 190 h. If alternate distribution is desired, then the first active data in the line after the vertical blanking interval is set to 198 h. 2.3.1 Equalizer Test One of the pathologicals occurs when there is a continuous pattern of 19 HIGHs and 1 LOW or 1 LOW and 19 HIGHs. This pattern appears as a flat magenta-like color. The scrambler used in SMPTE 292 video systems does not optimize for this pattern, and the ratio of ones to zeros becomes 1 to 19 or 19 to 1. This results in a large amount of low-frequency energy, and stresses the equalizer. As a result, this pattern is referred to as the equalizer test. The 19 HIGHs and 1 LOW pattern is easily generated by transmitting continuous 198 h and 300 h data in the luminance and color difference output vectors respectively. If a designer wishes to transmit 19 LOWs and 1 HIGH, then the std_altn input signal should be set to LOW. This will switch the data, and 300 h will be transmitted as the luminance data and 198 h will be transmitted as the color difference data. For this HDL module, the equalizer test is generated in the first half of the active video picture. Figure 4 shows the data allocation in each frame for RP 198 HDL module. 2.3.2 PLL Test The second pathological pattern included in the RP 198 HDL module is the PLL test. To generate the PLL test, a continuous pattern of 20 HIGHs and 20 LOWs, or vice versa, is generated. This pattern has a low transition density of ones and zeros. For better performance, the PLL requires high transition density. Therefore, this test is referred to as the PLL test and is displayed as grey in the video picture. The PLL test pattern is generated by continuously transmitting 110 h in the luminance output vector, and 300 h in the color difference output vector. If a designer wishes to transmit 20 LOWs and 20 HIGhs, the data can be switched, and 300 h is transmitted as the luminance data and 110 h is transmitted as the color difference data. The PLL pathological is generated on the second half of the active video picture in the RP 198 HDL module. 2.4 Grey Pattern Generation The grey pattern test generation is simply the continuous generation of 511 for the luminance data and 512 for the color difference data. The generated video picture will be a grey picture. January 18, 2005 Document No. 001-14938 Rev. ** - 6 -
Vertical Blanking Interval 1st Half of Active Picture 300h, 198h (Equalizer Test) EAV SAV Horizontal Blanking Interval 2nd Half of Active Picture 200h, 110h (Phase Lock Loop Test) Figure 4. RP 198 Frame Data Allocation 3.0 IP Core Features This IP Core includes HDL modules for SMPTE 292M EG-1 Color Bar, RP 198 Pathologicals, and Grey Pattern generation. This IP core allows designers to implement the test patterns and comply with SMPTE 292M HD standards. The deliverables for this IP Core include eg1_292.vhd, rp198.vhd, and grey_292.vhd. This IP Core assumes prior knowledge of the HOTLink II SERDES. Please visit www.cypress.com for more information. Complies with SMPTE 292M, EG-1, and RP 198 Supports 1080i active resolution at 30 Hz for HD video Communicates with the HOTLink II SERDES 4.0 Resource Usage 4.1 EG-1 Color Bar Resource Usage The SMPTE 292M EG-1 color bar generator requires 483 logic cells out of a total of 20,060 logic cells in an Altera Cyclone FPGA, using the Quartus II compiler. This code will also work with Xilinx and other programmable logic devices. 4.2 RP 198 Pathologicals Resource Usage The SMPTE 292M RP 198 pathologicals generator requires 295 logic cells out of a total of 20,060 logic cells in an Altera Cyclone FPGA, using the Quartus II compiler. This code will also work with Xilinx and other programmable logic devices. 4.3 Grey Pattern Resource Usage The SMPTE 292M grey pattern generator requires 255 logic cells out of a total of 20,060 logic cells in an Altera Cyclone FPGA, using the Quartus II compiler. This code will also work with Xilinx and other programmable logic devices. January 18, 2005 Document No. 001-14938 Rev. ** - 7 -
5.0 Block Diagrams CLK Y_DATA SMPTE 292M Color Bar Pattern Generation ENABLE C_DATA Figure 5. SMPTE 292M Color Bar Pattern Generation Block Diagram CLK Y_DATA ENABLE SMPTE 292M RP 198 Pathologicals C_DATA STD_ALTN Figure 6. SMPTE 292M RP 198 Pathologicals Generation Block Diagram CLK Y_DATA SMPTE 292M Grey Pattern Generation ENABLE C_DATA Figure 7. SMPTE 292M Grey Pattern Generation Block Diagram January 18, 2005 Document No. 001-14938 Rev. ** - 8 -
6.0 Signal Descriptions 6.1 SMPTE 292M Color Bar Generation Signal Descriptions Signal Inputs Width Active Description CLK N/A N/A The clock signal for the programmable logic device provided by an external source. ENABLE 1 HIGH Enables the color pattern generation when HIGH. The color pattern generation is disabled when LOW. Signal Outputs Width Active Description Y_DATA 10 N/A The luminance output data being transmitted from the programmable logic device to the HOTLink II family of SERDES devices. C_DATA 10 N/A The color difference output data being transmitted from the programmable logic device to the HOTLink II family of SERDES devices. 6.2 SMPTE 292M RP 198 Pathologicals Test Pattern Generation Signal Inputs Width Active Description CLK N/A N/A The clock signal for the programmable logic device provided by an external source. ENABLE 1 HIGH Enables the color pattern generation when HIGH. The color pattern generation is disabled when LOW. STD_ALTN 1 HIGH Standard distribution is selected when HIGH. Alternate Distribution is selected when LOW. Signal Outputs Width Active Description Y_DATA 10 N/A The luminance output data being transmitted from the programmable logic device to the HOTLink II Family of SERDES devices. C_DATA 10 N/A The color difference output data being transmitted from the programmable logic device to the HOTLink II Family of SERDES devices. 6.3 SMPTE 292M Grey Pattern Generation Signal Inputs Width Active Description CLK N/A N/A The clock signal for the programmable logic device provided by an external source. ENABLE 1 HIGH Enables the color pattern generation when HIGH. The color pattern generation is disabled when LOW. Signal Outputs Width Active Description Y_DATA 10 N/A The luminance output data being transmitted from the programmable logic device to the HOTLink II family of SERDES devices. C_DATA 10 N/A The color difference output data being transmitted from the programmable logic device to the HOTLink II family of SERDES devices. HOTLink II is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. January 18, 2005 Document No. 001-14938 Rev. ** - 9 -
Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: 408-943-2600 Fax: 408-943-4730 http://www.cypress.com Cypress Semiconductor Corporation, 2005-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. January 18, 2005 Document No. 001-14938 Rev. ** - 10 -