3030K Data sheet (Brief) ixelplus Co.,Ltd 3030K 1/6.2 nch VGA Single Chip CMS MAGE SENSR Last update : 20. Sept. 2004 XELLUS C,. LTD Kyunggi Verture B/D 502,#1017 ngae Dong aldalku Suwon city Kyunggido,442070 Korea Tel : 82312345311, FAX : 82312345287 Copyright 2004, ixelplus Co.,Ltd ALL RGHTS RESERVED age 1 of 5
ixelplus reliminary 3030K CMS mage Sensor with 640 X 480 ixel Array and ntegrated nchip mage Signal rocessor Features This document is an initial draft. t will be revised on without prior notice. Contact ixelplus for upto date information. 1/6.2 inch 640 X 4 80 effective pixel array with color filters and microlens. owe r supply 1.8V for core and 1.8 ~ 3.3V for /. utput formats : 8bit YCbCr / 9Bit Bayer data / 5:6:5 RGB / 8bit Y 30 frames/sec prog ressive scan @27 MHz master clock. mage processing on chip : lens shading, gam ma correction, de fect correction, low pass filter, color interpolation, edge enhancement, color corr ection, contrast stretch, color saturation, white balance, exposure control and back light compensation. Still image capture with electrical shutter. Frame size, window size and position controllable through a serial inte rface bus. VGA / QVGA / QQVGA Scaling. Horizontal / Vertical mirro ring. 50Hz, 60Hz flicker cancellation. ackage : 40 pin CLCC, 32 pin CS D4 D3 D2 D1 D0 MCLK HSYNC 36 37 38 39 40 1 2 3 4 5 STDBY VREF VREFN RSTB 35 34 33 32 31 30 29 28 27 26 3030K 40 pin C LCC 6 7 8 9 10 11 12 13 14 15 D7 D6 D5 V SYNC CLK XELLUS C,. LTD 25 24 23 22 21 20 19 18 17 16 peration Temp. Dynamic Range < Figure. 1> in Diagram ackage Table 1. Typical aram eters Total ixel Array 648 X 488 ixel Size m age Area Clock Rate Frame rate Dark Current Sensitivity Saturation Level Conversion Gain 3.6um X 3.6um 2.30 mm X 1.72 mm 27 MHz (Max.) Variable up to 30fps TDB na/ TDB V/Lux.sec @15fps,R cut filter TDB mv Fill Factor 40 % Supply voltage ower consumption TDB /electrons 1.8~3.3V /,1.8V Core TDB mw @15fps, active TDB uw @standby TDB TDB db 40 pin CLCC, 32 pin CS age 2 of 5 2/5
ixelplus reliminary 3030K CMS mage Sensor with 640 X 480 ixel Array and ntegrated nchip mage Signal rocessor N Descriptions in No. 1 2 3 4 5 6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 RSTB System reset must remain low for at least 8 master clocks after power is stabilized. When the sensor is reset, all registers are set to their default values. Analog vdd : 1.8V DC. 100nF capacit or to. Analog ground. Analog ground. Analog vdd : 1.8V DC. 100nF capacit or to. XELLUS C,. LTD 31 Name MCLK HSYN C CLK VSYNC D5 D6 D7 / Type / Functions / Descripti ons Digital vdd for / : DC 1.8~3.3V. Voltage range for all outp ut signals is 0V ~. Digital ground. Core and / c ircuits share the ground pads. Digital vdd for core lo gic : 1.8 V DC. 100nF capacitor to. Master clock input pad. Horizontal synchroniz ation pulse. HSYNC is high ( or low ) for the horizontal window of interest. t can be programmed to app ear or not outside the vertical window of interest. ixel clock. Data can be latched by external devices at the rising or falling ed ge of CLK. The p olarity can be controlled anyway. Digital vdd for / : DC 1.8~3.3V. Voltage range for all outp ut signals is 0V ~. Digital ground. Core and / c ircuits share the ground pads. Digital vdd for core lo gic : 1.8 V DC. 100nF capacitor to. Vertical sync : ndicat es the start of a new frame. Bit 5 of data output. Bit 6 of data output. Bit 7 of data output. 2C serial clock input. 2C serial data bus. Table 21. N Des criptions age 3 of 5 3/5
ixelplus reliminary 3030K CMS mage Sensor with 640 X 480 ixel Array and ntegrated nchip mage Signal rocessor in No. 32 33 34 35 36 37 38 39 40 Name VREFN VREF STDBY D4 D3 D2 D1 D0 / Type Functions / Descripti ons ADC reference voltage. 100nF capacitor to. ADC assumes VREF VREFN is t he mini mum inp ut voltage that will be converted to 1FFh. ADC reference voltage. 100nF capacitor to. ower standby mode. When STDBY= 1 there s no current flow in any analo g circuit branch, neither any beat of digital clock. D<8:0> and CLK, HSYNC, VSYNC pins can be programmed to tristate or all 1 or all 0. But it is possible to control int ernal registers through 2C bus interface in STDBY mode. All regist ers retain their current values. Bit 4 of data output. Bit 3 of data output. Bit 2 of data output. Bit 1 of data output. Bit 0 of data output. XELLUS C,. LTD Table 22. N Des criptions age 4 of 5 4/5
ixelplus reliminary 3030K CMS mage Sensor with 640 X 480 ixel Array and ntegrated nchip mage Signal rocessor Block Diagram Analog Control signal Row decoder Bias / A DC co ntrol Digital Control signal ixel array 648 X 488 CDS<0:647> ADC<0:647> Column decoder Digital Control signal < Figure. 2 > Block Diagra m 3030K has 648 x 488 effective pixe l array and column/row driver circuits to read out the pixel data progressively. CDS c ircuit reduces noise signals generated from various sources ma inly res ulting from process variations. ixel output is compared with the reset level of its own and only the difference signal is sampled, thus reducing fixed error signal level. Each of R, G, B pixel output can be multiplied by different gain factors to balance the color of images in various light conditions. The analog signals are converted to digital for ms one line at a time and 1 line data are streamed out column by column. The Bayer RGB data are passed through a sequence of image signal proces sing blocks to finally produce YCbCr 4:2:2 output data. mage s ignal processing includes such operations as gamma correction, defect correction, low pass filter, co lor interpolation, edge enhancement, color correction, contrast stretch, color s aturation, white XELLUS C,. LTD balance, exposure control and back light compens ation. nternal functions and output signal timing can be progra mmed simply by modifying the register files through 2 C serial interface. Bayer RGB 9 pclk ST DBY RST B X 1 Timing control Hsync mage Signal rocessing Vsync Data 9 Control register 2C Registers 8bits Y/UVor 9bits Bayer CLK HSYNC VSYNC age 5 of 5 5/5