Agilent EEsof EDA This document is owned by Agilent Technologies, but is no longer kept current and may contain obsolete or inaccurate references. We regret any inconvenience this may cause. For the latest information on Agilent s line of EEsof electronic design automation (EDA) products and services, please go to: www.agilent.com/find/eesof
Signal Expands Integrity SI Simulations Horizon Overview - ADS Solutions Using Advanced Design System for Signal Integrity Page 1
25 Years of Technological Innovation We combine proven technology with new innovations, a flexible, open, and proven architecture. YEAR 1980 1990 TRANSIENT CONVOLUTION SIMULATION 2006 PARAMETERIZED EM MODELS EEsof Touchstone & Libra, Academy, Series IV MDS Advanced Design System & RFDE HIGH-FREQUENCY SPICE LAYOUT DRIVEN SIMULATION MULTI-LAYER INTERCONNECT MODELS FULL-WAVE 3D EM ANALYSIS DSP / ANALOG CO-SIMULATION 2.5D EM ADAPTIVE POLYGONAL MESHING ELECTRONIC LAB NOTEBOOK SMART SIMULATION WIZARD LINUX SUPPORT Verilog-A Patent Pending Convolution Technology TECHNOLOGY PC-BASED LINEAR SIMULATOR FULL-WAVE 2D EM ANALYSIS YIELD OPTIMIZATION OPTIMIZATION FROM LAYOUT DESIGN OF EXPERIMENT YIELD NALYSIS MATLAB Cosimulation in ADS AUTOMATED FINITE METAL THICKNESS PHYSICAL CONNECTIVITY ENGINE DISCRETE VALUE OPTIMIZATION FAST 2.5D EM SIMULATOR Page 2
Typical SI Problem ( Ensuring Signal Quality and Timing) Channel Adaptation Pattern Generator Encoder Die Pre-emphasis/Driver Driver Package IBIS or Spice model Card Card Board Traces 2 (51mm) 10 (254mm) High speed Connectors Physical Channel IBIS or Spice model Die Receiver Physical Channel Backplane Traces 10 (254mm) 40 (1016mm) Package Card Receiver Decoder Equalizer Signal Recovery Page 3
Serial Link Analysis - Simulation Challenges S-parameter channel simulation with non-linear driver/receiver models Simulating SERDES models in a link containing analog nonlinear and linear components Post-processing waveform for BER and Jitter measurements Validation with measured data Page 4 ADS Ptolemy for Serial Link Analysis February, 2007
High Speed Digital Channel Design Expands SI Horizon - Simulates Complete Channel ADS ADS Encoder, Serializer Driver Package Board Backplane Board Package Receiver Decoder, De-serializer ADS supports all implementation domains (IC, Module, Board) ADS can analyze the full digital channel data in to data out Integrated data models and simulation technology Page 5
Combining Simulation Technologies for a Successful Design Frequency Domain Time Domain Numeric Domain Electromagnetic Domain S-Parameter AC-Simulation Harmonic Balance Convolution High Frequency SPICE Matlab HDL, C++, System-C Agilent Ptolemy Method of Moment Finite Element Analysis Finite Difference Time Domain Circuit Envelope Verilog-A HDL Page 6
ADS - Signal Integrity Simulation Seamless Integration integration of simulation technologies ADS DSP Simulator (Agilent Ptolemy) FIR, DFE, MATLAB, System-C, C++, HDL, ADS Analog Simulators ( Time, Frequency and Envelope) Interconnect Models, Driver Models ADS EM Simulators ( MOM, FEM, FDTD) Physical Models Accurately simulates SERDES models in a link containing analog non-linear and linear components including S-parameters Page 7
Enhanced Signal Integrity Simulation Capability ADS 2006 Update 1 Faster Transient Simulation Advanced Convolution IBIS I/O Models Broadband SPICE Model Generator Improved Design Flow Integration Superior Via Modeling Capability Page 8
Faster Transient Simulation In ADS 2006A, High-Frequency SPICE is 10% to 40% faster. Update 1 adds another 10% improvement due to: Algorithmic improvements Device optimization Code optimization Transient Speed-up Speed-up 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0 10 20 30 40 50 60 Circuit # Page 9
Convolution Technology Advances New engine for robust handling of S-parameter data in the time-domain, employing: Breakthrough technology accurately finds the causal timedomain response from the original S-Parameters Reference Results Optional passivity detection and correction prevents Teravolt outputs that could solve the Reference Results world s energy problems New Update 1 Engine Result: Correct time-domain response Typical SPICE simulators don t do this very well: high-speed digital board designers need this! 2006A Engine Low impedance power/ground plane (mohms) into a 50-Ohm reference impedance Page 10
IBIS Simulation in ADS Native IBIS Models in ADS in 2006 Update 1 Fast, robust and convenient to use Page 11
IBIS Device Functionality Driver Schedule New capability supports driver schedule Combines several IBIS models to simulate multi-stage drivers Provides modeling capabilities for pre-emphasis or de-emphasis buffers Vt table supported for complex terminations Page 12
Design Flow Integration with Other EDA Tools Allegro Import critical nets from Allegro environment to ADS for Momentum simulation Allegro import ADS/Momentum BBSPICE Broadband SPICE Export Momentum results to HSPICE HSPICE/PSPICE Links ADS and Momentum to external tools Page 13
Allegro Design Flow Integration - ADS Allegro PCB Design Environment Advanced Design System design and simulation environment Page 14
New E4687 Broadband SPICE Model Generator Fast and efficient way to convert S-parameter models to their SPICE equivalent Input File Format ADS dataset Citifile format Touchstone file format Momentum RAT Output Netlist Format ADS SPICE2 SPICE3 Page 15
Broadband SPICE Model Generator S-parameter data of passive components equivalent circuit models. Flowchart of the tool A rational fit is performed on the input S-parameters The fitting procedure is based on the vector fitting algorithm The passivity enforcement step modifies the residues of the model in order to obtain a passive model. Page 16
Electromagnetic Simulation Physical simulation of interconnects using Method of Moments Finite Element Analysis strip via slot mesh density = 50, 80, 100, 120, 150 Superior via hole modeling technology in ADS2006 update release Page 17
Meeting our Promise To provide you with the best high frequency time-domain design technology Powerful convolution technology ensuring causality and passivity of frequency domain models Industry best broadband SPICE model generator Native IBIS models in ADS (new IBIS interface, faster, and robust models) Allegro layout integration Transient Speed improvement by 30% ( already delivered in ADS2006A) Improved via modeling All these new features are shipping with ADS2006 Update 1 22 February, 2007 Page 18
ADS2006 Update 2 Encrypted HSPICE simulation in ADS environment New digital source in ADS Jitter analysis in ADS using Agilent s patented technology EMDS for ADS 3D EM (FEM) in ADS Link level components FFE DFE Encoders/Decoders ( 8B10B, 64B66B..) Shipment Late May 2007 Page 19
Encrypted HSPICE Simulation in ADS Environment Step I : Import the encrypted HSPICE sub-circuit definition into ADS. From the ADS main window menu, choose File->Import From the Import dialog box, click on the More Options button to specify the netlist import options. Using the Import Netlist Options dialog box, specify: HSPICE for the Input Netlist Dialect ADS Schematic for the Translated Output Format Page 20
Encrypted HSPICE Simulation in ADS Environment Select HSPICE netlist on the Import dialog box This will create and open an ADS design with interfacing pins and an HSPICE_INCLUDE component. The HSPICE_INCLUDE component instructs the simulator to treat this sub-circuit as an encrypted sub-circuit Page 21
Encrypted HSPICE Simulation in ADS Environment Step II : Build your circuit using the imported encrypted HSPICE. Note that the name of this sub-circuit will be the same name as the encrypted HSPICE netlist file. For the transient controller use the HS_Tran controller. Note that this is different than the regular ADS transient controller. Page 22
Digital Source in ADS 2006 Update 2 Features Five distinct modes of supplying digital data Maximal length LFSR User defined LFSR Explicit bit sequence File based bit sequence External trigger mode Familiar waveform description parameters Three distinct types of transition edge shaping Five built-in transition duration standards Differential voltage output Differential external trigger (if needed) Choice of %- or db-based de-emphasis for equalization Support for pre-emphasis over fractional bit periods Random jitter behavior on demand Up to three distinct sources of periodic jitter on demand Three choices of period jitter waveforms Page 23
Digital Source in ADS 2006 Update 2 Total Jitter = Random Jitter + Σi=1,2,3 Periodic Jitter [i] Page 24
Digital Source in ADS 2006 Update 2 Mode = Maximal Length LFSR, RegisterLength = 4 Mode = Explicit Bit Sequence, BitSequence = 101100 15-bit sequence Mode = Bit File, BitFile = data/prbs.txt Mode = External Trigger, VtriggerThreshold = 0.7 V Mode = User Defined LFSR, Taps = 1010, Seed = 1010 7-bit sequence, with initial settling time Page 25
Digital Source in ADS 2006 Update 2 Vlow, Vhigh DeEmphasisMode, DeEmphasis PreEmphasisSpan = 1.0 DeEmphasisMode= %, DeEmphasis=30 PreEmphasisSpan Page 26
Digital Source in ADS 2006 Update 2 1/BitRate = BitInterval BitRate, FallTime BitRate, RiseTime TransitionStd Page 27
BER Signal Integrity Roadmap Short term Provide powerful jitter generation and analysis capability in ADS Accurately predict bathtub/ber performance 120 100 500 400 Separate out jitter components 80 60 40 20 RJPJHist 300 200 TJHist 100 0 0 1.0E-11 8.0E-12 6.0E-12 4.0E-12 2.0E-12 0.0-2.0E-12-4.0E-12-6.0E-12-8.0E-12-1.0E-11 indep(rjpjhist) 1.0E-11 8.0E-12 6.0E-12 4.0E-12 2.0E-12 0.0-2.0E-12-4.0E-12-6.0E-12-8.0E-12-1.0E-11-1.2E-11 indep(tjhist) Composite Histogram DDJ Composite Histogram 500 1.0 400 0.8 300 0.6 200 DDJHist RJPJHist TJHist 0.4 DDJRHist DDJFHist DDJHist 100 0.2 Q-Scale Bathtub Plot Data and Modeled Bathtub Curve 0 m1 0.0 0 1E-1 4E-1 1.0E-11 8.0E-12 6.0E-12 4.0E-12 2.0E-12 0.0-2.0E-12-4.0E-12-6.0E-12-8.0E-12-1.0E-11-1.2E-11 6E-13 4E-13 2E-13 0-2E-13-4E-13-6E-13-2 m1 UI= 0.027 BTMdl=5.030E-5 1E-11 indep(tjhist) indep(rjpjhist) indep(ddjhist) indep(ddjhist) indep(ddjfhist) indep(ddjrhist) -4-6 1E-21 Q(x) -8 1E-31-10 -12 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 UI UI Page 28
Comparison of ADS Simulation vs. EZJit+ TJH is t TJ Histogram 1.5E4 1.0E4 5.0E3 0.0-6 -4-2 0 2 4 6 8 Time, psec RJPJHis t 300 250 200 150 100 RJPJ Histogram 50 0-4 -2 0 2 4 6 8 Time, psec 3 Composite DDJ Histogram 1.5E4 Composite Histogram DDJRHis t DDJFHist DDJHist 2 1 DDJHis t TJ Hist RJPJHist 1.0E4 5.0E3 0-600 -400-200 0 200 400 600 800 Time, fsec 0.0-6 -4-2 0 2 4 6 8 Time, psec Page 29
Comparison of ADS Simulation With EZJit+ TJHist 1.5E4 1.0E4 5.0E3 TJ Histogram 0.0-6 -4-2 0 2 4 6 8 10 Time, psec RJPJHist 300 250 200 150 100 RJPJ Histogram 50 0-6 -4-2 0 2 4 6 8 Time, psec 2.0 Composite DDJ Histogram 1.5E4 Composite Histogram DDJRHis t DDJFHist DDJHist 1.5 1.0 0.5 DDJHist TJHist RJPJHist 1.0E4 5.0E3 0.0-600 -400-200 0 200 400 600 Time, fsec 0.0-6 -4-2 0 2 4 6 8 10 Time, psec Page 30
A nice complementary full 3D EM simulator to Momentum in ADS at half of the price! EMDS for ADS Key Features: Use directly from ADS Layout New, user-friendly 3D pre-viewer Parameterized EM components for circuit co-simulation/co-optimization Include simulation of bond wires & dielectric bricks (finite dielectrics) Momentum-like usage and flow View currents, EM fields & radiation View results with ADS powerful data display Includes 64-bit simulation capability Multi-mode impedance & propagation constants overcomes single mode modeling limitation Page 31
Q & A Demo Page 32
Today s Highlight Accurate Transient Simulation at Gigabit/s Data Rate Demonstrate breakthrough convolution simulation technology with real world example System Level Simulation and Verification Using ADS Discuss the serial link simulation flow in ADS and validate simulation flow by comparing with measured data Designing a Transparent Via Demonstrate a simple yet robust methodology to evaluate design tradeoff for a transparent via Page 33
For more information about Agilent EEsof EDA, visit: www.agilent.com/find/eesof Agilent Email Updates www.agilent.com/find/emailupdates Get the latest information on the products and applications you select. Agilent Direct www.agilent.com/find/agilentdirect Quickly choose and use your test equipment solutions with confidence. www.agilent.com For more information on Agilent Technologies products, applications or services, please contact your local Agilent office. The complete list is available at: www.agilent.com/find/contactus Americas Canada (877) 894-4414 Latin America 305 269 7500 United States (800) 829-4444 Asia Pacific Australia 1 800 629 485 China 800 810 0189 Hong Kong 800 938 693 India 1 800 112 929 Japan 0120 (421) 345 Korea 080 769 0800 Malaysia 1 800 888 848 Singapore 1 800 375 8100 Taiwan 0800 047 866 Thailand 1 800 226 008 Europe & Middle East Austria 0820 87 44 11 Belgium 32 (0) 2 404 93 40 Denmark 45 70 13 15 15 Finland 358 (0) 10 855 2100 France 0825 010 700* *0.125 /minute Germany 01805 24 6333** **0.14 /minute Ireland 1890 924 204 Israel 972-3-9288-504/544 Italy 39 02 92 60 8484 Netherlands 31 (0) 20 547 2111 Spain 34 (91) 631 3300 Sweden 0200-88 22 55 Switzerland 0800 80 53 53 United Kingdom 44 (0) 118 9276201 Other European Countries: www.agilent.com/find/contactus Revised: March 27, 2008 Product specifications and descriptions in this document subject to change without notice. Agilent Technologies, Inc. 2008