Data Supply Voltage Reduction Sche for Low-Power AMOLED Displays Hyoungsik Nam and Hoon Jeong This paper donstrates a new driving sche that allows reducing the supply voltage of data drivers for lowpower active matrix organic light-itting diode (AMOLED displays. The proposed technique drives down the data voltage range by %, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 7%. ecause the gate voltage of a driving thin film transistor covers the same range as a conventional driving sche by means of a level-shifting sche, the low-data supply sche achieves the equivalent dynamic range of OLED currents. The average power consumption of data drivers is reduced by 6% over 4 test images, and power consumption is kept below %. Keywords: Data supply voltage reduction, low-power, level-shifting, AMOLED. I. Introduction Liquid crystal display (LCD has become the main display technology used in such consumer products as mobile phones, notebook PCs, monitors, and TVs. However, the market share of active matrix organic light-itting diodes (AMOLEDs has been significantly on the rise in the arena of small display applications, including mobile phones, and is expected to expand its domain into TV applications on the back of wide color gamut, slim and light design, high contrast ratio, fast response time, and the like []. As for AMOLED displays bodied in all consumer electronics, the industry may have to eventually apply lowpower technologies to abide with stricter legislation regarding the power consumption of electronic products [], [3]. So far, several power reduction techniques for AMOLED displays have been put forth, including OLED efficiency enhancent [4], through-current reduction in integrated panel circuitries [], and the RGW pixel format [6]. However, reducing the analog supply voltage of data drivers for low-power AMOLED displays has yet to be reported upon. ecause the power consumption of data drivers makes a big impact on the highresolution and high-frame-rate AMOLED displays for TV applications like LCDs [7], a low-power technique for data drivers is indispensable. II. Data Supply Voltage Reduction Sche Manuscript received Mar., ; revised June 8, ; accepted June,. This research was supported by National Research Foundation of Korea Grant funded by the Korean Government (KRF -39. Hyoungsik Nam (phone: +8 96 9, hyoungsiknam@khu.ac.kr and Hoon Jeong (hjeong@tftlcd.khu.ac.kr are with the Department of Information Display and Advanced Display Research Center, Kyung Hee University, Seoul, Rep. of Korea. http://dx.doi.org/.48/etrij...39 The AMOLED pixel circuit that has been suffering from the nonuniformity probl should compensate the variation on the threshold voltage of a driving thin-film transistor (TFT. In past research, the nonuniformity compensation has been performed by voltage modulation, current programming, and digital ETRI Journal, Volume 34, Number, October Hyoungsik Nam and Hoon Jeong 77
is Data from to Data from to / Digital circuits Analog circuits P P Digital circuits Analog circuits A A C ST C TH P 3 C ST C TH P 3 VDD / I VDD P P 4 Data driver P P 4 EVSS Data driver D D Fig.. AMOLED pixel circuits and timing diagrams: (a conventional circuit with data voltage driven at and (b proposed circuit with data voltage driven at /. I CON (a / P P 6 init P 7 EVSS (b data smp init Sampling Compensation 3 Emission 3 V DATA Initialization Sampling 3 Compensation 4 Emission 3 4 RV V DATA DS data V DS = or / driving sches [8]-[]. One of the most widely used methods is the voltage modulation circuit depicted in Fig. (a []. Only p-channel poly-silicon TFTs have been ployed on account of cost and hot carrier issues. The operation is divided into three periods: sampling, compensation, and ission. Whereas P operates at the saturation region, the other TFTs (P, P 3, P 4 are in use at the triode region for switching. During the sampling period, P and P 3 are turned on and P 4 is turned off. ecause the current path to an OLED (D is cut off, there is no light output. Node A is charged through the data line at the supply voltage (, and node, which is the gate terminal of P, is settled at V TH, where V TH is the threshold voltage of P. As a result, the voltage across C TH (V A becomes V TH. In the compensation period, P 3 is turned off and the target data voltage (V DATA is applied via the data line to node A. Since node is floating, the gate voltage of P is set as V DATA V TH. In the ission period, P and P 3 are turned off and P 4 is turned on. The resulting current of D (I CON is described as (, which is independent of V TH : βp ICON = ( V VTH βp = ( V V V β ( V DATA TH TH P = DATA. ( Our proposed low-supply sche modifies the conventional AMOLED pixel circuit of Fig. (a into the circuit of Fig. (b with three additional switching TFTs (P, P 6, P 7, which might affect the pixel size and brightness, to reduce the power consumption of data drivers. The operation is divided into four periods: initialization, sampling, compensation, and ission. Particularly, the data signal is provided at the half range from to /, which leads to a % voltage reduction of data drivers analog supply. As the maximum possible swing magnitude decreases by % and the peak power consumption is proportional to its square, a substantial power consumption reduction of 7% can be achieved at the maximum. The operation is as follows. In the initialization period, node is connected to EVSS through P 7 to ensure that P is turned on at the diode connection at the following sampling period. During the sampling period, the source of P is connected to / through P 6 and the voltage of node (V reaches to / VTH. When V DS is defined as the data signal at the sampling period, the voltage across C TH (V A is expressed as VA = VDS + VTH. ( In a compensation period, the target data voltage (RV DATA of the reduced voltage range from to / is provided to node A, and V is modulated into RVDATA V A as (3. Consequently, V obtained by level-shifting RV DATA by / V TH when V DS is and by V TH when V DS is /: 78 Hyoungsik Nam and Hoon Jeong ETRI Journal, Volume 34, Number, October
/ V DATA V DS = V V TH / V TH Source current (A 3 4 W/L=4 µm/ µm V DS = V V DS =. V 6 7 8 9 V DS = / V TH Fig.. Level-shifting at V according to V DS. V = RV V = RV V + / V DATA A DATA DS TH RVDATA VTH + /, VDS =, = RV V, V = /. DATA TH DS (3 The ensuing V can cover the full range of from VTH to V TH by programming V DS with two levels of and / even at the half analog supply of /, as explained in Fig.. As a consequence, the uniform OLED current (I of the equivalent dynamic range is obtained as (4, which is independent of V TH : βp I = ( V VTH β,, ( P RVDATA VDS = = βp ( RVDATA, VDS =. (4 On the other hand, because the proposed sche covers two different voltage regions by level-shifting through C TH, any errors on the stored voltage across C TH can degrade the image quality. However, this issue can be resolved by ploying separate data mapping tables for two different regions. III. Simulation Results. Circuit Simulation The proposed low data voltage driving sche is verified by conducting Simulation Program with Integrated Circuit Emphasis (SPICE simulation with parameters extracted from fabricated p-channel poly-silicon TFTs. The simulated transfer characteristic of the p-channel TFT is plotted in Fig. 3. The mobility and threshold voltage are 8 cm /Vs and.6 V, respectively. 3 8 6 4 4 6 Gate-source voltage, V GS (V Fig. 3. Simulated transfer characteristic of p-channel TFT. For the proposed pixel circuit, the size of a driving TFT is μm/ μm, the size of all the other switching TFTs is 4 μm/ μm, is V, EVSS is V, C ST is. pf, and C TH is. pf. Figure 4(a shows the waveforms of control signals, and Figs. 4(b and 4(c present the voltage waveforms of nodes A and in the two cases of V DS = V and V DS =/= V. Figure 4(b shows that when V DS is equal to V, the voltage of node successfully reaches a higher level than / by level-shifting through C TH. Figure plots the gate voltage of a driving TFT (V regarding VDATA and V DS. Whereas the data voltage has the V range, the range of V is doubled to around V, resulting in the equivalent dynamic range of the OLED current. Finally, Fig. 6 presents the OLED current characteristics of a proposed pixel circuit at the threshold voltage variation of ±.3 V.. Power Evaluation ecause the data lines can be approximated as capacitive loads, the dynamic power consumption of data drivers is expressed by summing the square terms of the output voltage swings [7]. For the conventional sche of Fig. (a, each pixel has two transitions from to V DATA and from V DATA to. As a result, the dynamic power consumption of conventional data drivers (DP CON is described as DPCON = k ( VDATA ( i, j, ( i= j= where k is the coefficient, 3N is the total number of column lines, M is the total number of row lines, and V DATA (i, j is the target data voltage of an i-th column and j-th row subpixel. For the proposed sche, the power can be estimated from ETRI Journal, Volume 34, Number, October Hyoungsik Nam and Hoon Jeong 79
(V 3 3 4 4 (V 3 3 4 4 init (V 3 3 4 4 (V 3 3 4 4 Time (μs 9 8 7 6 4 Node (V Node A (V RV DATA = 4 V 3 V DS = V 3 4 3 3 4 4 Time (μs (b 9 8 7 V DS = V 6 Node A (V RV DATA = 4 V 4 3 Node (V 3 4 3 3 4 4 Time (μs (c Fig. 4. Waveforms (a for control signals, (b for nodes A and at V DS = V, and (c for nodes A and at V DS = V. the data voltage swings as well. However, because the data voltage level of the sampling period is different according to the required V, the power estimation is accomplished by the more complicated method. Since the output luminance is proportional to the current, the normalized luminance of an i-th column and j-th row subpixel (L NO (i, j can be given as (6, where g(i, j is the gray level of an i-th column and j-th row subpixel in an 8-bit depth, γ is the gamma value of a display, and V MIN is the minimum voltage (a V OLED current (µa 8 6 4 V DS = V V DS = V 4 3 4 RV DATA Fig.. Plot of V with respect to RV DATA and V DS. 4 3 3 V DS = V RV DATA (V V TH =.3 V V TH =.6 V V TH =.9 V V DS = V 3 4 3 4 Fig. 6. Plot of OLED currents with respect to RV DATA and V DS at V TH variation of ±.3 V. level of V. Then, V (i, j and RV DATA (i, j are calculated with the gray level by (7 and (8: V L ( i j ( V (, i j gi (, j, = =, NO ( VMIN γ gi (, j = ( MIN V(, i j V, DATA γ (6 (7 V(, i j, V(, i j <, (, i j = V(, i j, V(, i j. The resultant squares of the voltage swing (DV (i, j at a (8 73 Hyoungsik Nam and Hoon Jeong ETRI Journal, Volume 34, Number, October
(a (b (c (d Fig. 7. Test patterns used to measure dynamic powers of data drivers: (a white (b black, (c H-line, and (d V-line. Normalized power (% 8 6 4 Patterns. DP NC DP NP White lock H-line V-line Fig. 8. Simulated power consumptions DP NC and DP NP depending on images displayed on conventional and proposed sches. given subpixel are estimated by considering the four cases as (9 to ( and the dynamic power consumption of the proposed sche (DP is achieved as their sum, shown in (3: When V ( i, j < & V ( i, j + <, DV (, i j = VDATA (, i j ; When V (, i j < & V (, i j+, ( DV (, i j = VDATA (, i j + ( VDATA (, i j ; When V (, i j & V (, i j + <, ( DV (, i j = ( VDATA (, i j + VDATA (, i j ; When V(, i j & V(, i j +, ( DV (, i j = V (, i j ; ( DATA (9 Fig. 9. 4 test images in use for evaluation. DP = k DV (, i j. (3 i= j= At the condition of V MIN = V, the normalized dynamic power consumption of conventional and proposed sches (DP NC, DP NP is defined as ( and (6 by means of the maximum dynamic power (DP MAX of (4: MAX (, DP = k = 6 knm ( DP DP i= j= ( VDATA ( i, j CON i= j= NC = = DPMAX 3 NM ( DP DV ( i, j DP i= j= NP = = DPMAX 6 NM (., (4 ( (6 First, we measure DP NC and DP NP according to the four test images shown in Fig. 7. In the conventional sche, the voltage swings become the maximum and minimum values at the white and black patterns, respectively. Thus, we can expect the white and black patterns to show the largest and smallest amount of dynamic power consumption of DP MAX and. Since the H-line and V-line patterns contain the same number of white and black pixels, the H-line and V-line patterns lead the medium power consumption of DP MAX /. However, in the proposed syst, the white and black patterns show the lower maximum power of DP MAX /4, and the H-line and V-line patterns consume DP MAX /8 and DP MAX /4, respectively. The simulation results of the four test patterns are presented in Fig. 8. When the displayed images include more low gray pixels, DP NC can be smaller than DP NP. However, the proposed method guarantees that any image consumes less than DP MAX /4. ETRI Journal, Volume 34, Number, October Hyoungsik Nam and Hoon Jeong 73
Table. Measured power consumption. Power reduction Test image APL DP NC (% DP NP (% (DP NC DP NP/DP NC 7.36.3.7 76.78 9.6.9 3 96.4.96.6 4 98 6.8.97.63 8.8 8.7.6 6 7 8. 6.8.76 7 4 6.97 4.49.74 8 6. 7..73 9 9..9.88 9. 3.4.8 9 3.7 6.33. 37.74 4.8.87 3 8.49 7.7.6 4 89 4.43 7.7.46 6 6.67.. 6 6.3 4.93.7 7 76.8 9..7 8 67 8. 9.8. 9. 4.9.76 7.76.3.7 4.7 4.4.79 7 8.68 4.9.74 3 9. 7..63 4 9.6 6.7.67 Average -.4 6.89.6 We evaluate the power consumption of the 4 real picture images, as shown in Fig. 9. Table shows the average pixel levels (APLs, the normalized power consumption, and the power reduction ratios for test images. Particularly, in image 8, DP NP is larger than DP NC because most of its pixels are located in the low gray region. The proposed sche establishes a substantial average power reduction of 6% for the 4 images. IV. Conclusion Our low data supply sche was established by reducing the data voltage range by half. Even at the reduced data voltage range, the full dynamic range of an OLED current was achieved using level-shifting through a sampling capacitor according to the level of a data voltage in the sampling period. The feasibility of the proposed sche was verified by SPICE. In addition, we showed that the power consumption is smaller than one-fourth of the maximum power in the conventional method over any displayed images. References [] S.S. Kim, The Next ig Thing in Displays, keynote presentation, SID,. [] J. Souk and S. Whangbo, Green Technology in LCDs, Information Display, vol. 6, no. &, Nov./Dec., pp. 4-7. [3] K. Teunissen and L.J. de OLDE, EcoDesign for TV Displays Information Display, Inf. Display, vol. 6, no. &, Nov./Dec., pp. -4. [4] J.Y. Lee, J.H. Kwon, and H.K. Chung, High Efficiency and Low Power Consumption in Active Matrix Organic Light Emitting Diodes, Organic Electron., vol. 4, no. -3, Sept. 3, pp. 43-48. [] S.H. Jung et al., A New Low-Power pmos Poly-Si Inverter for AMDs, IEEE Electron Device Lett., vol. 6, no., Jan., pp. 3-. [6] H. Kanno et al., Reduction in Power Consumption for Full-Color Active Matrix Organic Light-Emitting Devices, Jpn. J. Appl. Phys., vol. 4, no. 3, Sept. 6, pp. L947-L9. [7] H. Nam and S.-W. Lee, Low-Power Liquid Crystal Display Television Panel with Reduced Motion lur, IEEE Trans. Consum. Electron., vol. 6, no., May, pp. 37-3. [8] N. Komiya et al., Comparison of Vth Compensation Ability among Voltage Programming Circuits for AMOLED Panels, Proc. th Int. Display Workshops, 3, pp. 7-78. [9] T. Sasaoka et al., A 3.-inch AM-OLED Display with Top Emitting Structure and Adaptive Current Mode Programmed Pixel Circuit (TAC, Soc. Inf. Display (SID Symp. Digest,, pp. 384-386. [] T. Inukai et al., 4.-in. TFT-OLED Displays and a Novel Digital Driving Method, Soc. Inf. Display (SID Symp. Digest,, pp. 94-97. [] R.M.A. Dawson et al., Design of an Improved Pixel for a Polysilicon Active-Matrix Organic LED Display, Soc. Inf. Display (SID Symp. Digest, 998, pp. -4. Hyoungsik Nam received his S, MS, and PhD in EECS from the Korea Advance Institute of Science and Technology (KAIST, Daejeon Rep. of Korea, in 996, 998, and 4. He was involved in several projects of the VDSL transceiver, PLL/DLL, and LDIs for portable devices. He joined Samsung Electronics as a senior engineer in, where he worked on Active-Matrix Liquid- Crystal Displays in the area of motion picture quality improvent, new image signal interfaces, the compression algorithm, low-power 73 Hyoungsik Nam and Hoon Jeong ETRI Journal, Volume 34, Number, October
technology, and low-cost display solutions for LCDs. He was in charge of the development of the world s first clock bedded intra panel interface, AiPi TM. He is currently an assistant professor in the Department of Information Display at Kyung Hee University, Seoul, Rep. of Korea. His current research interests are low-power technologies, integrated circuits, and signal/user interfaces for flat panel displays. He has been active with SID and IMID as a mber of the Program Committee. Hoon Jeong received his MS in electronic engineering from Kyungpook National University, Daegu, Rep. of Korea, in 999. etween 999 and, at LG Displays Co. Ltd, he was in charge of developing highresolution mobile applications for low tperature polycrystalline silicon TFTs. Since, he has been pursuing his PhD at Kyung Hee University, Seoul, Rep. of Korea. His current research is focused on oxide TFTs, LTPS, and AMOLED display. ETRI Journal, Volume 34, Number, October Hyoungsik Nam and Hoon Jeong 733