LSI Course Code 3361104 GUJARAT TECHNOLOGICAL UNIERSITY, AHMEDABAD, GUJARAT COURSE CURRICULUM COURSE TITLE: LSI (COURSE CODE:3361103) Diploma Programme in which this course is offered Semester in which offered ELECTRONICS & COMMUNICATION ENGINEERING SIXTH 1. RATIONAL E: Digital Integrated circuits are integral part of devices starting from small toys to complex computer systems including personal digital assistants, mobile phones and Multimedia agents. Students must acquire the basic knowledge of LSI & programming through HDL for design and development of FPGA for ASIC chips.. COMPETENCY: The course content should be taught and implemented with the aim to develop different types of skills to make students able to acquire following competency. 1. Program and Implement Digital Logic in FPGA/ ASIC. 3. COURSE OUTCOMES The students should be able to acquire different learning outcomes in all three domains to demonstrate following course outcomes i. Gain the basic knowledge of LSI ii. Understand CMOS circuits iii. Develop Simple HDL Programs iv. Implement & test basic Digital Logic 4. TEACHINGAND EXAMINATION SCHEME Teaching Scheme (InHours) Total Credits (L+T+P Examination Scheme Theory Marks Practical Marks Total Marks L T P C ESE PA ESE PA 4 0 6 70 30 0 30 150 Legends:L- Lecture;T- Tutorial/TeacherGuidedStudentActivity;P - Practical; C -Credit;ESE- EndSemesterExamination;PA ProgressiveAssessment 1
LSI Course Code 3361104 5. COURSE DETAILS Unit Unit I. Introduction of Digital System and MOS Transistor Unit II MOS Inverters Unit III MOS Circuits Major Learning Outcomes (in cognitive domain) 1a. Overview of design Methodologies & Detail of Y Chart. 1b Describe Different Domain & Define different terms regarding design Hierarchy. 1c Introduction to LSI Design Style. 1d Explain Energy Band Diagram & Structure of MOS 1e Explain effect of external bias on two terminal MOS device with energy Band Diagram. 1f Explain Formation of Channel & Know Different Symbols Of MOSFET. 1g To Understand Gradual a b c d e f 3a Channel Approximation To Understand TC with OL, OH, IL,IH, TH& Noise Margins Explain operation of resistive load inverter without mathematical derivation of OL, OH, IL,IH, TH. (Write Only Final Equation) Describe inverter circuit with saturated & Linear Enhancement and Depletion type load Compare Enhancement load NMOS & Depletion Load NMOS Explain CMOS Inverter with Different Operating Modes of nmos & pmos transistor. Understand Cascaded stages Explain Two input NAND & NOR Gate with depletion NMOS load. Topics and Sub-topics 1.1 LSI Design Flow using Y chart 1. Design Hierarchy-Structural Decomposition in the physical (geometrical) domain. 1.3 FPGA, Gate Array Design, Standard Cell Based Design, Full Custom Design. 1.4 The MOS structure 1.5 The MOS system under external bias 1.6 Structure and operation of MOSFET transistor 1.7 MOSFET current- voltage Characteristics.1 Introduction. Resistive load Inverter..3 Inverter with n-type MOSFET Load.3.1 Enhancement load NMOS.3. Depletion Load NMOS.4 Comparison between NMOS structure.5 CMOS Inverter.5.1 Circuit operation and description.6 Cascaded CMOS Inverter stages 3.1 Combinational MOS Logic Circuits.
LSI Course Code 3361104 Unit-I Introduction to HDL 1. Unit- HDL Programming 3b 3c 3d 3e 3f 4a 4b Explain Two input NAND & NOR Gate using CMOS logic. Describe AOI & OAI Logic. Design XOR function Describe SR latch circuit Explain Clocked latch and Flip-Flop circuit Introduction to HDL Programming methodology Develop HDL Programs related to basic logic gates. 4c Develop HDL Programs related to Fundamental Arithmetic operations. 5a Develop HDL Programs related to Combinational circuits. 5b Develop HDL Programs related to Sequential circuits. 3. CMOS logic circuits 3.3 Complex logic circuit 3.4 Sequential MOS circuit 4.1 Data flow, behavioural, structural 4. Logic operations viz. AND,OR,NOR,NAND,NOT,EXOR, EXNOR etc. 4.3Adder and Subtractor. 5.1 Combinational circuits- Multiplexer and De multiplexer, Decoder and Encoder. 5. 4 bit Parallel Adder. 5.3 Parity Generator and parity checker. 5.4 Basic sequential circuits- SR, D Latch,RS,T, JK Flip flop 5.5 Parallel input Parallel output Shift Register, Up Counter, Down Counter NOTE: All mathematical expression and derivations are only for References. 6 SUGGESTED SPECIFICATION TABLE WITH HOURS & MARKS (THEORY) Unit I Unit Title Introduction of Digital System and MOS Transistor Teach ing Hours Distribution of Theory Marks U A Level Level R Level Total Marks 8 4 4 16 II MOS Inverters 1 4 14 III MOS Circuits 1 3 5 4 18 I Introduction to HDL 1 1 3 1 HDL Programming 1 1 3 10 Total 56 11 17 14 70 Legends: R = Remember; U= Understand; A= Apply and above levels (Bloom s revised taxonomy)
LSI Course Code 3361104 Note: This specification table shall be treated as only general guideline for students and teachers. The actual distribution of marks in the question paper may vary from above table. 7 SUGGESTED LIST OF EXERCISES/PRACTICAL The practical/exercises should be properly designed and implemented with an attempt to develop different types of skills so that students are able to acquire the competency. Following is the list of experiments for guidance. NOTE:- Following are the minimum experiences required, but the Faculty can do more experiences if possible. Sr No 1 Unit No. I Practical Exercises To study HDL entities and coding styles. Approx Hours. Required 3 4 5 6 7 8 9 10 11 1 13 14 15 16 17 18 19 0 1 I I I I I I I To simulate the Basic logic gates using HDL. To simulate the Universal logic gates using HDL To simulate X-OR and X-NOR logic gates using HDL To simulate Half Adder using HDL To simulate Full Adder using HDL To simulate Half Substracter using HDL To simulate Full Substracter using HDL To simulate 4 : 1 mux using HDL To simulate 1 : 4 de-mux using HDL To simulate 3 : 8 decoder using HDL To simulate 8 : 3 encoder using HDL To simulate SR flip-flops using HDL To simulate D flip-flops using HDL To simulate JK flip-flops using HDL To simulate T flip-flops using HDL To simulate 4 bit parallel adder using HDL To simulate 4 bit Up counter using HDL To simulate 4 bit Down counter using HDL To simulate any three above listed programs using Structural coding method Hardware implementation of all above listed program 4 8 SUGGESTED LIST OF STUDENT ACTIITIES Following is the list of proposed student activities like: 1. Survey Current requirement for Hardware/ Chip at your Company/ Department/ Institute.. Identify basic Circuits etc. 3. Project- Build a small ASIC for your Home /Community.
LSI Course Code 3361104 4. Enhance features and components of your ASIC by providing more Hardware. 5. Industrial visit. 9. SUGGESTED LEARNING RESOURCES ( A ) List of Books: Sr No Title of Book Author Publication 1 CMOS DIGITAL INTEGRATED CIRCUITS Sung Mo Kang TMH Introduction to LSI Circuits and Systems. Uyemura J.P. WILEY INDIA PT. LTD. 3 LSI DESIGN Das Debaprasad OXFORD 4 5 6 7 8 LSI DESIGN Theory and Practice Circuit design with HDL HDL Modelling of systems HDL Programming by Example HDL design ij ikrant,er. Syal Nidhi Pedroni.A. Znawabi Perry Douglas L. Bhaskar J LAXMI PUBLICATION S PT. LTD. PHI TMH MGH Pearson ( B ). List of Major Equipment/Materials i. Computer systems ii. LSI Trainer Kits iii HDL Simulator Software ( C ) List of Software/Learning Websites i. QUARTUS-II-ALTERA EAL ERSION ii. ModelSim HDL simulator for use by students in their academic coursework. iii. ISE Simulator iv. http://www.youtube.com/watch?v=9snr3m3cim4 10. INSTRUCTIONAL STRATEGY i. Show ideo/ Animation film explaining LSI Design which are available on internet. 11. COURSE CURRICULUM DEELOPMENT COMMITTEE Faculty Members from Polytechnics 1. Prof. K N aghela Sr. Lecturer in EC, Govt. Poly, Ahmedabad. Prof. U BUCH Sr. Lecturer in EC, Govt. Poly for Girls, Surat 3. Prof. J D Chauhan Lecturer in EC, B& B Poly, Nagar
LSI Course Code 3361104 4. Prof. L J ora Lecturer in EC,Govt. Poly, adnagar Coordinator and Faculty Members from NITTTR, Bhopal 1. Dr. Anjali Potnis, NITTTR, bhopal