Ilmenau, 9 Dec 206 Testing and programming PCBA s JTAG Technologies
The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge costs ( rule of ten applies) The "rule of ten" specifies that it costs 0 times more to find and fix a defect at the next stage of assembly. Important to find defects in an early stage. 2 JTAG Technologies
Horror case (dd. Oct, 206) 3 JTAG Technologies
Each assembly step adds possible defects Apply solder paste 4 JTAG Technologies
Each assembly step adds possible defects Pick and place components 5 JTAG Technologies
Each assembly step adds possible defects Soldering in reflow oven 6 JTAG Technologies
Important statement Simplified statement: If all components on a PCB are soldered correctly - the board should work. Assuming: Design is right Components are OK (0ppm - 25ppm) Conclusion: Testing the interconnections between the components should be sufficient to detect a great deal of bad boards. 7 JTAG Technologies
Defect analysis on real production data Tombstoning Others 6% 3% 26% Shorts incl. SA/SA0 Component defect 7% Careless placement 0% Upside down 9% 2% Not placed 7% Opens 8 JTAG Technologies
Commonly used Testmethods Structural Test Checks the structure of the board (component placement, soldering, value etc.) Functional Test Checks the functionality of the board 9 JTAG Technologies
AOI, Automated Optical Inspection Tombstoning 0 JTAG Technologies
AXI, Automated X-ray Inspection JTAG Technologies
FP, Flying Probe 2 JTAG Technologies
ICT, In Circuit Test Unit under test, UUT Bed of nails Test fixture 3 JTAG Technologies
FT, Functional Test Rack and Stack Instrumentation controlled by a computer and dedicated software. Instrumentation: Programmable Power Supplies Generator Oscilloscope Waveform-analyzer Switching matrix etc. 4 JTAG Technologies
Pros & Cons Functional Test Functional Test Checks the functionality of the board - Big problem if the core is not running - Manual creation of the tests (error prone to SW-bugs) - Very difficult to diagnose, doesn t pinpoint to the exact location of the problem - Requires highly skilled engineers to find the problem - Time consuming - Expensive + @Speed test 5 JTAG Technologies
Pros & Cons Structural Test Structural Test Checks the structure of the board (interconnects, device orientation, device values etc.) - No @Speed test + Automatic generation based on the Netlist + Low cost to generate testprogram (use ATPG) + Pinpoints to the exact location of the problem if sufficient testpoints are available 6 JTAG Technologies
Interconnect test on a PCBA with BGA s The probes require a minimum clearance, and a typical spring force of.5n per pin to ensure good contact. 7 JTAG Technologies
Boundary-scan provides accessibility What is Boundary-scan and how does it work Official standard: IEEE Std. 49. 8 JTAG Technologies
Boundary-scan architecture The Boundary-scan architecture is a standard implementation in many devices, such as µcontrollers, DSPs, FPGAs etc.. I/0 I/0 I/0 I/0 I/0 I/0 Core I/0 I/0 I/0 9 JTAG Technologies
Boundary-scan architecture Additional Testlogic and pins have been added to the device I/0 I/0 I/0 I/0 I/0 BSR Boundary-Scan Register I/0 I/0 Core I/0 I/0 TDI Bypass TDO TMS TCK TRST Optional Instruction register Controller 20 JTAG Technologies TDI Test Data In TDO Test Data Out TMS Test Mode Select TCK Test Clock TRSTTest Reset (optional)
Example with two Boundary-scan devices Core Core TDI BP TDO TDI BP TDO IR IR Controller Controller TMS TCK 2 JTAG Technologies
Goal is to test the interconnections Core Core TDI BP TDO TDI BP TDO IR IR Controller Controller TMS TCK 22 JTAG Technologies
TDI-TDO chains can be cascaded Core Core TDI BP IR Chains cascaded BP IR TDO Controller Controller TMS TCK 23 JTAG Technologies
Step : Define Testvector Core Core TDI BP BP TDO IR IR Controller Controller TMS TCK 24 JTAG Technologies
Step 2: Shift-in Testvector IC IC2 Core Core TDI BP IR TDO TDI BP IR TDO Controller Controller SHIFT TMS TCK Send multiple SHIFT commands to shift the testvector into the appropriate BSR cells. 25 JTAG Technologies
Step 3: Send UPDATE command TDI IC Core BP IR TDO TDI IC2 Core BP IR TDO Controller Controller UPDATE TMS TCK Send the UPDATE command, the testvector is driven onto the corresponding pins of IC. If the pins are soldered correctly the values on the pins will also appear on the nets. 26 JTAG Technologies
Step 4: Send CAPTURE command TDI IC Core BP IR 0 TDO TDI IC2 Core BP IR TDO Controller Controller CAPTURE TMS TCK The CAPTURE command senses the data on the pins and puts the values into the corresponding cells of IC2 27 JTAG Technologies
Step 5: Shift-out captured data IC IC2 Core 0 Core TDI BP IR TDO TDI BP IR TDO Result 0 Controller Controller SHIFT TMS TCK The repeated SHIFT command shifts-out the captured vector (Result). 28 JTAG Technologies
Compare Result with Expected IC IC2 Core 0 Core Expected TDI BP IR TDO TDI Result BP TDO 0 IR Controller Controller TMS TCK 29 JTAG Technologies
Diagnose the outcome IC IC2 Core 0 Core Expected TDI BP IR TDO TDI BP IR TDO Result 0 Controller Controller TMS TCK Mismatch caused due to an open pin 30 JTAG Technologies
Faultdetection With the aid of Intelligent testvectors Opens Shorts SA and SA0 problems are easily detected The Intelligent testvectors are based on an Enhanced Binary Search principle. (Minimum set of Testvectors with a Maximum Testcoverage) 3 JTAG Technologies
Compare and Diagnose Errors are shown in inverse video. In this case the result was a 0 however a was expected. and 0 are for Input H, L and Z are for output The diagnostics pinpoints to the exact error locations 32 JTAG Technologies
Testing the connectivity of Non-Bscan components Bscan Non-Bscan Bscan TDI TDO Boundary-scan chain 33 JTAG Technologies
Testing connectivity of NAND Gate A B & Y TDI TDO Bscan A B Y 0 0 0 0 0 Boundary-scan chain 34 JTAG Technologies Bscan Use Truthtable to stimulate the inputs and sense the outputs of the NAND-gate using the Bscan cells. A model contains information about the Truthtable.
Testing connectivity of RAM ADD Bscan RAM DATA Bscan Ctrl TDI TDO Boundary-scan chain Stimulate the Add/Data/Ctrl pins to write and read data from the RAM. The information on how to read/write to the memory is described in a model. 35 JTAG Technologies
Testing connectivity of FLASH ADD Bscan FLASH DATA Bscan Ctrl TDI TDO Boundary-scan chain A FLASH model contains all the information on how to get access to the device. 36 JTAG Technologies
Programming external FLASH ADD Bscan FLASH DATA Bscan Ctrl TDI TDO Boundary-scan chain The Image file gets integrated into the Bscan patterns to program the FLASH. 37 JTAG Technologies
Testing connectivity I/O block and Connector Bscan Bscan I/O Connector LoopBack Connector TDI Boundary-scan chain TDO Use loopback connector to test the connectivity of the I/O block and Connector 38 JTAG Technologies
Testing connectivity I/O block and Connector Bscan Bscan I/O Connector External Bscan device/board TDI TDO Boundary-scan chain Use an external Bscan device/board with required # of I/O pins to get full access. 39 JTAG Technologies
Testing connectivity serial devices I2C, SPI etc. SDA SLC Bscan I2C Bscan TDI TDO Simulating the I2C protocol on SDA and SLC givess access to the I2C device The information on how to simulate the serial protocol is defined in a model. 40 JTAG Technologies
Programming via the JTAG interface We ve already seen that the Boundary-scan chain can be used for Programming an on-board Flash. Some devices use the JTAG interface to get direct access to the inside of the device for programming/debug purposes. 4 JTAG Technologies
Programming FPGA s etc. Logic cells Interconnections JTAG Interface 42 JTAG Technologies
Programming FPGA s etc. JTAG Interface FPGAs use the JTAG interface to directly download the configuration file into the device. 43 JTAG Technologies
Programming FPGA s etc. JTAG Interface Fortunately, most of these these chips also have a Boundary-scan chain that provides direct access to the I/O pins and can be used for testing. 44 JTAG Technologies
Programming Embedded Flash Internal FLASH µcontroller Core JTAG Interface Many µcontrollers have internal flash that can be directly programmed via de JTAG interface 45 JTAG Technologies
Warning Not all devices with a JTAG interface are Boundary-scan compliant. JTAG interface JTAG interface For this type of devices a BSDL-file exists For this type of devices NO BSDL-file exists 46 JTAG Technologies
What is a BSDL-file The Boundary-Scan Description Language (BSDL) file is a model description of how the boundary-scan architecture is implemented in the device. The BSDL file is mandatory for the creation of Bscan applications. 47 JTAG Technologies
How to get BSDL files BSDL files can be downloaded from the suppliers websites Example: 48 JTAG Technologies
Demonstration 49 JTAG Technologies
Blockdiagram 50 JTAG Technologies
Full access via the TAP (Test Access Port) TAP 5 JTAG Technologies
JTAG Live Boundary-scan tools JTAG Live Studio is a complete Boundary-scan solution for testing, debugging and programming boards. 52 JTAG Technologies
JTAG Live Buzz JTAG Live Buzz provides an easy solution for debugging boards too crowded for traditional probing with scopes or logic analysers - what's more it's totally free. Buzz is ideal for electronics engineers and technicians to use in checking printed circuit boards for basic continuity and correct operation. Buzz simply uses the built-in pin access provided in boundary-scan (IEEE Std 49.) compliant devices to perform pin to pin continuity tests, drive output pins and can also sample pin activity on input pins FREE download on www.jtaglive.com 53 JTAG Technologies
Supported controllers 54 JTAG Technologies
v 55 JTAG Technologies