Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Summer 2016
State-Holding Elements Bistable Elements S Latch Latch Positive-Edge-Triggered Flip-Flop Flip-Flop with Enable Synchronous igital Logic The Synchronous Paradigm Shift egisters Counters Timing in Synchronous Circuits Flip-Flop Timing Timing in Synchronous Circuits Clock Skew
State-Holding Elements
Bistable Elements Equivalent circuits; right is more traditional. Two stable states: 0 1 1 0
A Bistable in the Wild This debounces the coin switch. Breakout, Atari 1976.
S Latch S S S 0 0 0 1 1 0 1 1
S Latch S 0 1 1 0 S S 0 0 0 1 1 0 Set 1 0 1 1 S Set
S Latch S 0 0 1 0 S S 0 0 Hold 0 1 1 0 Set 1 0 1 1 S Hold, State 1
S Latch S 1 0 0 1 S S 0 0 Hold 0 1 1 0 Set 1 0 0 1 eset 1 1 S eset
S Latch S 0 0 0 1 S S 0 0 Hold 0 1 1 0 Set 1 0 0 1 eset 1 1 S Hold, State 0
S Latch S 1 1 0 0 S S 0 0 Hold 0 1 1 0 Set 1 0 0 1 eset 1 1 0 0 Bad S Huh?
S Latch S 0 1 1 0 S S 0 0 Hold 0 1 1 0 Set 1 0 0 1 eset 1 1 0 0 Bad S Set
S Latch S 0 0 1 0 S S 0 0 Hold 0 1 1 0 Set 1 0 0 1 eset 1 1 0 0 Bad S Hold, State 1
S Latch S 1 1 0 0 S S 0 0 Hold 0 1 1 0 Set 1 0 0 1 eset 1 1 0 0 Bad S Huh?
S Latch S 0 0 X X S S 0 0 Hold 0 1 1 0 Set 1 0 0 1 eset 1 1 0 0 Bad S Undefined
S Latches in the Wild Generates horizontal and vertical synchronization waveforms from counter bits. Stunt Cycle, Atari 1976.
Latch C C inputs outputs C 0 X 1 0 0 1 1 1 1 0
A Challenge A simple traffic light controller. Want the lights to cycle green-yellow-red. C C Y C G oes this work?
C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 1 0 C C C M C S C transparent opaque
C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 1 0 C C C M C S C transparent opaque
C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 0 1 C C C M C S C transparent opaque opaque transparent
C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 0 1 C C C M C S C transparent opaque opaque transparent
C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 1 0 C C C M C S C transparent opaque transparent opaque transparent opaque
C M C S Positive-Edge-Triggered Flip-Flop C Master Slave 0 1 C C C M C S C transparent opaque transparent opaque opaque transparent opaque transparent
The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
The Traffic Light Controller: A second try Let s try this again with flip-flops. Y G Y G
The Traffic Light Controller with eset ESET Y G ESET Y G
The Traffic Light Controller with eset ESET Y G ESET Y G
The Traffic Light Controller with eset ESET Y G ESET Y G
The Traffic Light Controller with eset ESET Y G ESET Y G
The Traffic Light Controller with eset ESET Y G ESET Y G
The Traffic Light Controller with eset ESET Y G ESET Y G
Flip-Flop with Enable 0 1 E C C E 0 X 1 0 0 1 1 1 0 X X 1 X X E C What s wrong with this solution?
Asynchronous Preset/Clear PE CL PE CL
The Traffic Light Controller w/ Async. eset ESET PE CL PE CL Y PE CL G
The Synchronous igital Logic Paradigm Gates and flip-flops only INPUTS OUTPUTS Each flip-flop driven by the same clock STATE C L Every cyclic path contains at least one flip-flop CLOCK NEXT STATE
Cool Sequential Circuits: Shift egisters A 0 1 2 3 A 0 1 2 3 0 X X X X 1 0 X X X 1 1 0 X X 0 1 1 0 X 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0
Universal Shift egister L 3 2 0 0 1 0 3 2 1 1 1 0 3 2 2 2 1 0 3 2 3 3 1 0 S 1 S0 S 1 S 0 3 2 1 0 0 0 3 2 1 0 1 3 2 1 0 1 0 3 2 1 0 1 1 2 1 0 L S 1 S 0 Operation 0 0 Shift right 0 1 Load 1 0 Hold 1 1 Shift left
Cool Sequential Circuits: Counters Cycle through sequences of numbers, e.g., 00 01 10 11
The 74LS163 Synchronous Binary Counter
Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change t su
Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h
Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h Minimum Propagation elay: Time from clock edge to when might start changing t p(min)
Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h Minimum Propagation elay: Time from clock edge to when might start changing t p(min) t p(max) Maximum Propagation elay: Time from clock edge to when guaranteed stable
Timing in Synchronous Circuits C L t c t c : Clock period. E.g., 10 ns for a 100 MHz clock
Timing in Synchronous Circuits C L Sufficient Hold Time? t p(min,ff) t p(min,cl) Hold time constraint: how soon after the clock edge can start changing? Min. FF delay + min. logic delay
Timing in Synchronous Circuits C L t p(max,ff) Sufficient Setup Time? t p(max,cl) Setup time constraint: when before the clock edge is guaranteed stable? Max. FF delay + max. logic delay
2 Clock Skew: What eally Happens C L 1 2 Sufficient Hold Time? 1 t skew t p(min,ff) t p(min,cl) 2 arrives late: clock skew reduces hold time
2 Clock Skew: What eally Happens C L 1 2 Sufficient Setup Time? 1 t skew t p(max,ff) t p(max,cl) 2 arrives early: clock skew reduces setup time