Sequential Logic Reerences: Adapted rom: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles o CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian Pro. Kaushik Roy
Clocked Systems: Finite State Machines Inputs Combinational Logic Outputs Out = (In, State) Current state bits Next state bits Q D Registers Clock or clocks Registers serve as storage element to store past history Pro. Kaushik Roy
Clocked Systems: Pipelined Systems Inputs D Q D Q D Q Logic Logic Outputs Clock Registers Registers serve as storage element to capture the output o each processing stage Pro. Kaushik Roy
Storage Mechanisms Positive eedback Connect one or more output signals back to the input Regenerative, signal can be held indeinitely, static Charge-based Use charge storage to store signal value Need rereshing to overcome charge leakage, dynamic Pro. Kaushik Roy
Positive Feedback: Two Cascaded Inverters V i1 V o1 = V i2 V o2 V i2 = V o1 Pro. Kaushik Roy
Bi-Stability and Meta-Stability V i2 =V o1 A V i2 =V o1 A C C B B d V i1 =V o2 d V i1 =V o2 Gain larger than 1 ampliies the deviation rom C Gain less than 1 reduces the deviation rom A Pro. Kaushik Roy
SR-Flip Flop NOR-based SR lip-lop, positive logic Schematic Logic Symbol Characteristic table NAND-based SR lip-lop, negative logic Forbidden state Schematic Logic Symbol Characteristic table Pro. Kaushik Roy
JK- Flip Flop Schematic Logic Symbol Characteristic table Clock input to synchronize changes in the output logic states o lip-lops Forbidden state is eliminated, But repeated toggling when J = K = 1, need to keep clock pulse small < propagation delay o FF Pro. Kaushik Roy
Other Flip-Flops Toggle or T lip-lop Delay or D lip-lop Pro. Kaushik Roy
Race Problem A lip-lop is a latch i the gate is transparent while the clock is high (low) Signal can raise around when is high Solutions: Reduce the pulse width o Master-slave and edge-triggered FFs Pro. Kaushik Roy
Master-Slave Flip-Flop Either master or slave FF is in the hold mode Pulse lengths o clock must be longer than propagation delay o latches Asynchronous or synchronous inputs to initialize the lip-lop states Pro. Kaushik Roy
One-Catching or Level-Sensitive Q M Q S Pro. Kaushik Roy
Propagation Delay Based Edge-Triggered Depend only on the value o In just beore the clock transition Pro. Kaushik Roy
Edge Triggered Flip-Flop Pro. Kaushik Roy
Flip-Flop: Timing Deinitions Pro. Kaushik Roy
Maximum Clock Frequency t pff t p, comb t setup T Pro. Kaushik Roy
CMOS Clocked SR Flip-Flop V DD S Q Q M2 M4 Q R Q S M6 M5 M1 M3 M8 M7 R Pro. Kaushik Roy
Transistor Sizing o SR Flip-Flop Assume transistors o inverters are sized so that V M is V DD /2, mobility ratio m n /m p = 3 (W/L) M1 = (W/L) M3 = 1.8/1.2 (W/L) M2 = (W/L) M4 = 5.4/1.2 To bring Q rom 1 to 0, need to properly ratio the sizes o pseudo-nmos inverter (M7-M8)-M4 V OL must be lower than V DD /2 k n, M 78 V V 2 DD DD DD DD V 2 8 DD Vtn k p, M 4 VDD Vtp 2 8 p ( W / L) M 78 ( W / L) M 4 ( W / L) M 3 n m m ( W / L) M 2( W / L) M 78 2( W / L) M 3 7 (3.6/1.2) V V 2 Pro. Kaushik Roy
Flip-Flop: Transistor Sizing Pro. Kaushik Roy
Propagation Delay Pseudo- NMOS inverter (M5-M6)-M2 Inverter M3-M4 Pro. Kaushik Roy
Complementary CMOS SR Flip-Flop V DD S M10 M12 R M9 M11 Q M2 M4 Q M6 M1 M3 M8 S M5 M7 R Eliminates pseudo-nmos inverters Faster switching and smaller transient current Pro. Kaushik Roy
6-Transistor SR Flip-Flop V DD R Q M2 M4 Q S M1 M3 Pro. Kaushik Roy
CMOS D Flip-Flop V DD D Q Q Q Q D D Pro. Kaushik Roy
Master-Slave D Flip-Flop V DD Q Q D D Pro. Kaushik Roy
CVSL-Style Master-Slave D-FF V DD V DD Q Q D Pro. Kaushik Roy
Charge-Based Storage D In D Pseudo-static Latch Pro. Kaushik Roy
Layout o a D Flip-Flop Q In Q In Q Q Pro. Kaushik Roy
Master-Slave Flip-Flop In A B D Overlapping clocks can cause race conditions undeined signals Pro. Kaushik Roy
2 Phase Non-Overlapping Clocks D In 1 A 2 2 1 1 t p12 2 Pro. Kaushik Roy
Asynchronous Setting In 1 A 2 D 2 -Set 1 Pro. Kaushik Roy
2-phase Dynamic Flip-Flop In 1 A 2 D Input sampled Output Enabled 1 2 Pro. Kaushik Roy
Flip-lop Insensitive to Clock Overlap V DD V DD M2 M6 In M4 X M8 D M3 C L1 M7 C L2 M1 M5 -section -section C 2 MOS Latch or Clocked CMOS Latch Pro. Kaushik Roy
C 2 MOS Latch Avoids Race Conditions V DD V DD M2 M6 In X D C L1 1 M3 1 M7 C L2 M1 M5 Cascaded inverters: needs one pull-up ollowed by one pulldown, or vice versa to propagate signal (1-1) overlap: Only the pull-down networks are active, input signal cannot propagate to the output (0-0) overlap: only the pull-up networks are active Pro. Kaushik Roy
Clocked CMOS Logic Replace the inverter in a C 2 MOS latch with a complementary CMOS logic V DD V DD In1-3 In1-3 PUN M4 M3 PDN C L1 X PUN M8 M7 PDN C L2 Divide the computation into stages: Pipelining Pro. Kaushik Roy
REG REG REG REG REG REG REG REG Pipelining a Non-pipelined a Pipelined log log b b T min t p, reg t p, logic tsetup, reg T min, pipe t p, reg max( t p, adder, t p, abs, t p,log) tsetup, reg Pro. Kaushik Roy
Pipelined Logic using C 2 MOS V DD V DD V DD In out F G C 1 C 2 C 3 NORA CMOS (NO-RAce logic) Race ree as long as all the logic unctions F and G between the latches are non-inverting Pro. Kaushik Roy
Example V DD V DD V DD In Number o static inversion should be even Pro. Kaushik Roy
NORA CMOS -module = 0 = 1 Logic Precharge Evaluate Latch Hold Evaluate Pro. Kaushik Roy
NORA CMOS -module = 0 = 1 Logic Evaluate Precharge Latch Evaluate Hold Pro. Kaushik Roy
NORA Logic NORA data path consists o a chain o alternating and modules Dynamic-logic rule: single 0 1 (1 0) transition or dynamic n-block (p-block) C 2 MOS rule: I dynamic blocks are present, even number o static inversions between a latch and a dynamic block Otherwise, even number o static inversions between latches Static logic may glitch, best to keep all o them ater dynamic blocks Pro. Kaushik Roy
Doubled C 2 MOS Latches Doubled n-c 2 MOS latch Doubled p-c 2 MOS latch Pro. Kaushik Roy
TSPC - True Single Phase Clock Logic Including logic into the latch Inserting logic between the latches Pro. Kaushik Roy
Simpliied TSPC Latches A and A do not have ull logic swing Pro. Kaushik Roy
Master-Slave Simpliied TSPC Flip-Flops Positive edge-triggered D lip-lops Reduces clock load Pro. Kaushik Roy
Further Simplication Pro. Kaushik Roy
Schmitt Trigger VTC with hysteresis Restores signal slopes Pro. Kaushik Roy
Noise Suppression using Schmitt Trigger Sharp low-to-high transition Pro. Kaushik Roy
CMOS Schmitt Trigger Moves switching threshold o irst inverter Pro. Kaushik Roy
Sizing o M3 and M4 V M+ = 3.5V k2 2 M1 and M2 are in saturation; M4 is in triode region k1 2 4 2 V V V k V V V V DD M tp V M DD V tn tp 2 DD M V DD V 2 M 2 V M- = 1.5V M1 and M2 are in saturation; M3 is in triode region Pro. Kaushik Roy
Schmitt Trigger: Simulated VTC Pro. Kaushik Roy
CMOS Schmitt Trigger In = 0, at steady state, V Out = V DD, V X = V DD - V tn In makes a 0 1 transition Saturated load inverter M1-M5 discharges X M2 inactive until V X = V in - V tn Use V in to approximate V M- M1-M5 in saturation k1 2 k 2 2 5 V V V V 2 M tn DD M Pro. Kaushik Roy