Module -5 Sequential Logic Design

Module -5 Sequential Logic Design 5.1. Motivation: In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs, the input history. Sequential logic is combinational logic with memory. Sequential logic is used to construct finite state machines, a basic building block in all digital circuitry, as well as memory circuits and other devices. This subject addresses the basic principles of Digital electronics in the light of new developments in IT. Availability of various digital functions in ICs has changed the teaching of digital electronics from the good old style using discrete devices to a new style using modern digital ICs. 5.2. Syllabus: Module Contents Duration Self- Study 5.1 Flip Flops : SR, JK, D, T 1Hrs 1Hrs 5.2 5.3 master slave flip flop, Truth Table, 2 Hrs 2 Hrs 5.4 excitation table and conversion 1 Hrs 1 Hrs 5.5 5.6 Register: Shift register, SISO, SIPO, PISO, PIPO, 2 Hrs 2 Hrs 5.7 Bi-directional and universal shift register. 1 Hrs 2 Hrs 5.8 5.9 Counters: Design of synchronous and asynchronous,modulo Counter, 2 Hrs 4 Hrs 5.10 Up Down counter IC 74193, 1 Hrs 2 Hrs 5.11 Ring and Johnson Counter 1 Hrs 2 Hrs 5.3. Weightage in university Examination: - 5.5. Learning Objective/ outcome : 5.5.1 Learning Objective: In this module student will try to Design and implementation of sequential circuits 5.5.2 Learning Outcome: At the end student will be able to Design and develop sequential circuits

5.5. Theoretical Background: This subject addresses the basic principles of Digital electronics in the light of new developments in IT. Availability of various digital functions in ICs has changed the teaching of digital electronics from the good old style using discrete devices to a new style using modern digital ICs. 5.6. Key Definitions: Flip Flop Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at particular instants of time and not continuously Register Counter A group of flip-flop is known as a Register Digital circuit which is used for a counting pulses is known counter. 5.7 Introduction The combinational circuit does not use any memory. Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory so output can vary based on input. This type of circuits uses previous input, output, clock and a memory element. The basic building block that makes computer memories possible, and is also used in many sequential logic circuits is the flip-flop or bi-stable circuit. Just two interconnected logic gates make up the basic form of this circuit whose output has two stable output states. When the circuit is triggered into either one of these states by a suitable input pulse, it will remember that state until it is changed by a further input pulse, or until power is removed. For this reason the circuit may also be called a Bi-stable Latch. 5.7.1 Flip Flop Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge triggered rather than being level triggered like latches. 5.7.1.1 S-R Flip Flop

The SR flip-flop can be considered as a 1-bit memory, since it stores the input pulse even after it has passed. Flip-flops (or bi-stables) of different types can be made from logic gates and, as with other combinations of logic gates, the NAND and NOR gates are the most versatile, the NAND being most widely used. This is because, as well as being universal, i.e. it can be made to mimic any of the other standard logic functions, it is also cheaper to construct. It is basically S-R latch using NAND gates with an additional enable input. It is also called as level triggered SR-FF. For this, circuit in output will take place if and only if the enable input (E) is made active. In short this circuit will operate as an S-R latch if E = 1 but there is no change in the output if E = 0. The SR (Set-Reset) flip-flop is one of the simplest sequential circuits and consists of two gates connected as shown in Fig5.1. Notice that the output of each gate is connected to one of the inputs of the other gate, giving a form of positive feedback or crosscoupling. Block Diagram Circuit Diagram Fig5.1 Fig5.2

Truth Diagram Table 5.1 Operation S.N. Condition Operation If S = R = 0 then output of NAND gates 3 and 4 are 1 S = R = 0 : No change forced to become 1. Hence R' and S' both will be equal to 1. Since S' and R' are the input of the basic S-R latch using NAND gates, there will be no change in the state of outputs. Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the 2 S = 0, R = 1, E = 1 output of NAND-4 i.e. S' = 0. Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition. Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1. 3 S = 1, R = 0, E = 1 Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is the reset condition. As S = 1, R = 1 and E = 1, the output of NAND gates 3 4 S = 1, R = 1, E = 1 and 4 both are 0 i.e. S' = R' = 0. Hence the Race condition will occur in the basic NAND

latch. 5.7.2 Master Slave JK Flip Flop Master slave JK FF is a cascade of two S-R FF with feedback from the output of second to input of first. Master is a positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond to the negative level. Hence when the clock = 1 (positive level) the master is active and the slave is inactive. Whereas when clock = 0 (low level) the slave is active and master is inactive. Circuit Diagram Truth Table Fig 5.3 Operation Table 5.3 S.N. Condition Operation

1 J = K = 0 (No change) When clock = 0, the slave becomes active and master is inactive. But since the S and R inputs have not changed, the slave outputs will also remain unchanged. Therefore outputs will not change if J = K =0. Clock = 1 Master active, slave inactive. Therefore outputs of the master become Q1 = 0 and Q1 bar = 1. That means S = 0 and R =1. Clock = 0 Slave active, master inactive. Therefore outputs of the slave become Q = 0 and Q bar = 1. 2 J = 0 and K = 1 (Reset) Again clock = 1 Master active, slave inactive. Therefore even with the changed outputs Q = 0 and Q bar = 1 fed back to master, its output will be Q1 = 0 and Q1 bar = 1. That means S = 0 and R = 1. Hence with clock = 0 and slave becoming active the outputs of slave will remain Q = 0 and Q bar = 1. Thus we get a stable output from the Master slave. Clock = 1 Master active, slave inactive. Therefore outputs of the master become Q1 = 1 and Q1 bar = 0. That means S = 1 and R =0. 3 J = 1 and K = 0 (Set) Clock = 0 Slave active, master inactive. Therefore outputs of the slave become Q = 1 and Q bar = 0. Again clock = 1 then it can be shown that the outputs of the slave are stabilized to Q = 1 and Q bar = 0. Clock = 1 Master active, slave inactive. Outputs of 4 J = K = 1 (Toggle) master will toggle. So S and R also will be inverted. Clock = 0 Slave active, master inactive. Outputs of

slave will toggle. These changed output are returned back to the master inputs. But since clock = 0, the master is still inactive. So it does not respond to these changed outputs. This avoids the multiple toggling which leads to the race around condition. The master slave flip flop will avoid the race around condition. 5.7.3 Delay Flip Flop / D Flip Flop Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between S and R inputs. It has only one input. The input data is appearing at the output after some time. Due to this data delay between i/p and o/p, it is called delay flip flop. S and R will be the complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1, these input condition will never appear. This problem is avoid by SR = 00 and SR = 1 conditions. Block Diagram Circuit Diagram Fig 5.4 Fig 5.5

Truth Table Operation S.N. Condition Operation Table 5.4 1 E = 0 Latch is disabled. Hence no change in output. 2 E = 1 and D = 0 If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is the reset condition. 3 E = 1 and D = 1 If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state. Toggle Flip Flop / T Flip Flop Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together. It has only input denoted by T as shown in the Symbol Diagram. The symbol for positive edge triggered T flip flop is shown in the Block Diagram. Symbol Diagram Fig 5.7

Block Diagram Truth Table Fig 5.8 Operation S.N. Condition Operation Table 5.5 1 T = 0, J = K = 0 The output Q and Q bar won't change 2 T = 1, J = K = 1 Output will toggle corresponding to every leading edge of clock signal. 5.7.1.5 Summary of the Types of Flip-flop Behavior Since memory elements in sequential circuits are usually flip-flops, it is worth summarizing the behavior of various flip-flop types before proceeding further. All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response invoked by different value of input signals. The four types of flip-flops are defined in Table 1.

Table 5.6 Flip-flop Types FLIP - FLO P NA ME FLIP-FLOP SYMBOL CHARACTERI STIC TABLE CHARACT ERISTIC EQUATIO N EXCITATION TABLE SR S R 0 0 Q 0 1 0 1 0 1 1 1? Q(n ext) Q(next) = S + R'Q SR = 0 Q Q(n ext) S R 0 0 0 X 0 1 1 0 1 0 0 1 1 1 X 0 JK J K 0 0 Q 0 1 0 Q(n ext) Q(next) = JQ' + K'Q Q Q(n ext) J K 0 0 0 X 0 1 1 X 1 0 1 1 0 X 1 1 1 Q' 1 1 X 0 D D 0 0 Q(n ext) Q(next) = D Q Q(ne xt) D 0 0 0 0 1 1 1 1 1 0 0 1 1 1 T T Q(n ext) 0 Q Q(next) = TQ' + T'Q Q Q(ne xt) T 0 0 0 0 1 1 1 Q' 1 0 1 1 1 0

5.7.4 Flip Flop Conversion The main purpose of the flip flop conversion is to convert a flip flop into a desired type-b flip flop using some conversion logic. The flip flop conversions are classified into different types that are SR-FF to JK-FF Conversion JK-FF to SR-FF Conversion SR-FF to D-FF Conversion D-FF to SR-FF Conversion JK-FF to T-FF Conversion JK-FF to D-FF Conversion D-FF to JK-FF Conversion 5.7.4.1 SR-Flip Flop to JK-Flip Flop Conversion In JK-flipflop, j and k are given as external i/ps to S and R in SR-flip flop. Here, both S & R are o/ps of the combinational circuit. The truth tables of flip flop conversions are shown below. The current state is denoted with Qp& Qp+1 is the next state to be found when the J &K i/ps are applied. Fig 5.9 SR-FF to JK-FF Conversion

There are eight possible combinations for two i/ps J and K. For every combination of J, K &Qp, the equivalent Qp+1 states are found. Qp+1 simply recommends the future values to be found by the JK-flip flop after the importance of Qp. Then the table is finished by writing the values of S & R compulsory to get each Qp+1 from the equivalent Qp. That is, the S and R values are compulsory to change the state of the flip flop from Qp to Qp+1 are written 5.7.4.2 JK-Flip Flop to SR-Flip Flop Conversion The conversion of the JK-FF to SR-FF is opposite to the SR-FF to JK-FF. Here S & R will be the external i/ps to J & K, that is shown in the below logic diagram, J & K will be the o/ps of the combinational circuit. So, the J and K values have to be acquired in terms of S, R &Qp. The logic diagram is shown below. The conversion table for flip flop to be written in terms of S, R, Qp, Qp+1, J & K. There are eight possible combinations for two i/ps S and R. Fig 5.10 K-FF to SR-FF Conversion For every combination, the equivalent Qp+1 o/p s are found. The o/p s for the combinations of S=R=1 are not acceptable for an SR-FF. Therefore the o/p s are considered as invalid and the J & K values are taken as don t care. 5.7.4.3 SR-Flip Flop to D-Flip Flop Conversion

As shown in the below figure, actual inputs of the flip flop are S & R where D is the external i/p. The four combinations of the S & R in terms of D and Qp, conversion table, logic diagram and the Karnaugh map are given below. Fig 5.11 SR-FF to D-FF Conversion 5.7.4.4 D-Flip Flop to SR-Flip Flop Conversion In this type of conversion, D is the actual i/p of the flip flop where S & R are the external i/ps.there are Eight possible combinations are obtained from the external i/ps S, R &Qp. Nevertheless, since the combination of S=R=1 is unacceptable, the values of D and Qp+1 are taken as don t care. The logic diagram of D-FF to SR-FF is showing the conversion from D-FF to SR-FF, and the Karnaugh map for D in terms of S, R &Qp are given below. Fig 5.12 D-FF to SR-FF Conversion 5.7.4.5 JK-Flip Flop to T-Flip Flop Conversion In this type of conversion, J & k are the actual i/ps of the flip flop where K is considered as the external i/p. Four combinations are created by T, Qp, J & K that are

expressed in terms of T &Qp. The Karnaugh map, the logic diagram and conversion table, are given below. Fig 5.13 JK-FF to T-FF Conversion 5.7.4.6 JK-Flip Flop to D-Flip Flop Conversion In this type of flip flop conversion, J&K are the actual inputs where D is the external input of the flip flop. The four combinations of the flip flop will be done by using D &Qp, and in terms of these two J&K are expressed. The conversion table with four combinations, JK-FF to D-FF conversion logic diagram and Karnaugh map for J & K in terms of D & are shown below. Fig 5.14 JK-FF to D-FF Conversion 5.7.4.7 D-Flip Flop to JK-Flip Flop Conversion In this type of flip flop conversion, J & K are the external i/ps of the flip flop where D is the actual input. The eight combinations can make by using J, K and Qp that is shown in the conversion table below. D is stated in terms of J, K &Qp. The Karnaugh map D in terms of J, K &Qp, conversion table and the logic diagram of the D-FF to JK-FF is shown below.

Fig 5.15 D-FF to JK-FF Conversion Thus, this is all about different types of flip flop conversions, that includes SR-FF to JK- FF, JK-FF to SR-FF, SR-FF to D-FF, D-FF to SR-FF, JK-FF to T-FF, JK-FF to D-FF and D- FF to JK-FF. 5.7.5 Register Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and it is capable of storing an n-bit word. The binary data in a register can be moved within the register from one flip-flop to another. The registers that allow such data transfers are called as shift registers. There are four mode of operations of a shift register. Serial Input Serial Output Serial Input Parallel Output Parallel Input Serial Output Parallel Input Parallel Output 5.7.5.1 Serial Input Serial Output Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of a four bit binary number 1 1 1 1 is made into the register, this number should be applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected

to serial data input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flipflop i.e. D2 and so on. Block Diagram Fig 5.16 Operation Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of clock, the FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000. Fig 5.17 Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100. Fig 5.18

Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110. Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in the register is Q3 Q2 Q1 Q0 = 1111. Truth Table Fig 5.19 Waveforms

Fig 5.20 5.7.5.2 Serial Input Parallel Output In such types of operations, the data is entered serially and taken out in parallel fashion. Data is loaded bit by bit. The outputs are disabled as long as the data is loading. As soon as the data loading gets completed, all the flip-flops contain their required data, the outputs are enabled so that all the loaded data is made available over all the output lines at the same time. 4 clock cycles are required to load a four bit word. Hence the speed of operation of SIPO mode is same as that of SISO mode. Block Diagram

5.7.6.1 Parallel Input Serial Output (PISO) Fig 5.21 Data bits are entered in parallel fashion. The circuit shown below is a four bit parallel input serial output register. Output of previous Flip Flop is connected to the input of the next one via a combinational circuit. The binary input word B0, B1, B2, B3 is applied though the same combinational circuit. There are two modes in which this circuit can work namely - shift mode or load mode. Load mode When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they will pass B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of clock, the binary input B0, B1, B2, B3 will get loaded into the corresponding flip-flops. Thus parallel loading takes place. Shift mode When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence the parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active. Therefore the shifting of data from left to right bit by bit on application of clock pulses. Thus the parallel in serial out operation takes place. Block Diagram

Fig 5.22 5.7.6.2 Parallel Input Parallel Output (PIPO) In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the input binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear simultaneously to the output side. Only clock pulse is essential to load all the bits. Block Diagram Fig 5.23

5.7.7Bidirectional Shift Register If a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to dividing the original number by 2. Hence if we want to use the shift register to multiply and divide the given binary number, then we should be able to move the data in either left or right direction. Such a register is called bi-directional register. A four bit bi-directional shift register is shown in fig. There are two serial inputs namely the serial right shift data input DR, and the serial left shift data input DL along with a mode select input (M). Block Diagram Fig 5.24 Operation S.N. Condition Operation 1 With M = 1 Shift right operation If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas the remaining AND gates 2, 4, 6 and 8 will be disabled.

The data at DR is shifted to right bit by bit from FF-3 to FF-0 on the application of clock pulses. Thus with M = 1 we get the serial right shift operation. When the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are enabled while 1, 3, 5 and 7 are disabled. 2 With M = 0 Shift left operation The data at DL is shifted left bit by bit from FF-0 to FF-3 on the application of clock pulses. Thus with M = 0 we get the serial right shift operation. 5.7.7.6 Universal Shift Register A shift register which can shift the data in only one direction is called a uni-directional shift register. A shift register which can shift the data in both directions is called a bidirectional shift register. Applying the same logic, a shift register which can shift the data in both directions as well as load it parallely, is known as a universal shift register. The shift register is capable of performing the following operation Parallel loading Lift shifting Right shifting The mode control input is connected to logic 1 for parallel loading operation whereas it is connected to 0 for serial shifting. With mode control pin connected to ground, the universal shift register acts as a bi-directional register. For serial left operation, the input is applied to the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right operation, the serial input is applied to D input. Block Diagram

Fig 5.25 5.7.8 Counters Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Counters are of two types. Asynchronous or ripple counters. Synchronous counters. 5.7.8.1 Asynchronous or ripple counters The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are being used. But we can use the JK flip-flop also with J and K connected permanently to logic 1. External clock is applied to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop i.e. FF-B. Logical Diagram

Operation S.N. Condition Operation Fig 5.26 1 Initially let both the FFs be in the reset state QBQA = 00 initially As soon as the first negative clock edge is applied, FF-A will toggle and QA will be equal to 1. 2 After 1st negative clock edge QA is connected to clock input of FF-B. Since QA has changed from 0 to 1, it is treated as the positive clock edge by FF-B. There is no change in QB because FF-B is a negative edge triggered FF. QBQA = 01 after the first clock pulse. 3 After 2nd negative clock edge On the arrival of second negative clock edge, FF-A toggles again and QA = 0. The change in QA acts as a negative clock edge for FF-B. So it will also toggle, and QB will be 1. QBQA = 10 after the second clock pulse. 4 After 3rd negative clock edge On the arrival of 3rd negative clock edge, FF-A toggles

again and QA become 1 from 0. Since this is a positive going change, FF-B does not respond to it and remains inactive. So QB does not change and continues to be equal to 1. QBQA = 11 after the third clock pulse. On the arrival of 4th negative clock edge, FF-A toggles again and QA becomes 1 from 0. 5 After 4th negative clock edge This negative change in QA acts as clock pulse for FF-B. Hence it toggles to change QB from 1 to 0. QBQA = 00 after the fourth clock pulse. Truth Table Synchronous counters If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is called as synchronous counter. 2-bit Synchronous up counter The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The JB and KB inputs are connected to QA. Logical Diagram

Operation S.N. Condition Operation Fig 5.27 1 Initially let both the FFs be in the reset state QBQA = 00 initially. 2 3 4 5 After 1st negative clock edge After 2nd negative clock edge After 3rd negative clock edge After 4th negative clock edge As soon as the first negative clock edge is applied, FF-A will toggle and QA will change from 0 to 1. But at the instant of application of negative clock edge, QA, JB = KB = 0. Hence FF-B will not change its state. So QB will remain 0. QBQA = 01 after the first clock pulse. On the arrival of second negative clock edge, FF-A toggles again and QA changes from 1 to 0. But at this instant QA was 1. So JB = KB= 1 and FF-B will toggle. Hence QB changes from 0 to 1. QBQA = 10 after the second clock pulse. On application of the third falling clock edge, FF-A will toggle from 0 to 1 but there is no change of state for FF-B. QBQA = 11 after the third clock pulse. On application of the next clock pulse, QA will change from 1 to 0 as QB will also change from 1 to 0. QBQA = 00 after the fourth clock pulse.

Classification of counters Depending on the way in which the counting progresses, the synchronous or asynchronous counters are classified as follows Up counters Down counters Up/Down counters UP/DOWN Counter Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode control (M) input is also provided to select either up or down mode. A combinational circuit is required to be designed and used between each pair of flip-flop in order to achieve the up/down operation. Type of up/down counters UP/DOWN ripple counters UP/DOWN synchronous counter UP/DOWN Ripple Counters In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flipflops or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every other FF is obtained from (Q = Q bar) output of the previous FF. UP counting mode (M=0) The Q output of the preceding FF is connected to the clock of the next stage if up counting is to be achieved. For this mode, the mode select input M is at logic 0 (M=0). DOWN counting mode (M=1) If M = 1, then the Q bar output of the preceding FF is connected to the next FF. This will operate the counter in the counting mode. Example 3-bit binary up/down ripple counter. 3-bit hence three FFs are required.

UP/DOWN so a mode control input is essential. For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next one. For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next one. For a ripple down counter, the Q bar output of preceding FF is connected to the clock input of the next one. Let the selection of Q and Q bar output of the preceding FF be controlled by the mode control input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1, DOWN counting. So connect Q bar to CLK. Block Diagram Fig 5.28 Truth Table Table 5.

Operation S.N. Condition Operation If M = 0 and M bar = 1, then the AND gates 1 and 3 in fig. will be enabled whereas the AND gates 2 and 4 will be disabled. Hence QA gets connected to the 1 Case 1 With M = 0 (Up counting mode) clock input of FF-B and QB gets connected to the clock input of FF- C. These connections are same as those for the normal up counter. Thus with M = 0 the circuit work as an up counter. If M = 1, then AND gates 2 and 4 in fig. are enabled whereas the AND gates 1 and 3 are disabled. 2 Case 2: With M = 1 (Down counting mode) Hence QA bar gets connected to the clock input of FF-B and QB bar gets connected to the clock input of FF- C. These connections will produce a down counter. Thus with M = 1 the circuit works as a down counter.

Synchronous Counter With the Synchronous Counter, the external clock signal is connected to the clock input of EVERY individual flip-flop within the counter so that all of the flip-flops are clocked together simultaneously (in parallel) at the same time giving a fixed time relationship. In other words, changes in the output occur in synchronization with the clock signal. The result of this synchronization is that all the individual output bits changing state at exactly the same time in response to the common clock signal with no ripple effect and therefore, no propagation delay. Binary 4-bit Synchronous Up Counter Fig 5.29 It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each of the J-K flip-flops in the counter chain and that both the J and K inputs are all tied together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic 1 allowing the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a predetermined sequence of states in response to the common clock signal, advancing one state for each pulse. The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also supplied with signals from the input and output of the previous

stage. These additional AND gates generate the required logic for the JK inputs of the next stage. If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are HIGH we can obtain the same counting sequence as with the asynchronous circuit but without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time. Then as there is no inherent propagation delay in synchronous counters, because all the counter stages are triggered in parallel at the same time, the maximum operating frequency of this type of frequency counter is much higher than that for a similar asynchronous counter circuit. 4-bit Synchronous Counter Waveform Timing Diagram. Because this 4-bit synchronous counter counts sequentially on every clock pulse the resulting outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ). Therefore, this type of counter is also known as a 4-bit Synchronous Up Counter. However, we can easily construct a 4-bit Synchronous Down Counter by connecting the AND gates to the Q output of the flip-flops as shown to produce a waveform timing diagram the reverse of the above. Here the counter starts with all of its outputs HIGH

( 1111 ) and it counts down on the application of each clock pulse to zero, ( 0000 ) before repeating again. Binary 4-bit Synchronous Down Counter Fig 5.30 As synchronous counters are formed by connecting flip-flops together and any number of flip-flops can be connected or cascaded together to form a divide-by-n binary counter, the modulo s or MOD number still applies as it does for asynchronous counters so a Decade counter or BCD counter with counts from 0 to 2 n -1 can be built along with truncated sequences. All we need to increase the MOD count of an up or down synchronous counter is an additional flip-flop and AND gate across it. Decade 4-bit Synchronous Counter A 4-bit decade synchronous counter can also be built using synchronous binary counters to produce a count sequence from 0 to 9. A standard binary counter can be converted to a decade (decimal 10) counter with the aid of some additional logic to implement the desired state sequence. After reaching the count of 1001, the counter recycles back to 0000. We now have a decade or Modulo-10 counter. Decade 4-bit Synchronous Counter

Fig 5.31 The additional AND gates detect when the counting sequence reaches 1001, (Binary 10) and causes flip-flop FF3 to toggle on the next clock pulse. Flip-flop FF0 toggles on every clock pulse. Thus, the count is reset and starts over again at 0000 producing a synchronous decade counter. We could quite easily re-arrange the additional AND gates in the above counter circuit to produce other count numbers such as a Mod-12 counter which counts 12 states from 0000 to 1011 (0 to 11) and then repeats making them suitable for clocks, etc. Triggering a Synchronous Counter Synchronous Counters use edge-triggered flip-flops that change states on either the positive-edge (rising edge) or the negative-edge (falling edge) of the clock pulse on the control input resulting in one single count when the clock input changes state. Generally, synchronous counters count on the rising-edge which is the low to high transition of the clock signal and asynchronous ripple counters count on the falling-edge which is the high to low transition of the clock signal.

Fig 5.32 It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state, but this makes it easier to link counters together because the most significant bit (MSB) of one counter can drive the clock input of the next. This works because the next bit must change state when the previous bit changes from high to low the point at which a carry must occur to the next bit. Synchronous counters usually have a carry-out and a carry-in pin for linking counters together without introducing any propagation delays. Then to summarize some of the main points about Synchronous Counters: Synchronous Counters can be made from Toggle or D-type flip-flops. Synchronous counters are easier to design than asynchronous counters. They are called synchronous counters because the clock input of the flip-flops are all clocked together at the same time with the same clock signal. Due to this common clock pulse all output states switch or change simultaneously. With all clock inputs wired together there is no inherent propagation delay. Synchronous counters are sometimes called parallel counters as the clock is fed in parallel to all flip-flops. The inherent memory circuit keeps track of the counters present state. The count sequence is controlled using logic gates. Overall faster operation may be achieved compared to Asynchronous counters. 5.7.9Asynchronous Counter

Asynchronous counters are those whose output is free from the clock signal. Because the flip flops in asynchronous counters are supplied with different clock signals, there may be delay in producing output. The required number of logic gates to design asynchronous counters is very less. So they are simple in design. Another name for Asynchronous counters is Ripple counters. The number of flip flops used in a ripple counter is depends up on the number of states of counter (ex: Mod 4, Mod 2 etc). The number of output states of counter is called Modulus or MOD of the counter. The maximum number of states that a counter can have is 2n where n represents the number of flip flops used in counter. For example, if we have 2 flip flops, the maximum number of outputs of the counter is 4 i.e. 22. So it is called as MOD-4 counter or Modulus 4 counter. Different types of Asynchronous counters There are many types of Asynchronous counters available in digital electronics. They are 4 bit synchronous UP counter 4 bit synchronous DOWN counter 4 bit synchronous UP / DOWN counter Asynchronous 4-bit UP counter Fig 5.33 A 4 bit asynchronous UP counter with D flip flop is shown in above diagram. It is capable of counting numbers from 0 to 15. The clock inputs of all flip flops are cascaded and the D input (DATA input) of each flip flop is connected to a state output of the flip flop. That means the flip flops will toggle at each active edge or positive edge of the clock signal. The clock input is connected to first flip flop. The other flip flops in counter receive the clock signal input from Q output of previous flip flop. The output of the first flip flop will change, when the positive edge on clock signal occurs.

In the asynchronous 4- bit up counter, the flip flops are connected in toggle mode, so when the when the clock input is connected to first flip flop FF0, then its output after one clock pulse will become 20. The rising edge of the Q output of each flip flop triggers the clock input of its next flip flop. It triggers the next clock frequency to half of its applied input. The Q outputs of every individual flip flop (Q0, Q1, Q2, Q3) represents the count of the 4 bit UP counter such as 20 (1) to 23 (8). Working of asynchronous up counter is explained below, Let us assume that the 4 Q outputs of the flip flops are initially 0000. When the rising edge of the clock pulse is applied to the FF0, then the output Q0 will change to logic 1 and the next clock pulse will change the Q0 output to logic 0. This means the output state of the clock pulse toggles (changes from 0 to1) for one cycle. As the Q of FF0 is connected to the clock input of FF1, then the clock input of second flip flop will become 1. This makes the output of FF1 to be high (i.e. Q1 = 1), which indicates the value 20. In this way the next clock pulse will make the Q0 to become high again. So now both Q0 and Q1 are high, this results in making the 4 bit output 11002. Now if we apply the fourth clock pulse, it will make the Q0 and Q1 to low state and toggles the FF2. So the output Q2 will become 0010 2. As this circuit is 4 bit up counter, the output is sequence of binary values from 0, 1, 2, 3.15 i.e. 00002 to 11112 (0 to 1510). Fig 5.34 Timing diagram of Asynchronous counter

For example, if the present count = 3, then the up counter will calculate the next count as 5. Asynchronous 4-bit DOWN counter Fig 5.35 A 4 bit asynchronous DOWN counter is shown in above diagram. It is simple modification of the UP counter. 4 bit DOWN counter will count numbers from 15 to 0, downwards. The clock inputs of all flip flops are cascaded and the D input (DATA input) of each flip flop is connected to logic 1. That means the flip flops will toggle at each active edge (positive edge) of the clock signal. The clock input is connected to first flip flop. The other flip flops in counter receive the clock signal input from Q output of previous flip flop, rather than Q output. Here Q0, Q1, Q2, Q3 represents the count of the 4 bit down counter. The output of the first flip flop will change, when the positive edge of clock signal occurs. For example, if the present count = 3, then the up counter will calculate the next count as 2. The input clock will cause the change in output (count) of the next flip-flop. The operation of down counter is exactly opposite to the up counter operation. Here every clock pulse at the input will reduce the count of the individual flip flop. So the down counter counts from 15, 14, 13 0 i.e. (0 to 1510) or 11112 to 00002. Both up and down counters are designed using the asynchronous, based on clock signal, we don t use them widely, because of their unreliability at high clock speeds. What is clock ripple? The sum of time delay of individual clock pulses, that drive the circuit is called Clock ripple. The below figure explains how the logic gates will create propagation delay, in each flip flop.

Fig 5.36 The propagation delays of logic gates are represented by blue lines. Each of them will add to the delay of next flip flop and the sum of all these individual flip flops is known as the propagation delay of circuit. As the outputs of all flip-flops change at different time intervals and for every different inputs at clock signal, a new value occurs at output each time. For example, at clock pulse 8, the output should change from 11102 (710) to 00012 (810), in some time delay of 400 to 700 ns (Nano Seconds). For clock pulses other than 8, the sequence will change. Although this problem prevents the circuit being used as a reliable counter, it is still valuable as a simple and effective frequency divider, where a high frequency oscillator provides the input and each flip-flop in the chain divides the frequency by two. This is all about clock ripple. Asynchronous 3-bit up/down counters By adding up the ideas of UP counter and DOWN counters, we can design asynchronous up /down counter. The 3 bit asynchronous up/ down counter is shown below.

Fig 5.37 It can count in either ways, up to down or down to up, based on the clock signal input. UP Counting If the UP input and down inputs are 1 and 0 respectively, then the NAND gates between first flip flop to third flip flop will pass the non inverted output of FF 0 to the clock input of FF 1. Similarly, Q output of FF 1 will pass to the clock input of FF 2. Thus the UP /down counter performs up counting. DOWN Counting If the DOWN input and up inputs are 1 and 0 respectively, then the NAND gates between first flip flop to third flip flop will pass the inverted output of FF 0 to the clock input of FF 1. Similarly, Q output of FF 1 will pass to the clock input of FF 2. Thus the UP /down counter performs down counting. The up/ down counter is slower than up counter or a down counter, because the addition propagation delay will added to the NAND gate network Advantages Asynchronous counters can be easily designed by T flip flop or D flip flop. These are also called as Ripple counters, and are used in low speed circuits. They are used as Divide by- n counters, which divide the input by n, where n is an integer. Asynchronous counters are also used as Truncated counters. These can be used to design any mod number counters, i.e. even Mod (ex: mod 4) or odd Mod (ex: mod3).

Disadvantages Sometimes extra flip flop may be required for Re synchronization. To count the sequence of truncated counters (mod is not equal to 2n), we need additional feedback logic. While counting large number of bits, the propagation delay of asynchronous counters is very large. For high clock frequencies, counting errors may occur, due to propagation delay. Applications of Asynchronous Counters Asynchronous counters are used as frequency dividers, as divide by N counters. These are used for low power applications and low noise emission. These are used in designing asynchronous decade counter. Also used in Ring counter and Johnson counter. Asynchronous counters are used in Mod N ripple counters. EX: Mod 3, Mod 4, Mod 8, Mod 14, Mod 10 etc. 5.7.5 Decade Counters. A decade counter requires resetting to zero when the output count reaches the decimal value of 10, ie. when DCBA = 1010 and to do this we need to feed this condition back to the reset input. A counter with a count sequence from binary 0000 (BCD = 0 ) through to 1001 (BCD = 9 ) is generally referred to as a BCD binary-coded-decimal counter because its ten state sequence is that of a BCD code but binary decade counters are more common. 5.7.5.1. Asynchronous Decade Counter Fig 5.38

This type of asynchronous counter counts upwards on each trailing edge of the input clock signal starting from 0000 until it reaches an output 1001 (decimal 9). Both outputs QA and QD are now equal to logic 1. On the application of the next clock pulse, the output from the 74LS10 NAND gate changes state from logic 1 to a logic 0 level. As the output of the NAND gate is connected to the CLEAR ( CLR ) inputs of all the 74LS73 J-K Flip-flops, this signal causes all of the Q outputs to be reset back to binary 0000 on the count of 10. As outputs QA and QD are now both equal to logic 0 as the flip-flop s have just been reset, the output of the NAND gate returns back to a logic level 1 and the counter restarts again from 0000. We now have a decade or Modulo-10 upcounter. Decade Counter Truth Table Clock Count Output bit Pattern QD QC QB QA Decimal Value 1 0 0 0 0 0 2 0 0 0 1 1 3 0 0 1 0 2 4 0 0 1 1 3 5 0 1 0 0 4 6 0 1 0 1 5 7 0 1 1 0 6 8 0 1 1 1 7 9 1 0 0 0 8 10 1 0 0 1 9 11 Counter Resets its Outputs back to Zero

Decade Counter Timing Diagram Fig 5.39 By using the same idea of truncating counter output sequences, the above circuit could easily be adapted to other counting cycles be simply changing the connections to the inputs of the NAND gate or by using other logic gate combinations. So for example, a scale-of-twelve (modulo-12) can easily be made by simply taking the inputs to the NAND gate from the outputs at QC and QD, noting that the binary equivalent of 12 is 1100 and that output QA is the least significant bit (LSB). Since the maximum modulus that can be implemented with n flip-flops is 2 n, this means that when you are designing truncated asynchronous counters you should determine the lowest power of two that is greater than or equal to your desired modulus. Lets say we wish to count from 0 to 39, or mod-40 and repeat. Then the highest number of flip-flops required would be six, n = 6 giving a maximum MOD of 64 as five flip-flops would not be enough as this only gives us a MOD-32.

Now suppose we wanted to build a divide-by-128 counter for frequency division we would need to cascade seven flip-flops since 128 = 2 7. Using dual flip-flops such as the 74LS74 we would still need four IC s to complete the circuit. 5.7.10 Modulus Counter (MOD-N Counter) The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-8 counter. So in general, an n-bit ripple counter is called as modulo-n counter. Where, MOD number = 2 n. Type of modulus 2-bit up or down (MOD-4) 3-bit up or down (MOD-8) 4-bit up or down (MOD-16) Application of counters Frequency counters Digital clock Time measurement A to D converter Frequency divider circuits Digital triangular wave generator. 5.7.6 Ring counters (Johnson Ring Counter) Ring counter is a sequential logic circuit that is constructed using shift register. Same data recirculates in the counter depending on the clock pulse. Ring counters are of two types 1)Ordinary Ring counters

2) Johnson counter 5.7.10.1 4 bit Ring Counter The ring counter is a cascaded connection of flip flops, in which the output of last flip flop is connected to input of first flip flop. In ring counter if the output of any stage is 1, then its reminder is 0. The Ring counters transfers the same output throughout the circuit. That means if the output of the first flip flop is 1, then this is transferred to its next stage i.e. 2nd flip flop. By transferring the output to its next stage, the output of first flip flop becomes 0. And this process continues for all the stages of a ring counter. If we use n flip flops in the ring counter, the 1 is circulated for every n clock cycles. The circuit diagram of the ring counter is shown below. Fig 5.40 Here we design the ring counter by using D flip flop. This is a Mod 4 ring counter which has 4 D flip flops connected in series. The clock signal is applied to clock input of each flip flop, simultaneously and the RESET pulse is applied to the CLR inputs of all the flip flops. Operation of Ring Counter

Initially, all the flip flops in ring counter are reset to 0 by applying CLEAR signal. Before applying the clock pulse, we apply the PRESET pulse to the flip flops which assigns the value 1 to the ring counter circuit. For each clock signal, the data circulates among all the 4 flip flop stages of ring counter. This 4 staged ring counter is called Mod 4 ring counter or 4 bit ring counter. To circulate the data correctly in the ring counter, we must load the counter with required values like all 0 s or all 1 s. Circulation of data in Ring counters Fig 5.41 We know that the ring counter is similar to that of the shift registers connected in series. The above diagram shown the four stages of flip flops as the parallel in serial our shift registers, with data inputs D0, D1, D2 and D3. The data circulation in ring counter is explained below. By passing the reset signal, initially the flip flops are at RESET state. When the PRESET is applied to the ring counter the input of the circuit becomes 1. This input is connected to the first flip flop in the series, so that the flip flop QA is set to 1 and all other outputs of remaining flip flops will be low.

If we make the data input of the flip flop A to low, this gives us the data pulse as 0 1 0. Then for the second clock signal, the output of first flip flop will again change and then the output of B will become high. This means the data pulse 0 0 1 occurs. In this way, as the clock signal and input of first flip flop changes, the output of the other flip flops changes. As the output of last flip flop in series is connected to the input of the first flip flop, the data sequence rotates or circulates in the ring counter. Truth table of ring counter The truth table of the 4 bit ring counter is explained below. Table 5. When CLEAR input CLR = 0, then all flip flops are set to 1. When CLEAR input CLR = 1, the ring counter starts its operation. For one clock signal, the counter starts its operation. On next clock signal, the counter again resets to 0000. Ring counter has 4 sequences: 0001, 0010, 0100, 1000, 000. Timing diagram of Ring Counter

Fig 5.42 The timing diagram of the Ring counter will explain that the clock signal changes the output of every stage of the counter, so that CLK signal will help the data to circulate from one flip flop to another. As the 4 bit ring counter (4 stages or 4 flip flops) circulates the preset digit within one clock signal, the output frequency of each flip flop is ¼ th of the main clock frequency. State diagram of ring counter Fig 5.43

The state diagram of the 4 bit ring counter is shown in above picture. It denotes that the position of the preset digit (in this case preset digit is 1) is changing its position from LSB to MSB, for one clock signal. Advantages Can be implemented using D and JK flip-flops. It is a self-decoding circuit. Disadvantages Only four of the 15 states are being utilized. 5.7.11 Johnson Counter The Johnson counter is a modification of ring counter. In this the inverted output of the last stage flip flop is connected to the input of first flip flop. If we use n flip flops to design the Johnson counter, it is known as 2n bit Johnson counter or Mod 2n Johnson counter. This is an advantage of the Johnson counter that it requires only half number of flip flops that of a ring counter uses, to design the same Mod. The main difference between the 4 bit ring counter and the Johnson counter is that, in ring counter, we connect the output of last flip flop directly to the input of first flip flop. But in Johnson counter, we connect the inverted output of last stage to the first stage input. The Johnson counter is also known as Twisted Ring Counter, with a feedback. In Johnson counter the input of the first flip flop is connected from the inverted output of the last flip flop. The Johnson counter or switch trail ring counter is designed in such a way that it overcomes the limitations of ring counter. Mainly it reduces the number of flip flops required for designing the circuit.

Fig 5.44 Similar to the ring counter, the clock signal in johnson counter is connected to the clock input of each flip flop simultaneously. Operation of johnson counter The Johnson counter designed with D flip flop is shown below. It has four stages i.e. four flip flops connected in series type or cascaded. Initially zero / Null is fed to the Johnson counter and on applying the clock signal, outputs will change to 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 in a sequence and the sequence will repeat for next clock signal. The Johnson counter produces a special pattern by passing four 0 s and then four 1 s and thus it produces a special pattern by counting up down. Truth table of johnson counter The truth table of the 4 bit ring counter is explained below.

The state diagram indicates that how the data transfers from one flip flop to another for every clock pulse. The4 stage Johnson ring counters are used as frequency dividers, by varying their feedback connections. So they can be used as frequency divider circuits also. Timing diagram of johnson counter Fig 5.45 The timing diagram of the johnson counter will explain that the clock signal changes the output of every stage of the counter, so that CLK signal will help the data to circulate from one flip flop to another.