Sequential Circuits Combinational circuits Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs) Sequential circuits Combination circuits with memory Can store, retain, and then retrieve information 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 1
Sequential Circuits Consists of a combinational circuit connected to storage elements to form a feedback path Storage elements contain binary information which can define the state of the sequential circuit A sequential circuit is specified by a time sequence of inputs, outputs, and internal states 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 2
Sequential Circuits Two main types of sequential circuits A function of the timing of their signals 1. Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time 2. Asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change Often a combinational circuit with feedback to implement storage elements May become unstable at times; difficult to design Will not be covered 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 3
Synchronous Sequential Circuits Synchronous sequential circuits use storage elements that operate at discrete instants of time Clock generator provides synchronization (signal often called clock or clk) Clock pulses are distributed throughout the system in such a way that storage elements are affected only with the arrival of each pulse This pulse determines when computational activity will occur within the circuit, and other signals (external inputs and otherwise) determine what changes will take place affecting the storage elements and the outputs 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 4
Synchronous Sequential Circuits Often called clocked sequential circuits The activity within the circuit and the resulting updating of stored values is synchronized to the occurrence of clock pulses Most frequently used as they seldom have instability problems Their timing is easily broken down into independent discrete steps, each of which can be considered separately 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 5
Sequential Circuits: Flip-Flops Flops Storage elements (memory) used in clocked sequential circuits are flip-flops A binary storage device capable of storing one bit of information In a stable state, the output of a flip-flop is either 0 or 1 A sequential circuit may use many flip-flops to store as many bits as necessary 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 6
Sequential Circuits: Flip-Flops Flops The outputs and value that is stored in a flip-flop when the clock pulse occurs, are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both) Prior to the occurrence of the next clock pulse, the combinational logic forming the next value of the flip-flop must have reached a stable value Otherwise the flip-flop will capture transitional values and the circuit will fail 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 7
Sequential Circuits: Flip-Flops Flops The speed at which the combinational logic circuits operate is critical If the clock (synchronizing) pulses arrive at a regular interval the combinational logic must respond to a change in the state of the flip-flop in time to be updated before the next pulse arrives Propagation delays play an important role in determining the minimum interval between clock pulses that will allow the circuit to operate correctly 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 8
Sequential Circuits: Flip-Flops Flops A change in state of the flip-flops is initiated only by a clock pulse transition (0 to 1) When a clock pulse is not active, the feedback loop between the value stored in the flip-flop and the value formed at the input to the flip-flop is effectively broken because the flip-flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value The transition from one state to the next occurs only at predetermined intervals dictated by the clock pulses 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 9
Storage Elements: Latches A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit), until directed by an input signal to switch states Differ in the manner in which the inputs affect the binary state Latches operate with signal levels (level sensitive) Flip-flops operate with signal transitions (edge sensitive) Built with latches so we will cover them Latches are useful in asynchronous sequential circuits 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 10
SR Latch: NOR SR latch is a circuit with two cross-coupled NOR gates, and two inputs labeled S for set and R for reset Latch has two useful states When Q = 1 and Q' = 0, it is in the set state When Q = 0 and Q' = 1, it is in the reset state When both inputs are equal to 1 outputs Q and Q' are no longer complements of each other Forbidden 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 11
SR Latch: NOR Under normal conditions, both inputs of the latch remain at 0 unless the state has to be changed Applying a momentary 1 to the S causes the latch to go to the set state S must go back to 0 before any other changes take place (ie. R) Applying a momentary 1 to the R causes the latch to go to the reset state R must go back to 0 before any other changes take place (ie. S) 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 12
SR Latch: NAND SR latch with two crosscoupled NAND gates operates with both inputs normally at 1, unless the state of the latch has to be changed Applying 0 to the S input causes output Q to go to 0, and Q' to a 1 Applying 0 to the R input causes output Q to go to 1, and Q' to a 0 Avoid setting both to 0 Input and output signals for the SR NAND latch are the complement of the SR NOR latch Sometimes referred to as an S'R' or S R latch 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 13
SR Latch with Enable Basic SR latch can be modified by providing an enable signal for the other two inputs The outputs do not change as long as the enable signal remains at 0 When the enable input goes to 1, information from the S or R input is allowed to affect the latch as stated before SR Latches are typically not used because of the possibility of the forbidden condition 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 14
D Latch Ensure that inputs S and R are never equal to 1 (for NAND SR Latch w/enable) at the same time to eliminate the undesirable condition in the SR latch Use an inverter to set R to S' S becomes D (for data) When En = 0, the output doesn t change When En = 1, the output, Q becomes D and Q' becomes D' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 15
D Latch Often called a transparent latch since output follows changes in the data input as long as the enable input is asserted A latch is designated by a rectangular block with inputs on the left and outputs on the right (normal and complement) For the NAND SR latch, bubbles are added to the inputs to indicate that setting and resetting occur with a logic-0 signal An inverter could be placed at the enable input so that it will be active low 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 16
Storage Elements: Flip-Flops Flops The state of a latch or flipflop is switched by a change in the control input; called a trigger Using a D Latch would cause problems since a full feedback loop is active while clock is high D Flip-Flop is preferred as it only allows data to be captured for an instance and then the feedback loop is closed Combination circuit cannot change and deliver new outputs in that small amount of time 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 17
Positive Edge-Triggered D Flip-Flop Flop Constructed with two D Latches, master and slave When Clk is low, the master is capturing while the slave is holding on its previous value When the Clk switches high (rising edge), the master stops capturing and the slave captures the value the master had (Q is this value) when the Clk changed Later, when Clk switches low (falling edge), the slave starts holding its previous value while the master starts capturing again; Q does not change Remove first inverter to make it negative edge-triggered (Don t need to know figure 5.10) 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 18
Edge-Triggered D Flip-Flop Flop Timing response Setup time: minimum time that D must be maintained before the clock transition Hold time: minimum time that D must be maintained after the clock transition Propagation delay time: interval between the trigger edge and the stabilization of the output Symbol is similar to the D latch, except for the arrowhead-like symbol (dynamic input) in front of Clk A bubble indicates a negative edge trigger 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 19
JK Flip-Flops Flops Allows full control with only 2 inputs, J and K Characteristic Equation: Q(t+1) = JQ' + K'Q 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 20
T Flip-Flops Flops Output doesn t change when T = 0 Toggles output when T = 1 Characteristic Equation: Q(t+1) = TQ' + T'Q = T Q 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 21
Direct Inputs Some flip-flops may have direct inputs to set or reset the circuit Required to establish the initial state of a circuit on power-up Asynchronous; state of clock is not important Direct reset or Clear sets the flip-flop to 0 Direct set or Preset sets the flip-flop to 1 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 22
Analysis with State Equations State equation specifies the next state as a function of the present state and inputs A(t+ 1) = A(t)x(t) + B(t)x(t) B(t+ 1) = A'(t)x(t) y(t) = [A(t) + B(t)]x'(t) Drop (t) to simplify equation form: A(t+ 1) = Ax + Bx B(t+ 1) = A'x y = [A + B]x' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 23
State Table A sequential circuit with m flip-flops and n inputs needs 2 m+n rows Example (m=2, n=1): ABx is the input Use all combinations Derive outputs based on state equations: A(t+ 1) = Ax + Bx B(t+ 1) = A'x y = [A + B]x' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 24
Alternative State Table Inputs are states Needs 2 m rows Output shows next state for each input combination 2 n x (states + outputs) columns 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 25
State Diagram Numbers in side circles show the state (AB) Lines between circles show how the current state changes to the next If no change, a looped line back to the same state is shown x/y near lines show inputs/outputs values 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 26
Analysis with D Flip-Flops Flops Use new notation: D A = A x y Change to state equations: A(t+1) = D A A(t+1) = A x y 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 27
Analysis with JK Flip-Flops Flops 1. Determine flip-flop inputs in terms of present state and input variables 2. List binary values for each input equation 3. Use flip-flop characteristics table to determine next state Example: J A = B K A = Bx' J B = x' K B = A'x + Ax' = A x 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 28
Analysis with JK Flip-Flops Flops Find next state: J A = B K A = Bx' J B = x' K B = A x 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 29
Analysis with JK Flip-Flops Flops Or substitute into characteristic equations: J A = B K A = Bx' J B = x' K B = A x A(t + 1) = J A A' + K A 'A = BA' + (Bx')'A = A'B + AB' + Ax B(t + 1) = J B B' + K B 'B = x'b' + (A x)'b = B'x' + ABx + A'Bx' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 30
Analysis with T Flip-Flops Flops Same method as JK Inspect circuit: T A = Bx T B = x y = AB 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 31
Analysis with T Flip-Flops Flops Find next state: T A = Bx T B = x y = AB 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 32
Analysis with T Flip-Flops Flops Or substitute into characteristic equations: T A = Bx T B = x y = AB A(t + 1) = T'A + TA' = (Bx)'A + (Bx)A' = AB' + Ax' + A'Bx B(t + 1) = T'B + TB' = x B 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 33
Finite State Machines (FSM) - Mealy Mealy Machine Uses both state information and inputs to generate outputs Inputs should be registered to ensure proper synchronization of outputs 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 34
Finite State Machines (FSM) - Moore Moore Machine Uses only the state information to generate outputs State information is already registered to ensure proper synchronization of outputs 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 35
State Reduction m flip-flops may have 2 m states Reducing m may reduce overall circuit size May not as extra circuits to accommodate for reduction may increase the size in the end Example: Use letter symbols instead of binary values Examine state transitions, inputs, and outputs 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 36
2018 Roberto Muscedere Images 2013 Pearson Education Inc. 37 State Reduction State Reduction 01010110100 Generate state table: 0 0 1 0 1 1 0 0 0 0 0 Output 0 0 1 0 1 1 0 1 0 1 0 Input a g f g f f e d c b a a State
State Reduction Given a completely specified state table: Two states are said to be equivalent if, for each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state State e and g are equivalent, remove g 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 38
State Reduction State d and f are equivalent, remove f Reduction can be done systematically 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 39
State Assignment Must assign unique binary code to each state Options are: 1. Binary: may have some unused states; don t cares can reduce logic 2. Gray code: Easier to implement the Boolean functions for the transitions between states 3. One-Hot: Can reduce the overall number of decoders in the circuit, but it requires more flipflops 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 40
HDL Blocking/Non-Blocking Feedback path from flip-flops to combinational circuit back to flip-flops is not instant Use non-blocking assignments ( <= ) to honour this behaviour Sets the value for the next clock edge Blocking assignments ( = ) honour the behaviour of step-bystep or software evaluation Useful for intermediate computation or complex behavioural circuits Cannot mix block and non-blocking assignments on the same register in a process 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 41
Non-Blocking For example, C is the value stored in the flip-flop C will be changed on the rising edge of the next clock E is set to the current C, not the new value set to change on the rising edge of the clock Register can only be assigned once per branch // Verilog-2001 module nblock (output reg C, E, input CK, A, B, input [1:0] D); always @(posedge CK) begin if (D==0) C <= A B C; else if (D==1) C <= A&B&C; else if (D==2) C <= A^B^C; else C <= ~C; //(D==3) E <= C; end endmodule 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 42
Non-Blocking All branches of if and case must be assigned either with else or default respectively Otherwise circuit will use a controlled feedback (shown) or an enable on flip-flop (more logic, bigger circuit) // Verilog-2001 module nblock (output reg C, E, input CK, A, B, input [1:0] D); always @(posedge CK) begin if (D==0) C <= A B C; else if (D==1) C <= A&B&C; else if (D==2) C <= A^B^C; E <= C; end endmodule 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 43
Blocking Blocking assignments leading up to non-blocking assignments are processed in series Similar to software T is never actually a register, just wires since its value is not read at the beginning of the process If T were read, it would become a register and the last assignment would be the value saved in the flip-flop... C <= A + 2 + B; D <= A + 2 + B + C; E <= A + 2 + B + D;... // Verilog-2001 module block (output reg [6:0] C, D, E, input CK, input [4:0] A, B); reg [6:0] T; always @(posedge CK) begin T = A; T = T + 2; T = T + B; C <= T; D <= T + C; T = T + D; E <= T; // T never exists as a // register end endmodule 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 44
Inferring D Latches Inferring D latches in a design requires that the output of a register is set using a non-blocking assignment (<=) on a condition based on the clock (CK) which is not prefixed by posedge or negedge in the sensitivity list In this example, T (computed earlier with a blocking assignment) is loaded into Y when CK is high // Verilog-2001 module circuit_latch (output reg Y, input CK, A, B); reg T; always @(CK, A, B) begin // some logic with A and B // with results in T // eg. T = A + B; if (CK) Y <= T; end endmodule 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 45
Inferring D Flip-Flops Flops Inferring D flip-flop in a design requires that the output of a register is set using a non-blocking assignment (<=) on a condition based on the clock (CK) which is prefixed only by posedge or negedge in the sensitivity list In this example, T (computed earlier with a blocking assignment) is loaded into Y on the positive edge of CK (as noted by the sensitivity list) // Verilog-2001 module circuit_ff (output reg Y, input CK, A, B); reg T; always @(posedge CK) begin // some logic with A and B // with results in T // eg. T = A + B; Y <= T; end endmodule 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 46
Inferring D Flip-Flops Flops with Direct Inputs Inferring D flip-flop with direct inputs (eg. reset or preset) in a design requires that the procedure be encased with an if where all desired outputs are set to 0 (or 1) based on the reset or preset condition The else of if should contain non-reset/nonpreset logic // Verilog-2001 module circuit_ffr (output reg Y, input CK, R, A, B); reg T; always @(posedge CK, negedge R) begin if (!R) Y <= 0; else begin // some logic with A and B // with results in T // eg. T = A + B; Y <= T; end end endmodule 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 47
FSM HDL of Zero Detector Y is not registered; don t set it in posedge process Last value of blocked registers honoured Moore FSM since Y doesn t depend on X directly // Verilog-2001 module zerodetect_moore (output reg Y, input CK, R, X); reg [1:0] cs, ns; always @(posedge CK, negedge R) if (!R) cs <= 2'b00; else cs <= ns; always @(cs, X) begin Y = 0; ns = 2'b00; casex ({cs,x}) 3'b00_0: ns = 2'b00; 3'b00_1: ns = 2'b01; 3'b01_1: ns = 2'b11; 3'b11_1: ns = 2'b10; 3'b10_1: ns = 2'b10; default: Y = 1; endcase end endmodule 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 48
FSM HDL of Zero Detector Y is not registered; set in assign based on current state and input X Mealy FSM since Y depends on X directly // Verilog-2001 module zerodetect_mealy (output Y, input CK, R, X); reg [1:0] cs; always @(posedge CK, negedge R) if (!R) cs <= 2'b00; else begin casex ({cs,x}) 3'b00_1: cs <= 2'b01; 3'b01_1: cs <= 2'b11; 3'b1x_1: cs <= 2'b10; default: cs <= 2'b00; endcase end assign Y = (cs==0)? 0 : ~X; endmodule 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 49
Design Procedure or Methodology Industry relies on automated synthesis tools for designing massive integrated circuits Synthesis tools use D flip-flops Possible to use JK and T flip-flops Designers do not concern themselves with the type of flip-flop Focus is on correctly describing the sequential functionality of the circuit Designing combinational circuits requires a truth table Designing clocked sequential circuits requires a set of specifications, state table (series of steps), a series of combinational circuits 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 50
Design Procedure or Methodology Number of flip-flops is determined from the number of states needed in the circuit and the choice of state assignment codes Combinational circuit is derived from the state table by evaluating the type of flip-flop and its input equations and output equations Steps: 1. Derive state table/diagram, and reduce states 2. Assign binary values to the states, and adjust table 3. Select flip-flop type, add to state table if necessary 4. Derive the flip-flop input and output equations 5. Draw the logic diagram 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 51
Design Example - D Flip-flops 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 52
Design Example - D Flip-flops 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 53
Design Example - JK Flip-flops 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 54
Design Example - JK Flip-flops 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 55
Design Example - T Flip-flops 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 56
Design Example - T Flip-flops Every sequential design should have a reset signal 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 57