MEMS1082 Chapter 6 Digital Circuit 6-5
General digital system
D Flip-Flops, The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the clear state. CK
JK Flip-Flop A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop. J is for set and the letter K is for clear. When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, i.e., if Q=1, it switches to Q=0 and vice versa. Transition table CK
JK Flip-Flop Timing Diagram/ wave form
JK Flip-Flop
JK Flip-Flop D flip-flop (JK)
Timing diagram for D flip-flop
D flip-flop for parallel data transfer Controlled by negative edge clock signal
JK Flip-Flop with Synchronous Inputs
JK Flip-Flop
JK Flip-Flop Toggle
JK Flip-Flop T (toggle) flip-flop Toggle: the output changes to opposite state
JK Flip-Flop: Timing diagram A,B, C: input wave forms D,E, F: output wave forms
Applications Flip-flop Q Switch debouncing Q Mechanical contact bounce will produce multiple transition NANA latch is used to debounce a Mechanical switch
Applications Flip-flop Switch debouncing Circuit
Applications Flip-flop Example: Analyze the operation of the circuit Passage of lkhz pulse signal NANA latch used to debounce a Mechanical switch
Applications Flip-flop Light detector/alarming using flip-flop When light on the phototransistor, S=R=0, Q is LOW When light off momentarily, S=1, R=0, then Q will be HIGH Alarming The alarm will remain on because Q will remain HIGH even light on again. Open S1 will produce high to S (C in the figure), which turn off alarm.
Applications Flip-flop Detecting an input sequence
Applications Flip-flop Data Register A 4-bit data register uses negative edge-triggered D flip-flops to transfer data from four data lines to the outputs of four AND gates First, the data values Di are transferred to the outputs Q of the flip-flops on the negative edge of the load signal. Then a pulse on the read line presents the data at the register outputs Ri of the AND gates. Data registers are used in microprocessors to hold data for arithmetic calculations. Data registers can be cascaded to store as many bits as are required.
Applications Flip-flop A: Binary counting (3 bits) and frequency divider A 3-bit binary counter consisting of fthree negative edge-triggered toggle flip-flops connected in sequence. The three output bits Xi change according to the binary number counting sequence, counting from 0 to 8 (base 10) and returning back to 0. This circuit may also be used as a frequency divider. Output Xo is a divide-by-2 output since its frequency is 1/2 the input pulse train frequency. Xl, X2, and are divide-by-4, and-8 outputs, respectively.
Applications Flip-flop A: Binary counting (3 bits)
Applications Flip-flop B: Binary counting (4 bits) and frequency divider A 4-bit binary counter consisting of four negative edge-triggered toggle flip-flops connected in sequence. The four output bits Bi change according to the binary number counting sequence, counting from 0 to 15 (base 10) and returning back to 0. This circuit may also be used as a frequency divider. Output Bo is a divide-by-2 output since its frequency is 1/2 the input pulse train frequency. Bl, B2, and B3 are divide-by-4, -8, and -16 outputs, respectively.
Applications Flip-flop Series and Parallel Interfaces Series-to-parallel converter using negative-edge-triggered D flip-flop
Applications Flip-flop Series and Parallel Interfaces Parallel-to-Series converter using negative-edge-triggered JK flip-flop