Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals, the counter can be used as an instrument for measuring time and therefore period and frequency.there are two types of counters: synchronous and asynchronous. All processors contain a program counter, or PC. Programs consist of a list of instructions that are to be executed one after another (for the most part). The PC keeps track of the instruction currently being executed. The PC increments once on each clock cycle, and the next program instruction is then executed. Counters could be serial or parallel counters or combination of both. Counters could be asynchronous or synchronous counters. Counters operate in Count up mode Count down mode When counters are cleared, then all the flip flops are cleared and they contain zero. Counter are preset such that the contents of the flip flop represent any desired binary number. Asynchronous counter Events that do not have fixed time relationship with each other and generally, do not occur at the same time.
Asynchronous Counter is a digital circuit in which flip-flops (FF) within the counter do not change states at exactly the same time because they do not have a common clock pulse. When the output of a flip-flop is used as the clock input for the next flip-flop, we call the counter a ripple counter, or asynchronous counter. A binary ripple counter can be constructed using clocked JK flip-flops. 4Bit Asynchronous Binary Counter An Application Specific Integrated Circuit (ASIC) dedicated for 4 Bit Asynchronous Binary Counting. It has 4 internal JK FFs. A 2 Input NAND Gate for clearing all FFs. The 2 Input NAND Gate can be wired to the Q1 and Q3 to form a Modulus 12 counter
7493A 2 reset inputs are active low. High at both the reset inputs resets all flip flops simultaneously. This will occur regardless of the clock.
Decoding Gates: A decoding gate can be connected to the outputs of a counter in such a way that the output of the gate will be high (or low) only when the counter contents are equal to a given state. Synchronous Counters: Events that have fixed time relationship with each other and generally, occur at the same time. Digital Circuit s clock inputs are all wired together. With all clock inputs wired together, propagation delay is assumed to be equal. Propagation Delay occurs from the triggering edge of the input clock pulse. Each FF s Q-outputs toggle simultaneously Response time for a Synchronous counter is faster than Asynchronous circuit. A 2 Bit Binary Synchronous Counter can be built quite easily.
The flip-flop delay time and possibility of glitches are overcome by the use of a synchronous or parallel counter. Every flip-flop is triggered in synchronism with the clock. 2Bit binary synchronous counter The flip-flop delay time and possibility of glitches are overcome by the use of a synchronous or parallel counter. Every flip-flop is triggered in synchronism with the clock.
Changing the counter modulus Counters are said to have a natural count of 2 n. A counter having a modulus of 3 or 5 would be useful and such counters are said to have a modified count.
Decade Counters A Mod-5 counter: A MOD-10 Counter A 2x5 or a 5x2 will form a mod-10 counter, or a decade counter.
UP/DOWN 3 BIT SYNCHRONOUS COUNTER An Up/Down 3 Bit Counter is capable of progressing in either direction through a certain sequence. An Up/Down Counter is also known as bidirectional counter. A 3 Bit Binary counter advances upward in sequence (0,1,2,3,4,5,6,7). It advances downward in reverse sequence (7,6,5,4,3,2,1,0). The counter advances to next output state on the positive edge of the input clock.
Presettable Counters A basic 3-bit up/down synchronous counter
The 74HC/HCT163 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP).The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). For the 163 the clear function is synchronous. A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for MR are met). This action occurs regardless of the levels at PE, CET and CEP inputs. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage.
Synchronous Up-Down counter: Counter design as a synthesis problem Let us try to design a modulo-6 counter, the counting states (memory values) of which are shown in state transition diagram. We need three memory element or flip-flops for this as with n flip-flop we can get at most 2n number of different counting states. 000 101 001 100 010 011
Our next objective is to get logic equation for each flip-flop input as a function of present state of the counter. C n B n A n 0 0 0 1 1 1 1 0 C n B n A n 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 J C = A n K C = A n C n B n A n 0 0 0 1 1 1 1 0 C n B n A n 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 00 1 _ J B = C n A n K B = A n
The final step is to draw the circuit diagram from the design equations, which is shown. 1 J A A J B B J C C 1 K A _ A 1 K B _ B K C _ C CLK Y