hilips emiconductors rogrmmle Logic Devices equencer devices INTODUTION Ten yers go, in their serch for strightforwrd solution to complex sequentil prolems, hilips emiconductors originted rogrmmle Logic equencers. hilips emiconductors rogrmmle equencers represent product line which comines the verstility of two progrmmle rrys (LA concept) with flip-flops, to chieve powerful stte mchine rchitectures. ch rrngement or rchitecture offers vrition of the sic concept which comines two progrmmle logic rrys with some flip-flops, in n undedicted fshion. The LA product terms re not specificlly dedicted to ny prticulr flip-flop. All, none, or ny mix in etween my e connected to ny flip-flop the designer chooses. The LA structure therefore supports 100% product term-shring s well s very wide O functions preceding the flip-flops. hilips emiconductors line of rogrmmle Logic equencers hs een further customized to ccommodte specific types of stte mchine designs. ome hve oth registered nd comintoril outputs, specificlly for synchronous nd synchronous Moore-type stte mchines. Others hve stte or uried registers, s well s output registers. These devices (LU105, L42VA12 nd LU405) re idel for synchronous Mely-type pplictions. J-K nd - register functions re nother enefit. The logic functions provided y these types of registers fr exceed the cpility of D-type register. The functionlity of the J-K llows the designer to optimize the logic used in generting stte trnsitions. Ninety percent of AL devices hve D-type registers. All the sequencers re equipped with three stte options for ussing opertions, JK or flip-flops nd some form of register reset/eset functions. inlly, ll L devices hve Trnsition omplement Arry. This synchronous feedck pth, from the O rry to the AND rry, genertes complement trnsition functions using single term. Virtully hidden in etween the AND rry nd the O rry is the omplement Arry. This single NO gte is not necessrily n rry, however the inputs nd outputs of this complement gte spn the entire AND rry. The input(s) to the omplement Arry cn e ny of the product terms from the AND rry. The output of the omplement Arry will e the complement of the product term input. If severl product terms re connected to the omplement Arry, their respective complements cn lso e generted. The output of the omplement Arry is fed ck to the AND rry, wherey it cn e logiclly gted through nother AND gte nd finlly propgted to the O rry. The significnce eing tht the complement stte of severl product terms cn e generted using one dditionl AND product term. or exmple, if n efficient method of sensing tht no inputs were sserted ws needed, the designer could connect the output of pproprite AND gtes to the complement NO gte. The output of the NO gte could then e used to condition nd then set or reset flip-flop ccordingly. As well, he could detect prticulr stte vrile comintion nd force trnsition to new stte, independent of the inputs. Or he could comine input signls nd stte (AND) terms to generte new composite term. In ny of these pplictions, the omplement Arry gretly reduces the numer of stte trnsition terms required. In order to present the mteril in the most concise fshion, rief stte eqution tutoril is presented first. The LU105 description immeditely follows. In this cpsule description, the level of detil is expnded, so red it first for sic understnding. ch dditionl presenttion will e done with regrd to the fundmentls descried for the LU105. igure 3 shows the detiled drwing of the LU105 in full detil. igure 4 shows compressed rendition of the sme digrm so tht the reder cn understnd the digrm nottion. The compressed shorthnd version will e used for the rest of the sequencers. U 0 U While [TAT 0] I [U] THN [TAT 1] I [/D] THN [TAT 3] 3 D D 1 While [TAT 1] I [U] THN [TAT 2] I [/D] THN [TAT 0] D D While [TAT 2] I [U] THN [TAT 3] I [/D] THN [TAT 1] U 2 U When [TAT 3] I [U] THN [TAT 0] I [/D] THN [TAT 2] igure 1. Up-Down ounter tte Digrm igure 2. TAT UATION to Implement Up-Down ounter for JK or Type lip-lop Bsed equencer Octoer 1993 1
hilips emiconductors rogrmmle Logic Devices equencer devices tte qution Tutoril TAT eqution entry is convenient wy to descrie elementry sequentil mchines in mnner which is directly relted to stte digrm of the mchine. The sic commnds re few, ut cn e comined in powerful fshion. igure 1 shows 4 stte up-down counter for mchine with n U(up)/D(down) input line. igure 2 shows the stte eqution syntx to implement igure 1. The sic mening cn e summrized in the following wy. imply, while in stte X if input Y occurs, trnsverse to stte Z. This is Moore mchine model. Mely my e ccommodted y ddition of the with opertion which designtes n output vrile eing ssocited s shown elow: A.) While or B.) While with I then I then with [UNT TAT] [OUTUT VAIABL] [INUT VAIABL] [NXT TAT] [UNT TAT] [INUT VAIABL] [NXT TAT] [OUTUT VAIABL] If ltched output vrile is desired, the ddition of prime notion (/) to the right of the output vrile is required. The designer must ssign the inry vlues of choice to specific sttes for stte eqution function to e implemented. The hilips emiconductors NA mnul detils stte eqution solutions with more exmples, ut the dvntge of stte equtions is tht the designer cn e less involved with the internl structure of the sequencer thn required y other methods. The LU105 This prt (igure 3) hs sixteen logic inputs nd eight outputs. It lso hs eight - flip-flops tied directly to those output pins through 3-tte uffers (common control from pin 19). The user my select pin 19 to e n Output nle signl or n synchronous preset () signl which is common to ll flip-flops. medded into the device re 48 AND gtes. All flip-flops re - type with n O gte on oth nd. The designer my choose ny numer of product terms nd connect them with ny O gte. The product terms cn lso e shred cross ny O gte, s needed. ix of the 14 flip-flops re termed uried registers s their outputs re fed ck to the AND rry, regenerting oth the nd / stte vriles. There is no direct connection to n output. Both the input signls nd the stte vriles nd / re fed to the AND rry through uffers which provided the TU (or noninverted) nd omplement (inverted) renditions of the vrile. This is criticl for the efficient use of the AND rry. The designer hs ll stte nd input vriles necessry to generte ny stte trnsition signl to set nd/or reset commnds to the flip-flops. Becuse of this AND/O rrngement, comined with complete freedom of configurtion, ll sequentil design optimiztion methods re pplicle. There re mny other feture cpilities suitle for cretive usge. or exmple, it is common prctice to use the 48 product terms with the 6-it uried register, treting the output 8-it register s n intermedite, lodle dt register only. This provides very good us pipeline for the internl 6-it mchine. However, other logic options cn e ccomplished y comining internl stte informtion (present stte) with current input informtion, generting next stte which is different from the current internl stte. Octoer 1993 2
hilips emiconductors rogrmmle Logic Devices equencer devices (LOGI TM T) (OTION) I 0 I 1 I 2 9 8 7 19 /O I 3 6 I 4 5 I 5 4 I 6 3 I 7 I 8 I 9 I 10 I 11 I 12 I 13 I 14 I 15 2 27 26 25 24 23 22 21 20 I 0 1 2 3 4 5 0 1 2 N 3 4 5 18 0 17 1 16 2 15 3 13 4 12 5 11 6 10 7 47 40 39 32 31 24 23 16 15 8 7 0 1 K igure 3. LU105 Octoer 1993 3
hilips emiconductors rogrmmle Logic Devices equencer devices I 16 /O TAT G. (6) (8) 8 T 47 T 0 OUTUT G. LK igure 4. ompressed Drwing of LU105 Octoer 1993 4
hilips emiconductors rogrmmle Logic Devices equencer devices The L155, 157, nd 159A constitute three prt fmily of 20-pin sequencers tht re well suited for high speed hndshkers, counters, shift registers, pttern detectors nd sequence genertors. Additionl pplictions include testility enhncement, demonstrted in the ppliction exmples of signture nlysis nd pseudo rndom numer genertion. The three devices re very similr in rchitecture. All hve totl of 12 possile outputs. The difference is the rtio of comintionl I/O to registered outputs ville. The L155 The L155 is sequencer providing four J-K flip-flops with LA hving 32 logic product terms nd 13 control product terms. ight comintionl I/O re ville in ddition to the four registered outputs. All of the stte vriles nd comintionl vriles re presented to the output pins y wy of 3-tte inverting uffers. The comintionl nd stte vrile outputs re fully connected (fed ck) ck to the AND rry in oth the True nd omplemented form of the vrile. The product includes specil feture tht llows the user to configure the flip-flops s either J-K or D flip-flops on n individul sis. A egister relod feture is supported vi two product terms (L, L) which permit ck loding of dt into the flip-flops, directly from the output pins. The prt cn now e esily forced into ny known stte y enling L, L, pplying dt t the outputs (previously 3-tted ), nd pplying clock pulse. egister reset nd eset functions re controlled in 2 nks of 2 registers ech. Note tht control product terms re from the O rry. The outputs of ll vriles re 3-tte controlled y unique prtition. in 11 provides n Output nle input (O) which cn e sserted with the A nd B control product terms. A controls the flip-flops 0 nd 1, nd B controls 2 nd 3. ch comintionl output term hs distinct 3-tte control term (D0 - D7) originting from the AND rry of the LA. ch comintionl output vrile cn e progrmmed s inverting (ctive LOW) or non-inverting (ctive HIGH) y wy of the output polrity X-O gte ssocited with ech I/O pin. (LOGI TM) (ONTOL TM) L D O 2 opies X 8 opies B M J (n) K K T 31 T 0 4 opies igure 5. L155 Architecture Octoer 1993 5
hilips emiconductors rogrmmle Logic Devices equencer devices The L157 This sequencer fetures ll the ttriutes of the forementioned L155, however, two flip-flops hve een dded, t the expense of two of the comintionl outputs. ins 13 nd 18 on the L157 re flip-flop driven, where the sme pins on the L155 re comintoril, driven from the LA. Agin, ll vriles (input, output, or stte vriles) fully connect over the LA portion with oth True nd complemented versions supplied. The numer of product terms, the omplement rry, Output nle, 3-tte configurtions, egister relod, etc., trck the L155 prt. As with the L155, distinct clock input on pin 1 is provided for synchronous opertion. egister reset nd eset re ville in 2 nks. in 4 nd 5 re controlled from the AND rry (roduct Terms B nd B ). The remining 4 registers, 0-3, re controlled y the sum terms (from the O rry) A nd A. Designs requiring more thn 16 sttes ut less thn or equl to 64 sttes re solid cndidtes for reliztion with the L157. It cn e configured s Moore mchine for counter nd shifter designs from the flip-flop outputs, or s high speed pulse genertors or sequence detectors with the comintionl outputs. Mixed solutions re lso possile. (LOGI TM) (ONTOL TM) L L D O X B M J (n) K K M J (n) K K T 31 T 0 igure 6. L157 Architecture Octoer 1993 6
hilips emiconductors rogrmmle Logic Devices equencer devices The L159A By extending the L157 rrngement even further, the L159A cn e derived. Agin, mintining identicl input, product terms, omplement rry nd similr 3-tte prtitioning, the L159A lso resides in 20-pin pckge. The expnsion to dul 4-it nks of flip-flops, t the expense of 2 comintionl outputs, enhnces the numer of ville internl sttes while mintining product term nd pin comptiility. Note tht ll registers re controlled from the AND rry in 2 groups of four. The L159A is n octl prt. It redily enters the environment of the 8-it dt opernd s well s the us oriented system. or enhnced performnce, the flip-flop outputs re inverted. To provide positive outputs for shifters nd counters, the input vriles nd stte feedck vriles cn e selectively inverted through n input receiver or the feedck pth through the AND gte rry. (LOGI TM) (ONTOL TM) O 2 opies X 4 opies B M J (n) K K T 31 T 0 8 opies igure 7. L159A Architecture Octoer 1993 7
hilips emiconductors rogrmmle Logic Devices equencer devices There re three sic memers in the 24-pin pckge fmily: The L167A, the L168A, nd the L179. The L42VA12 is discussed elsewhere. The L167A The L167A hs 14 logic inputs nd six registered outputs (- flip-flops). ix dditionl uried flip-flops reside eside the 48 product term AND rry. This device cn support stte mchine designs of up to 256 sttes s two outputs feed ck into the AND rry, mking totl of eight uried registers. There is complete feedck connectivity of the inputs nd the stte flip-flop outputs to the LA AND gtes. Orgniztionlly it hs much more in common with the L105A thn the forementioned 20-pin prts. The synchronous reset nd the Output nle re identicl to the L105A. By hving the output ltched stte vrile cpility, it provides n utomtic uffer for us sed systems. The current stte my e presented, fully stle nd synchronized to us while the internl uried mchine is trnsitioning to the next stte sed on current input conditions. I M /O TAT G. (6) (2) (4) OUTUT G. T 47 T 0 K igure 8. L167A Octoer 1993 8
hilips emiconductors rogrmmle Logic Devices equencer devices The L168A This sequencer is down-scled version of the L105A. Hving identicl product terms, omplement rry, synchronous T/Output nle options, nd 3-tte controls, its primry difference is hving 12 inputs compred to the L105A s 16 inputs. However, the L168A cn ecome stte mchine of up to 1024 sttes due to internl feed ck of its six stte registers, plus the feedck of four of the eight output registers. The L168A is pckged in 300mil-wide 24-pin DI or 28-pin L. This is lso n octl prt, providing n 8-it register to us sed system. tte registers, interrupt vector synchronizers, counters, shifters, or just out ny sic stte mchine cn e generted nd 3-tte interfced to computer us with L168A. Outputs provided y the positive sserted sense mke stte trnsitioning nd loding of stte vriles strightforwrd. I M /O TAT G. (6) (4) (4) OUTUT G. T 47 T 0 K igure 9. L168A Octoer 1993 9
hilips emiconductors rogrmmle Logic Devices equencer devices The L179 The L179 is rchitecturlly similr to the L159A. The 3-tte enle, numer of product terms, flip-flop mode controls, register prelod, etc., re ll identicl to the L159A. The four dditionl inputs re the dominnt differentiting feture for this prt s compred to the L159A. As with the L159A, the L179 reset nd eset functions re controlled from the AND rry in 2 groups of 4 registers ech. The L179 is lso n octl prt. roviding the stte contents directly to the pin through 3-tte uffers llows counters nd other sequence genertors direct ccess to n sserted low octl us. ome design cretivity will generte positive ssertion through the pin inverters, for positive driven usses. Additionl input pins expnd the cpility of the prt eyond the L159A. Input comintions my e presented in wider formt, more fully decoded to the sequencer for fster rection nd less externl circuitry thn the L159A requires. O 0 31 I 0 I 7 8 4 B 4 4 opies 2 opies J 8 K 8 opies LK igure 10. L179 Architecture Octoer 1993 10
hilips emiconductors rogrmmle Logic Devices equencer devices The LU405 The LU405 is functionl superset of the LU105. It is lso much fster. The performnce of the LU405 hs een drmticlly improved reltive to the L105A. Aville in two speed versions, the operting frequencies ( 1 /t I + t KO ) rnge from 37 to 45MHz (minimum gurnteed frequency). The clock frequencies, or toggle rte of the flip-flops, re 50MHz nd 58.8MHz, respectively. The LU405 hs 16 more product terms nd two more uried stte registers thn the LU105. quipped with two independent clocks, it is prtitionle into two distinct stte mchines with independent clocks. And, it contins two independent omplement rrys, llowing full enefits over oth mchines. The LU405 cn e prtitioned s one lrge stte mchine (16s) with 64 ville p-terms using one clock nd 16 inputs or lterntely two stte mchines (8s ech) with independent clocks, shring 64 p-terms with 15 inputs in ny comintion the user desires. The omplement rrys cn e used to generte the else trnsition over ech stte mchine or lterntely used s NO gtes. They cn e coupled into ltch if needed. The Asynchronous reset option of the L105/167/168 rchitectures hs een replced with rogrmmle Initiliztion feture. Insted of reset to ll logic 1 s, the user cn customize the reset/eset pttern of ech individul register. When the INIT pin (in 19) is rised to logic 1, ll registers re preset/or reset. The clocks re inhiited (locked out) until the INIT signl is tken Low. Note tht in 19 lso controls the O function. ither Initiliztion or O is ville, ut not oth. A MO extension to the LU405 is hilips emiconductors L415, which is pin comptile nd functionl superset of the LU405 rchitecture. Octoer 1993 11
hilips emiconductors rogrmmle Logic Devices equencer devices I0 0 63 I14 I/LK 7 0 LU405 ircuitry with dshed line is replicted four times. (16 JK flip-flops) J K J K 4 OI J K J 7 K 0 K INIT/O The uture is Here Now. ecent rchitecturl extensions re currently ville from hilips emiconductors. These include the L415 nd L42VA12. These igure 11. LU405 new uper equencers re ville now for high-end new designs. lese check the dt sheet section of this hndook for more informtion. ee lso the MO equencers section for more design exmples using the L415 nd the L42VA12. Octoer 1993 12