65OM / 128 EG DRIVER & ONTROLLER FOR TN LD July 2001 Ver. 0.0 ontents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LD Driver I Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. onsequently, the users of the packages which may expose chips to external light such as OB, OG, TP and OF must consider effective methods to block out light from reaching the I on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. onsider and verify the protection of penetrating light to the I at substrate (board or glass) or product design stage. 2. Always test and inspect products under the environment with no penetration of light.
65 OM / 128 EG DRIVER & ONTROLLER FOR TN LD PRELIMINARY PE. VER. 1.0 6B0755 pecification Revision History Version ontent Date 0.0 Original July.2001 2
6B0755 PRELIMINARY PE. VER. 1.0 65 OM / 128 EG DRIVER & ONTROLLER FOR TN LD ONTENT INTRODUTION...! BLOK DIAGRAM...! PAD ONFIGURATION...! PAD ENTER OORDINATE...! PIN DERIPTION...! POWER UPPLY...! LD DRIVER UPPLY...! YTEM ONTROL...! MIROPROEOR INTERFAE...! LD DRIVER OUTPUT...! FUNTIONAL DERIPTION...! MIROPROEOR INTERFAE...! DIPLAY DATA RAM (DDRAM)...! LD DIPLAY IRUIT...! LD DRIVER IRUIT...! POWER UPPLY IRUIT...! REFEREE IRUIT EXA MPLE...! REET IRUIT...!. INTRUTION DERIPTION...! PEIFIATION...! ABOLUTE MAXIMUM RATING...! D HARATERITI...! A HARATERITI...! REFERENE APPLIATION...! MIROPROEOR INTERFAE...! ONNETION BETWEEN 6B0755 AND LD PANEL...! 3
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD INTRODUTION The (TQFP type: 6B2086) is a LD driver LI which is fabricated by low power MO high voltage process technology. In segment driver mode, it can be interfaced in 1-bit serial or 4-bit parallel method by the controller. In common driver mode, dual type mode is applicable. And in segment mode application, the power down function reduces power consumption. FEATURE Power supply voltage: + 5V ± 10 %, + 3V ± 10% upply voltage for display: 6 to 28V (V DD -V EE ) 4-bit parallel/1-bit serial data processing (in segment mode) ingle mode operation/dual mode operation (in common mode) Power down function (in segment mode) Applicable LD duty: 1/64 1/256 Interface OM (cascade) Drivers EG (cascade) High voltage MO process Available PKG type: bare die, 100 QFP, 100 TQFP or TP 4
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD 5 PAKAGE INFORMATION PKG TYPE 100QFP Package (100-QFP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VEE V5 V43 V12 V0 M DIP0FFB VDD V D3_DM D1_ID L2 30 29 28 27 26 25 24 23 22 21 20 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD 6 TP TYPE TP N N N 8 0 7 9 7 8 7 7 7 6 7 5 7 4 ---------------- 7 6 5 4 3 2 1 N N N E R B V E E V 5 V 4 3 V 1 2 V 0 M D I P 0 F F B V D D H L V D 4 - D R D 3 - D M D 2 - D L D 1 - I D L 2 A M L 1 E L B #1 #20 * Package Type = 100-TP-35mm * Input Lead Pitch = 0.80mm * Output Lead Pitch = 0.22mm
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD 7 PAD DIAGRAM (/ TP) hip size: 4530 4390 Pad size: 98 98 Unit: µm (0, 0) X Y 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 29 28 27 26 25 24 23 22 21 20 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VEE V5 V43 V12 V0 M DIPOFFB VDD V D3_DM D1_ID L2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD PAD ENTER OORDINATE (/TP) Pad Pad oordinates Pad Pad oordinates Pad Pad oordinates No. Name X Y No. Name X Y No. Name X Y 1 51-1690 1959 35 V12-900 -1959 69 9 2029 544 2 52-2029 1884 36 V0-775 -1959 70 20 2029 678 3 53-2029 1750 37 V -600-1959 71 21 2029 812 4 54-2029 1616 38 M -475-1959 72 22 2029 946 5 55-2029 1482 39 DIP0FFB -350-1959 73 23 2029 1080 6 56-2029 1348 40 VDD -225-1959 74 24 2029 1214 7 57-2029 1214 41-100 -1959 75 25 2029 1348 8 58-2029 1080 42 V 25-1959 76 26 2029 1482 9 59-2029 946 43 266-1959 77 27 2029 1616 10 60-2029 812 44 D3_DM 470-1959 78 28 2029 1750 11 61-2029 678 45 711-1959 79 29 2029 1884 12 62-2029 544 46 D1_ID 915-1959 80 30 1690 1959 13 63-2029 410 47 L2 1040-1959 81 31 1529 1959 14 64-2029 276 48 1165-1959 82 32 1368 1959 15 65-2029 142 49 1290-1959 83 33 1207 1959 16 66-2029 8 50 1496-1959 84 34 1046 1959 17 67-2029 -126 51 2029-1884 85 35 885 1959 18 68-2029 -260 52 2 2029-1735 86 36 724 1959 19 69-2029 -394 53 3 2029-1601 87 37 563 1959 20 70-2029 -528 54 4 2029-1467 88 38 402 1959 21 71-2029 -662 55 5 2029-1333 89 39 241 1959 22 72-2029 -797 56 6 2029-1199 90 40 80 1959 23 73-2029 -931 57 7 2029-1065 91 41-80 1959 24 74-2029 -1065 58 8 2029-931 92 42-241 1959 25 75-2029 -1199 59 9 2029-797 93 43-402 1959 26 76-2029 -1333 60 0 2029-662 94 44-563 1959 27 77-2029 -1467 61 1 2029-528 95 45-724 1959 28 78-2029 -1601 62 2 2029-394 96 46-885 1959 29 79-2029 -1735 63 3 2029-260 97 47-1046 1959 30-2029 -1884 64 4 2029-126 98 48-1207 1959 31-1479 -1959 65 5 2029 8 99 49-1368 1959 32 VEE -1275-1959 66 6 2029 142 100 50-1529 1959 33 V5-1150 -1959 67 7 2029 276 34 V43-1025 -1959 68 8 2029 410 8
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD 9 TQFP TYPE (6B2086) 100TQFP 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 6B2086 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 27 26 25 24 23 22 21 20 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 2 L2 D1_ID D3_DM V VDD DIP0FFB M V0 V12 V43 V5 VEE 79 78
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD 10 PAD DIAGRAM (6B2086) 6B2086 hip size: 4410 x 4600 Pad size: 98 x 98 Unit: µm (0, 0) X Y 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 27 26 25 24 23 22 21 20 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 51 52 53 54 61 63 60 64 65 62 66 67 68 73 55 57 59 58 56 72 71 69 70 75 74 78 79 VEE V0 V12 V43 V5 V VDD DIPOFFB M D3_DM D1_ID L2 2
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD PAD ENTER OORDINATE (6B2086) Pad Pad oordinates Pad Pad oordinates Pad Pad oordinates No. Name X Y No. Name X Y No. Name X Y 1 28-1969 1691 35 62-515 -2064 69 D1_ID 1969 924 2 29-1969 1551 36 63-390 -2064 70 L2 1969 1049 3 30-1969 1411 37 64-265 -2064 71 1969 1174 4 31-1969 1271 38 65-140 -2064 72 1969 1299 5 32-1969 1131 39 66-15 -2064 73 1969 1504 6 33-1969 991 40 67 110-2064 74 1969 1904 7 34-1969 851 41 68 235-2064 75 2 1969 2029 8 35-1969 711 42 69 360-2064 76 3 1360 2064 9 36-1969 571 43 70 485-2064 77 4 1235 2064 10 37-1969 431 44 71 610-2064 78 5 1110 2064 11 38-1969 291 45 72 735-2064 79 6 985 2064 12 39-1969 151 46 73 860-2064 80 7 860 2064 13 40-1969 11 47 74 985-2064 81 8 735 2064 14 41-1969 -151 48 75 1110-2064 82 9 610 2064 15 42-1969 -291 49 76 1235-2064 83 0 485 2064 16 43-1969 -431 50 77 1360-2064 84 1 360 2064 17 44-1969 -571 51 78 1969-2029 85 2 235 2064 18 45-1969 -711 52 79 1969-1904 86 3 110 2064 19 46-1969 -851 53 1969-1779 87 4-15 2064 20 47-1969 -991 54 1969-1475 88 5-140 2064 21 48-1969 -1131 55 VEE 1969-1270 89 6-265 2064 22 49-1969 -1271 56 V5 1969-1145 90 7-390 2064 23 50-1969 -1411 57 V43 1969-1020 91 8-515 2064 24 51-1969 -1551 58 V12 1969-895 92 9-640 2064 25 52-1969 -1691 59 V0 1969-770 93 20-765 2064 26 53-1640 -2064 60 1969-595 94 21-890 2064 27 54-1515 -2064 61 M 1969-470 95 22-1015 2064 28 55-1390 -2064 62 DIP0FFB 1969-345 96 23-1140 2064 29 56-1265 -2064 63 VDD 1969-220 97 24-1265 2064 30 57-1140 -2064 64 1969-95 98 25-1390 2064 31 58-1015 -2064 65 V 1969 30 99 26-1515 2064 32 59-890 -2064 66 1969 272 100 27-1640 2064 33 60-765 -2064 67 D3_DM 1969 477 34 61-640 -2064 68 1969 719 11
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD BLOK DIAGRAM 2 3 7879 V0 V12 V43 80-bit 4-level Driver V5 VEE 80-bit Driver DIP0FFB M Output Level elector D1_ID LK 80-bit Data Latch/ ommon Data bi-directional hift Register D3_DM K 20 x 4-bit egment Data bi-directional hift Register L2 lock ontrol Data Latch ontrol Power Down Function VDD V 12
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD BLOK DERIPTION Name Function OM/EG lock control Data latch control Power down function Output level selector 20x4-bit segment data I- directional shift register 80-bit data latch / common data I- directional shift register 80-bit level shifter 80-bit 4-level driver Generates latch clock (LK), shift clock (K) and control clock timing according to the input of, L2 and control inputs (, ). In common driver application mode, this block generates the shift clock (LK) for the common data Bi-directional shift register. Determines the direction of segment data shift, and input data of each Bi-directional shift register. In 4-bit segment data parallel transfer mode, data is shifted by a 4-bit unit. In common driver application mode, data is transferred to the common data shift register directly, which disables this block. ontrols the clock enable state of the current driver according to the input value of enable pin ( or ). If enable input value is Low, every clock of the current driver is enabled and the clock control block works. But if enable input is High, current driver is disabled and the input data value has no effect on the output level. o power consumption can be lowered. ontrols the output voltage level according to the input control pin (M and DIPOFFB) (refer to PIN DERIPTION). tores output data value by shifting the input values. In 1-bit serial interface mode application, all 80 shift clocks (K) are needed to store all the display data. But in 4-bit parallel transfer mode application, only 20 clocks are needed. In common driver application mode, this block does not work. In segment driver application mode, the data from the 20x4-bit segment data shift register are latched for segment driver output. In single-type common driver application,1-bit input data (from DL or DR pin) is shifted and latched by the direction according to the signal input. In dual-type common application mode, 80-bit registers are divided by two blocks and controlled independently (refer to NOTE 3). Voltage level shifter block for high voltage part. The inputs of this block are of logical voltage level and the outputs of this block are at high voltage level value. These values are input in to the driver. elects the output voltage level according to M and latched data value. If the data value is High the driver output is at selected voltage level (V0 or V5), and in the reverse case the driver output value is at the non-selected level (V12 or V43). In segment driver application mode, non-selected output value is V2 or V3. and when in common driver application, this value becomes V1 or V4. OM/EG EG EG OM/EG EG OM/EG EG EG 13
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD PIN DERIPTION Pin I/O Name Function Interface V0, V12, V43, V5 I LD driver output voltage level - O LD driver output L2 I Data shift clock M I A signal for LD driver output I Data latch clock DIPOFFB I Display OFF control I OM/EG mode control I Application mode select Bias supply voltage input to drive the LD. Bias voltage divided by the resistance is usually used as a supply voltage source (refer to NOTE 2). Display data output pin which corresponds to the respective latch contents. One of V0, V12, V34 and V5 is selected as a display driving voltage source according to the combination of the latched data level and M signal (refer to NOTE 1). lock pulse input for the bi-directional shift register. In segment driver application mode, the data is shifted to 20 x 4-bit segment data shift. The clock pulse, which was input when the enable bit (/) is in not active condition, is invalid. In common driver application mode, the data is shifted to 80-bit common data bi-directional shift register by the clock. Hence, this clock pin is not used (Open or connect this pin to VDD). Alternate signal input pin for LD driving. Normal frame inversion signal is input in to this pin. In segment driver application mode, this signal is used for latching the shift register contents at the falling edge of this clock pulse. pulse High level initializes power-down function block. In common driver application mode, is used as a shifting clock of common output data. ontrol input pin to fix the driver output () to V0 level, during Low value input. LD becomes non-selected by V0 level output from every output of segment drivers and every output of common drivers. When = Low, is used as an 80-bit segment driver. When = High, is set to an 80-bit common driver According to the input value of the and the pin, application mode of is differs as shown below. Power LD ontroller ontroller ontroller ontroller V DD /V V DD /V Apllication mode 0 0 4-bit Parallel Interface mode 0 1 1-bit erial Interface mode 1 0 ingle Type Application mode 1 1 Dual Type Application mode OM/EG EG OM 14
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD PIN DERIPTION (ONTINUED) Pin I/O Name Function Interface D1_ID,, D3_DM, I/O Display data input/serial input data/left, right data input output In segment driver application mode, these pins are used as 4-bit data input pin (when 4-bit parallel interface mode : = Low ), or D1_ID is used as serial data input pin and other pins are not used (connect these to V DD ) (when 1-bit serial interface mode : = High ). ontroller In common driver application mode, the data is shifted from () to (), when in single type interface mode ( = Low ). In dual-type application case, the data are shifted from and D3_DM ( and D3_DM) to (). In each case the direction of the data shift and the connection of data pins are determined by input (refer to NOTE 3, NOTE 4). Input hift direction control, I/O Enable data input/output When = Low, data is shifted from left to right. When = High, the direction is reversed. (refer to NOTE3) In segment driver application mode, the internal operation is enabled only when enable input ( or ) is Low (power down function). When several drivers are serially connected, the enable state of each driver is shifted according to the input. onnect these pins as below. V DD /V egment Driver L H Output (open) Input (V ) Input (V ) Output (open) In common driver application mode, power down function is not used. Open these pins. NOTE 1. Output Level ontrol M Latched data DIPOFFB Output level ( - ) EG Mode OM Mode L L H V12 (V2) V12 (V1) L H H V0 V5 H L H V43 (V3) V43 (V4) H H H V5 V0 X X L V0 V0 15
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD NOTE 2. LD Driving Voltage Application ircuit (1) egment driver application ( = Low ) VDD R R (n-4)r R R VDD V0 V1 V2 V3 V4 V5 VEE to OM Driver to OM Driver V0 V12 V43 V5 V EG1- EG80 V0, V5 V2, V3 to LD Panel election Level Non-selection Level * n = 9 (when 1/64 duty) to 17 (when 1/256 duty) (2) ommon driver application ( = High ) VDD R R (n-4)r VDD V0 V1 V2 V3 to EG Driver V0 V12 VDD OM1- OM80 to LD Panel R R V4 V5 VEE V43 V5 V V0, V5 V1, V4 election Level Non-selection Level * n = 9 (when 1/64 duty) to 17 (when 1/256 duty) 16
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD NOTE 3. Data hift Direction according to ontrol ignals (1) When = Low (segment driver application) Application Mode Data Direction Input Pin 2 3 4 73 74 75 76 77 78 79 L D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 L 4-Bit Parallel Data Transfer Mode (EG) D1 D2 D3 D4 Last Data 2 3 4 hift Direction First Data 73 74 75 76 77 78 79 D1_ID,, D3_DM H D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 First Data hift Direction D1 D2 D3 D4 Last Data 2 3 4 73 74 75 76 77 78 79 L H 1-Bit erial Data Transfer Mode (EG) Last Data (D1_ID) 2 3 4 hift Direction First Data 73 74 75 76 77 78 79 D1_ID H First Data hift Direction Last Data 17
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD (2) When = High (common driver application) Application Mode Data Direction hift Direction Input Pin 2 3 38 39 40 41 42 43 78 79 L L ingle-type Application Mode (OM) Input Data () hift Direction Output Data () 2 3 38 39 40 41 42 43 78 79 H Input Data () Output Data () hift Direction L 2 3 38 39 40 41 42 43 78 79, D3_DM H Dual-type Application Mode (OM) Input Data1 () Input Data2 (D3_DM) hift Direction Output Data () H 2 3 38 39 40 41 42 43 78 79, D3_DM Input Data () Input Data2 (D3_DM) Output Data1 () 18
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD NOTE 4. Usage of Data Pins OM/EG Application mode Data Interface Pin ( pin) ( pin) D1_ID D3_DM EG ( = Low ) OM ( = High ) 4-bit parallel interface mode ( = Low ) 1-bit serial interface mode ( = High ) X D1 (input) D2 (input2) D3 (input3) D4 (input4) X ID (input) onnect to V DD single-type application mode L open DL (input) Open DR (output) ( = Low ) H DL (output) DR (input) dual-type application mode ( = High ) L open DL (input1) DM (input2) DR (output2) H DL (output2) DM (input2) DR (input1) MAXIMUM ABOLUTE LIMIT haracteristic ymbol Value Unit Power upply Voltage V DD -0.3 to +7.0 V Driver upply Voltage V LD 0 to +30 Input Voltage V IN -0.3 to V DD + 0.3 Operating Temperature T OPR -30 to +85 torage Temperature T TG -55 to +150 NOTE: Voltage greater than above may do damage to the circuit. 19
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD ELETRIAL HARATERITI D HARATERITI (1) egment Driver Application (V = 0V, Ta = - 30 to +85 ) haracteristic ymbol Test ondition Min. Typ. Max. Unit Operating V DD 2.7 5.5 Voltage1 V LD V IN = V DD - V EE 6 28 V Input Voltage (1) V IH 0.8V DD V DD V IL 0 0.2V DD Output Voltage (2) V OH I OH = -0.4mA V DD -0.4 V Input Leakage urrent 1 (1) Input Leakage urrent 2 (3) V OL I OL = 0.4mA 0.4 I IL1 V IN = V DD to V -10 10 µa I IL2 V IN = V DD to V EE -25 25 On Resistance (4) R ON I ON = 100µA 2 4 kω upply urrent (5) I TBY f = 32kHz M = V V pin 100 µa I DD f = 32kHz V DD = 5V 5 ma f M = 80Hz V DD = 3V 2 I EE V DD = 5V 500 µa NOTE: 1. Applied to, L2,,, D1_ID -,, DIPOFFB, M,, pin 2., pin 3. V0, V12, V43, V5 pin 4. V LD = V DD - V EE, V0 = V DD = 5V, V5= V EE = -23 V V12 = V DD -2/n(V LD ), V43 = V EE +2/n(V LD ), n = 17 (1/256 duty, 1/17 bias) 5. V0 = V DD, V12 = 1.71V(V DD = 5V) or -0.06V (V DD = 3V), V43 = -19.71 V(V DD = 5V) or -19.94V (V DD = 3V), V5 = V EE = -23V, no-load condition (1/256 duty, 1/17 bias) 4-bit parallel interface mode I TBY : V DD = 5V, f L2 = 5.12MHz, = V, DIPOFFB = V DD, M = V, display data pattern = 0000 I DD : V DD = 3V, f L2 = 4MHz, display data pattern = 0101 V DD = 5 V, f L2 = 5.12MHz, display data pattern = 0101 I EE : V DD = 5V, f L2 = 5.12MHz, display data pattern = 0101, V EE pin 20
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD D HARATERITI (ONTINUED) (2) ommon Driver Application (V = 0V, Ta = - 30 to +85 ) haracteristic ymbol Test ondition Min. Typ. Max. Unit Operating V DD 2.7 5.5 V Voltage V LD V IN = V DD V EE 6 28 Input Voltage (1) V IH 0.8V DD V DD V IL 0 0.2V DD Output Voltage (3) V OH I OH = -0.4mA V DD 0.4 V Input Leakage urrent 1 (1) Input Leakage urrent (2) Input Leakage urrent 3 (4) V OL I OL = 0.4mA 0.4 I IL1 V IN = V DD to V -10 10 µa I IL2 V IN = 0V, V DD = 5V (PULL UP) -50-125 -250 I IL3 V IN = V DD to V EE -25 25 On Resistance (5) R ON I ON = 100µA 2 4 kω upply urrent (6) I TBY f = 32Khz V pin 100 µa I DD f = 32kHz V DD = 5V 200 f M = 80Hz V DD = 3V 120 I EE V DD = 5V 150 NOTE: 1. Applied to, ( = LOW), ( = HIGH),, DIPOFFB, M,, pin 2. Pull-up input pins : L2, D1_ID, D3_DM ( = HIGH), ( = LOW), ( = HIGH) 3. ( = HIGH), ( = LOW) pin 4. V0, V12, V43, V5 pin 5. V LD = V DD -V EE, V0 = V DD = 5V, V5 = V EE = -23V V12 = V DD -1/n(V LD ), V43 = V EE +1/n(V LD ), n = 17(1/256 duty, 1/17 bias) 6. V0 = V DD, V12 = 3.35V (V DD = 5V) or 1.47V (V DD = 3V), V43 = -21.35V (V DD = 5 V) or -21.47V (V DD = 3 V), V5 = V EE = -23 V, no-load condition (1/256 duty, 1/17 bias) single-type mode operation : = V, = V, DIPOFFB = V DD D1_ID = D3_DM = V DD, = OPEN, = = OPEN, I TBY : V DD = 5V, M = V, = V I DD : f M = 80Hz, = V DD V DD = 3 V, display data pattern = 10000000..., 01000000..., 00100000..., 00010000...,.. V DD = 5 V, display data pattern = 10000000..., 01000000..., 00100000..., 00010000...,.. I EE : f M = 80Hz, = V DD V DD = 5V, current through V EE Pin, display data pattern = 10000000..., 01000000..., 21
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD 00100000..., 00010000... A HARATERITI (1) egment Driver Application (V = 0V, Ta = - 30 to +85 ) haracteristic ymbol Test (1) V DD = 5V 10% (2) V DD = 3V 10% Unit ondition Min. Typ. Max. Min. Typ. Max. lock cycle time t Y Duty = 50% 125 250 ns lock pulse width t WK 45 95 lock rise/fall time t R /t F 30 Data set-up time t D 30 65 Data hold time t DH 30 65 lock set-up time t 80 120 lock hold time t H 80 120 Propagation delay time t PHL Output 60 125 Output 60 125, set-up time t PU Input 30 65 DIPOFFB low pulse width Input 30 65 t WDL 1.2 1.2 µs DIPOFFB clear time t D 100 100 ns M - OUT propagation delay time - OUT propagation delay time DIPOFFB - OUT propagation delay time t PD1 L = 15pF 1.0 1.2 µs t PD2 1.0 1.2 t PD3 1.0 22
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD A HARATERITI (ontinued) (2) ommon Driver Application (V = 0V, Ta = - 30 to +85 ) haracteristic ymbol Test (1) V DD = 5 V 10% (2) V DD = 3V 10% Unit ondition Min. Typ. Max. Min. Typ. Max. lock cycle time t Y Duty = 50% 250 500 ns lock pulse width t WK 45 95 lock rise/fall time t R /t F 50 50 Data set-up time t D 30 65 Data hold time t DH 30 65 DIPOFFB low pulse width t WDL 1.2 1.2 µs DIPOFFB clear time t D 100 100 ns Output delay time t DL L = 15pF 200 250 M OUT propagation delay time - OUT propagation delay time DIPOFFB - OUT propagation delay time t PD1 1.0 1.2 µs t PD2 1.0 1.2 t PD3 1.0 1.2 23
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD A HARATERITI (ontinued) (3) egment Driver Application Timing 0.8VDD 0.2VDD t WK 0.8VDD 0.2VDD t t H L2 0.8VDD 0.8VDD 0.2VDD t WK tf t WK 0.2VDD 0.8VDD 0.2VDD D1_ID - t R t Y t D t DH 0.8VDD 0.2VDD t WDL t D DIP0FFB L2, (Output 1) 1 2 3 19 20 0.2VDD t PHL 0.2VDD 0.8VDD, (Input 2) 0.2VDD t PU M 0.8VDD 0.2VDD t PD1 0.2VDD t PD2 DIPOFFB 0.8VDD 0.2VDD t PD3 - (Latched Data) 24
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD A HARATERITI (ontinued) (4) ommon Driver Application Timing t Y 0.8VDD 0.2VDD t R t DWKH t F 0.8VDD 0.2VDD t F t D t DH (*1) DI 0.8VDD 0.2VDD 0.8VDD 0.2VDD t DL (*1) DO 0.8VDD twdl t D 0.2VDD DIP0FFB (*1) When in ingle-type Interface Mode DI => ( = L), ( = H) DO => ( = L ), ( = H) When in Dual-type Interface Mode DI => and D3_DM ( = L), and D3_DM ( = H) DO => ( = L), ( = H) M 0.8VDD 0.2VDD t PD1 0.2VDD t PD2 DIPOFFB 0.8VDD 0.2VDD t PD3 - (Latched Data) 25
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD POWER DOWN FUNTION In the case of cascade connection of segment mode drivers, has a power down function In order to reduce the power consumption. Enable input Enable output urrent driver status The other drivers status L While = Low, current driver is enabled. H While = Low, current driver is enabled. Disabled Disabled NOTE: In the case of common driver application, power down function does not work. L2 1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1 1(input1) 1/2 (Output1/Input2) 2/3 (Output2/Input3) 3/4 (Output3/Input4) 4 (Output4) NOTE: 1. = High ( = Input, = Output) urrent 's must be connected to the next 's. 2. When in 4-bit parallel interface mode: n = 20 When in 1-bit serial interface mode: n = 80 26
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD OPERATION TIMING DIAGRAM (1) 4-bit Parallel Mode Interface egment Driver When = Low L2 D1_ID 19 20 1 2 3 5 77 73 69 19 20 1 2 5 77 73 D3_DM 6 2 78 74 70 6 2 78 74 7 3 79 75 71 7 3 79 75 8 4 76 72 8 4 76 (Input) (Output) - When = High L2 D1_ID 19 20 1 2 3 76 4 8 2 19 20 1 2 76 4 8 D3_DM 75 79 3 7 1 75 79 3 7 74 78 2 6 0 74 78 2 6 73 77 5 9 73 77 5 (Input) (Output) - 27
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD (2) 1-bit erial Mode Interface egment Driver When = Low L2 D1_ID (Input) (Output) 79 80 1 2 3 2 79 78 79 80 1 2 2 79 - When = High L2 D1_ID (Input) (Output) 79 80 1 2 3 79 2 3 79 80 1 2 79 2-28
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD (3) ingle-type Interface Mode ommon Driver When = Low 79 80 1 2 79 80 1 2 OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA79 OM_DATA80 urrent Driver's OMMON Area When = High D4_DL 79 80 1 2 79 80 1 2 D2_DR OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA79 OM_DATA80 urrent Driver's OMMON Area 29
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD (4) DUAL-type Interface Mode ommon Driver When = Low 1 2 3 39 40 1 2 3 39 40 D3_DM OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA39 OM_DATA40 OM_DATA41 OM_DATA42 OM_DATA43 OM_DATA79 OM_DATA80 When = High 1 2 3 39 40 1 2 3 39 40 D3_DM OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA39 OM_DATA40 OM_DATA41 OM_DATA42 OM_DATA43 OM_DATA79 OM_DATA80 30
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD (5) ommon/egment Driver Timing (1/200 Duty) Latched Data (EG) M 199 200 1 200 1 199 200 1 199 200 OM_DATA1 OM_DATA199 OM_DATA200 OM1 OM199 OM200 V0 V1 V4 V5 V0 V1 V4 V5 V0 V1 V4 V5 EG_DATA1 EG1 V0 V1 V2 V3 V4 V5 L2 1 2 18 19 20 1 D1 - D4 Latched_Data M Enable Out 31
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD APPLIATION INFORMATION 1-bit erial Interface Mode (80-H egment Driver) a) Lower View ( = L, = H ) LD PANEL 1 80 81 160 n n+80 D1_ID - D1_ID - D1_ID - 1-bit serial data input b) Upper View ( = H, = H) 1-bit serial data input D1_ID - - D1_ID - D1_ID 1 80 81 160 n n+80 LD PANEL 32
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD 4-Bit Parallel Interface Mode (80-H egment Driver) a) Lower View ( = L, = L ) LD PANEL 1 80 81 160 n n+80 D1_ID- D1_ID- D1_ID- 4-bit serial data input 4 4 4 b) Upper View ( = H, = L) 4-bit serial data input 4 4 4 D1_ID- D1_ID- D1_ID- 1 80 81 160 n n+80 LD PANEL 33
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD ingle-type Interface Mode (80H ommon Driver) input data 1 1 80 81 LD PANEL 160 161 240 34
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD Dual-type Interface Mode (40H + 40H ommon Driver) input data 1 1 80 81 LD PANEL (1/2) 160 input data 2 D3_DM 161 40 41 200 201 240 241 320 LD PANEL (2/2) 321 400 NOTE: Using this application mode (dual-type common mode), the duty ratio can be reduced to half. In the case abale, 1/200 duty can be used to drive the 400 common LD panel. 35
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD APPLIATION IRUIT EXAMPLE VDD R R (n-4)r R R OM /EG V1 OM V2 EG V3 EG V4 V5 OM OM /EG V0-V5 DIPOFFB M 4 4 4 4 4 4 D1_ID - EG - EG80 L2 V0-V5 D1_ID - DIPOFFB M L2 EG - EG80 V0-V5 D1_ID - DIPOFFB M L2 EG - EG80 V VEE M DIPOFFB 1 1 80 81 160 161 240 OM1 - OM80 80 4 V0-V5 M DIPOFFB 81 240 x 240 LD MODULE OM1 - OM80 161 4 V0-V5 ontroller DIPOFFB FRAME(M) OM_DATA D1 - D4 L2 4 M DIPOFFB V0-V5 OM1 - OM80 161 240 36
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD NOTE 37
80H OMMON/EGMENT DRIVER FOR DOT MATRIX LD IMPORTANT NOTIE The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. amsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. amsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described here in any license under the patent rights of amsung or others. amsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does amsung assume any liability arising out of the application or use of any product r circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by the customer s technical experts. amsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant in to the body, for other applications intended to support or sustain life, or for any other application I which the failure of the amsung product could create a situation where personal injury or death may occur. hould the Buyer purchase or use a amsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold amsung and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that amsung was negligent regarding the design or manufacture of said product. *Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. onsequently, the users of the packages which may expose chips to external light such as OB, OG, TP and OF must consider effective methods to block out light from reaching the I on all parts as the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. onsider and verify the protection of penetrating light to the I at substrate (board or glass) or product design stage. 2. Always test and inspect products under the environment with no penetration of light. Graphic LD Driver I Data Book 2002 amsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of amsung Electronics. amsung Electronics o,.ltd an#24 Nongseo-Ri, Kiheung-Eup Yongin-ity Kyungi-Do, Korea.P.O. Box #37, uwon 449-900 TEL: 82-331-209-1431 FAX: 82-331-209-1432 Home page URL: http://www.samsungsemi.com/ Printed in the Republic of Korea 38