3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Audio and Video Processing. Applications SD/HD/3G-SDI

GS2971A 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Audio and Video Processing Key Features Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s Supports SMPTE ST 425 (Level A and Level B), SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C and DVB-ASI Integrated adaptive cable equalizer Typical equalized length of Belden 1694A cable: 150m at 2.97Gb/s 250m at 1.485Gb/s 480m at 270Mb/s Integrated Reclocker with low phase noise, integrated VCO Serial digital reclocked, or non-reclocked output Integrated audio de-embedder for 8 channels of 48kHz audio Integrated audio clock generator Ancillary data extraction Optional conversion from SMPTE ST 425 Level B to Level A for 1080p 50/60 4:2:2 10-bit Parallel data bus selectable as either 20-bit or 10-bit Comprehensive error detection and correction features Output H, V, F or CEA 861 Timing Signals 1.2V digital core power supply, 1.2V and 3.3V analog power supplies, and selectable 1.8V or 3.3V I/O power supply GSPI Host Interface -20ºC to +85ºC operating temperature range Low power operation (typically 545mW) Small 11mm x 11mm 100-ball BGA package Pb-free and RoHS compliant Applications SD/HD/3G-SDI 3G-SDI 3G-SDI Analog Sync Application: Single Link (3G-SDI) to Dual Link (HD-SDI) Converter GS2971A 10-bit HV F/PCLK HV F/PCLK 10-bit GS2962/72 GS2962/72 Application: 1080p50/60 Monitor GS2971A AUDIO 1/2 AUDIO 3/4 AUDIO 5/6 AUDIO 7/8 Audio Clocks 10-bit HV F/PCLK CTRL/TIMECODE AES - OUT Audio Selector Video Processor DAC DAC HD-SDI Link A HD-SDI Link B Speakers Display Application: Multi-format Downconverter GS2971A 10-bit Sync Seperator HV F/PCLK AES 1/2 AES 3/4 AES 5/6 AES 7/8 GS4901 10-bit bit SD Bypass Memory Video Downconverter & Aspect Ratio Conversion Audio Clocks HV F/PCLK Audio Processing & Delay AES 1/2 AES 3/4 AES 5/6 AES 7/8 10-bit HD/SD Serializer (GS1582, GS1672) SD-SDI 1 of 150

Analog Sync Sync Seperator Application: Multi-input Video Monitoring System 3G-SDI Input 1 3G-SDI Input 2 3G-SDI Input n GS2971A GS2971A GS2971A GS4911 10-bit HV F/PCLK 10-bit HV F/PCLK 10-bit HV F/PCLK AES BUS Video Memory Audio Select HV F/PCLK Audio Clocks Video Formatter On Screen Display Generator Audio Processor HV/DE/PCLK AE S OUT 1/2 AE S OUT 3/4 AE S OUT 5/6 AE S OUT 7/8 DVI/ VGA DAC Application: Multi-format Audio De-embedder Module SD/HD/3G-SDI GS2971A 10-bit PCLK AUDIO 1/2 AUDIO 3/4 AUDIO 5/6 AUDIO 7/8 Audio Clocks GS2962 Video Output Description The GS2971A is a multi-rate SDI integrated Receiver which includes complete SMPTE processing, as per SMPTE ST 425, SMPTE ST 292 and SMPTE ST 259-C. The SMPTE processing features can be bypassed to support signals with other coding schemes. The GS2971A integrates Semtech's adaptive cable equalizer technology, achieving unprecedented cable lengths and jitter tolerance. It features DC restoration to compensate for the DC content of SMPTE pathological signals. Switch Logic & Drivers DAC SD/HD/3G-SDI AES Audio Outputs Analog Audio Outputs Application: Multi-format Digital VTR/Video Server SD/HD/3G-SDI GS2971A 10-bit HVF/PCLK AUDIO 1/2 AUDIO 3/4 AUDIO 5/6 AUDIO 7/8 Audio Clocks V ideo Output Video Processor Audio Processor Audio Outputs Storage: Tape/ HDD/Solid State The device features an Integrated Reclocker with an internal VCO and a wide Input Jitter Tolerance (IJT) of 0.7UI. A serial digital loop-through output is provided, which can be configured to output either reclocked or non-reclocked serial digital data. The serial digital output can be connected to an external cable driver. The device operates in one of four basic modes: SMPTE mode, DVB-ASI mode, Data-Through mode or Standby mode. In SMPTE mode (the default operating mode), the GS2971A performs full SMPTE processing, and features a number of data integrity checks and measurement capabilities. The device also supports ancillary data extraction, and can provide entire ancillary data packets through host-accessible registers. It also provides a variety of other packet detection and error handling features. All of these processing features are optional, and may be individually enabled or disabled through register programming. Both SMPTE ST 425 Level A and Level B inputs are supported with optional conversion from Level B to Level A for 1080p 50/59.94/60 4:2:2 10-bit inputs. In DVB-ASI mode, sync word detection, alignment and 8b/10b decoding is applied to the received data stream. In Data-Through mode all forms of SMPTE and DVB-ASI processing are disabled, and the device can be used as a simple serial to parallel converter. The device can also operate in a lower power Standby mode. In this mode, no signal processing is carried out and the parallel output is held static. Parallel data outputs are provided in 20-bit or 10-bit format for 3Gb/s, HD and SD video rates, with a variety of mapping options. As such, this parallel bus can interface directly with video processor ICs, and output data can be multiplexed onto 10 bits for a low pin count interface. Up to eight channels (two audio groups) of serial digital audio may be extracted from the video data stream, in accordance with SMPTE ST 272-C and SMPTE ST 299. The output audio formats supported by the device include AES/EBU and I 2 S, and two other industry standard serial digital formats. A variety of audio processing features are provided to ease implementation. Audio clocks are internally generated and provided by the device. 2 of 150

Functional Block Diagram RESET_TRST STANDBY IOPROC_EN/DIS SMPTE_BYPASS 20BIT/10BIT TIM861 SW_EN DVB_ASI Crystal Buffer/ Oscillator GSPI and JTAG Controller Host Interface VBG LB_CONT LF SDI Reclocker with Integrated VCO Serial to Parallel Converter Descramble, Word Align, Rate Detect Flywheel Video Standard Detect TRS Detect Timing Extraction Audio De-Embedder, Audio Clock Generation ANC/ Checksum /ST 352 Extraction Illegal code remap, TRS/ Line Number/ CRS Insertion, EDH Packet Insertion Mux Output Mux/ Demux SDO SDO Buffer Mux DVB-ASI Decoder LOCKED H/HSync V/VSync F/De Rate_det[1:0] Error Flags YANC/CANC I/O Control SDO_EN/DIS RC_BYP EQ_VDD EQ_GND A_VDD A_GND BUFF_VDD BUFF_GND VCO_VDD VCO_GND PLL_VDD PLL_GND XTAL1 XTAL2 XTAL_OUT JTAG/HOST SDIN_TDI SCLK_TCLK CS_TMS SDOUT_TDO AUDIO_EN/DIS AOUT_1/2 AOUT_3/4 AOUT_5/6 AOUT_7/8 ACLK AMCLK WCLK CORE_VDD CORE_GND IO_VDD IO_GND SDI EQ Buffer SMPTE ST 425 Level B Level A 1080p 50/60 4:2:2 10-bit PCLK DOUT[19:0] AGCP AGCN LOCKED GS2971A Functional Block Diagram Revision History Version ECO PCN Date Changes and/or Modifications 3 014961 August 2013 2 158578 September 2012 Clarified IOPROC_EN/DIS register configuration throughout Section 4. Added note to Section 4.20. Updated SMPTE format throughout document. Added back the Typ column in the Table 2-4: AC Electrical Characteristics 1 158083 June 2012 Updates throughout the document 0 154391 July 2010 New Document 3 of 150

Contents 1. Pin Out...9 1.1 Pin Assignment...9 1.2 Pin Descriptions...9 2. Electrical Characteristics... 16 2.1 Absolute Maximum Ratings... 16 2.2 Recommended Operating Conditions... 16 2.3 DC Electrical Characteristics... 17 2.4 AC Electrical Characteristics... 19 3. Input/Output Circuits... 25 4. Detailed Description... 28 4.1 Functional Overview... 28 4.2 SMPTE ST 425 Mapping - 3G Level A and Level B Formats... 29 4.2.1 Level A Mapping... 29 4.2.2 Level B Mapping... 29 4.3 Serial Digital Input... 30 4.3.1 Integrated Adaptive Cable Equalizer... 30 4.4 Serial Digital Loop-Through Output... 31 4.5 Serial Digital Reclocker... 32 4.5.1 PLL Loop Bandwidth...32 4.6 External Crystal / Reference Clock...33 4.7 Lock Detect... 34 4.7.1 Asynchronous Lock... 35 4.7.2 Signal Interruption... 35 4.8 SMPTE Functionality... 35 4.8.1 Descrambling and Word Alignment... 35 4.9 Parallel Data Outputs... 36 4.9.1 Parallel Data Bus Buffers...36 4.9.2 Parallel Output in SMPTE Mode... 39 4.9.3 Parallel Output in DVB-ASI Mode... 39 4.9.4 Parallel Output in Data-Through Mode... 39 4.9.5 Parallel Output Clock (PCLK)... 39 4.9.6 DDR Parallel Clock Timing... 40 4.10 Timing Signal Generator... 42 4.10.1 Manual Switch Line Lock Handling... 43 4.10.2 Automatic Switch Line Lock Handling... 44 4.10.3 Switch Line Lock Handling During Level B to Level A Conversion... 44 4.11 Programmable Multi-function Outputs... 47 4.12 H:V:F Timing Signal Generation...47 4.12.1 CEA-861 Timing Generation... 49 4.13 Automatic Video Standards Detection... 56 4.13.1 2K Support... 60 4.14 Data Format Detection & Indication... 60 4.15 EDH Detection... 61 4 of 150

4.15.1 EDH Packet Detection... 61 4.15.2 EDH Flag Detection... 62 4.16 Video Signal Error Detection & Indication... 62 4.16.1 TRS Error Detection... 64 4.16.2 Line Based CRC Error Detection... 64 4.16.3 EDH CRC Error Detection... 65 4.16.4 HD & 3G Line Number Error Detection... 65 4.17 Ancillary Data Detection & Indication... 65 4.17.1 Programmable Ancillary Data Detection... 67 4.17.2 SMPTE ST 352 Payload Identifier... 68 4.17.3 Ancillary Data Checksum Error... 69 4.17.4 Video Standard Error...70 4.18 Signal Processing... 71 4.18.1 TRS Correction & Insertion... 72 4.18.2 Line Based CRC Correction & Insertion... 72 4.18.3 Line Number Error Correction & Insertion... 72 4.18.4 ANC Data Checksum Error Correction & Insertion... 73 4.18.5 EDH CRC Correction & Insertion... 73 4.18.6 Illegal Word Re-mapping... 73 4.18.7 TRS and Ancillary Data Preamble Remapping... 73 4.18.8 Ancillary Data Extraction... 74 4.18.9 Level B to Level A Conversion... 78 4.19 Audio De-embedder... 79 4.19.1 Serial Audio Data I/O Signals... 79 4.19.2 Serial Audio Data Format Support... 81 4.19.3 Audio Processing... 85 4.19.4 Error Reporting... 92 4.20 GSPI - HOST Interface... 93 4.20.1 Command Word Description... 94 4.20.2 Data Read or Write Access... 94 4.20.3 GSPI Timing... 95 4.21 Host Interface Register Maps... 97 4.21.1 Video Core Registers... 97 4.21.2 SD Audio Core Registers... 111 4.21.3 HD and 3G Audio Core Registers... 126 4.22 JTAG Test Operation... 141 4.23 Device Power-up... 143 4.24 Device Reset...143 4.25 Standby Mode... 143 5. Application Reference Design... 144 5.1 High Gain Adaptive Cable Equalizers... 144 5.2 PCB Layout... 144 5.3 Typical Application Circuit...145 6. References & Relevant Standards... 146 5 of 150

7. Package & Ordering Information... 147 7.1 Package Dimensions... 147 7.2 Packaging Data... 148 7.3 Marking Diagram... 148 7.4 Solder Reflow Profiles... 149 7.5 Ordering Information... 149 List of Figures Figure 3-1: Digital Input Pin with Schmitt Trigger... 25 Figure 3-2: Bidirectional Digital Input/Output Pin...25 Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength... 26 Figure 3-4: XTAL1/XTAL2/XTAL-OUT... 26 Figure 3-5: VBG... 26 Figure 3-6: LB_CONT... 27 Figure 3-7: Loop Filter... 27 Figure 3-8: SDO/SDO... 27 Figure 3-9: Equalizer Input Equivalent Circuit... 27 Figure 4-1: Level A Mapping... 29 Figure 4-2: Level B Mapping... 29 Figure 4-3: GS2971A Integrated EQ Block Diagram... 31 Figure 4-4: 27MHz Clock Sources... 33 Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 1... 36 Figure 4-6: PCLK to Data and Control Signal Output Timing - SDR Mode 2... 37 Figure 4-7: PCLK to Data and Control Signal Output Timing - DDR Mode... 37 Figure 4-8: DDR Video Interface - 3G Level A... 41 Figure 4-9: DDR Video Interface - 3G Level B... 41 Figure 4-10: Delay Adjustment Ranges... 42 Figure 4-11: Switch Line Locking on a Non-Standard Switch Line... 43 Figure 4-12: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode... 48 Figure 4-13: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode 3G Level B 20-bit Mode, each 10-bit stream... 48 Figure 4-14: H:V:F Output Timing - 3G Level B 10-bit Mode... 48 Figure 4-15: H:V:F Output Timing - HD 20-bit Output Mode... 48 Figure 4-16: H:V:F Output Timing - HD 10-bit Output Mode... 49 Figure 4-17: H:V:F Output Timing - SD 20-bit Output Mode... 49 Figure 4-18: H:V:F Output Timing - SD 10-bit Output Mode... 49 Figure 4-19: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4)... 51 Figure 4-20: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5)... 51 Figure 4-21: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7)... 52 Figure 4-22: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19)... 52 Figure 4-23: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20)... 53 Figure 4-24: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22)... 54 Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16)... 54 Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31)... 55 Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32)... 55 Figure 4-28: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33)... 56 Figure 4-29: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34)... 56 Figure 4-30: 2K Feature Enhancement... 60 Figure 4-31: Y/1ANC and C/2ANC Signal Timing... 67 6 of 150

Figure 4-32: Ancillary Data Extraction - Step A... 75 Figure 4-33: Ancillary Data Extraction - Step B... 76 Figure 4-34: Ancillary Data Extraction - Step C... 76 Figure 4-35: Ancillary Data Extraction - Step D... 77 Figure 4-36: ACLK to Data Signal Output Timing... 80 Figure 4-37: I 2 S Audio Output Format... 81 Figure 4-38: AES/EBU Audio Output Format...81 Figure 4-39: Serial Audio, Left Justified, MSB First... 82 Figure 4-40: Serial Audio, Left Justified, LSB First... 82 Figure 4-41: Serial Audio, Right Justified, MSB First...82 Figure 4-42: Serial Audio, Right Justified, LSB First... 82 Figure 4-43: AES/EBU Audio Output to Bit Clock Timing... 82 Figure 4-44: ECC 24-bit Array and Examples... 85 Figure 4-45: Sample Distribution over 5 Video Frames (525-line Systems)... 87 Figure 4-46: Audio Buffer After Initial 26 Sample Write... 87 Figure 4-47: Audio Buffer Pointer Boundary Checking... 88 Figure 4-48: GSPI Application Interface Connection... 93 Figure 4-49: Command Word Format... 94 Figure 4-50: Data Word Format... 95 Figure 4-51: Write Mode... 95 Figure 4-52: Read Mode... 95 Figure 4-53: GSPI Time Delay... 95 Figure 4-54: In-Circuit JTAG... 142 Figure 4-55: System JTAG...142 Figure 4-56: Reset Pulse... 143 Figure 5-1: Typical Application Circuit... 145 Figure 7-1: Package Dimensions... 147 Figure 7-2: GS2971A Marking Diagram...148 Figure 7-3: Pb-free Solder Reflow Profile... 149 List of Tables Table 1-1: Pin Description... 9 Table 2-1: Absolute Maximum Ratings... 16 Table 2-2: Recommended Operating Conditions... 16 Table 2-3: DC Electrical Characteristics... 17 Table 2-4: AC Electrical Characteristics... 19 Table 4-1: Serial Digital Output... 31 Table 4-2: PLL Loop Bandwidth... 32 Table 4-3: Input Clock Requirements... 33 Table 4-4: Lock Detect Conditions... 34 Table 4-5: GS2971A Output Video Data Format Selections... 38 Table 4-6: GS2971A PCLK Output Rates... 40 Table 4-7: Switch Line Position for Digital Systems... 45 Table 4-8: Output Signals Available on Programmable Multi-Function Pins... 47 Table 4-9: Supported CEA-861 Formats... 49 Table 4-10: CEA861 Timing Formats... 50 Table 4-11: Supported Video Standard Codes... 57 Table 4-12: Data Format Register Codes... 61 Table 4-13: Error Status Register and Error Mask Register... 63 Table 4-14: SMPTE ST 352 Packet Data... 69 7 of 150

Table 4-15: IOPROC_1 and IOPROC_2 Register Bits... 71 Table 4-16: Serial Audio Pin Descriptions... 79 Table 4-17: Audio Output Formats... 81 Table 4-18: Audio Data Packet Detect Register... 83 Table 4-19: Audio Group DID Host Interface Settings... 84 Table 4-20: Audio Data and Control Packet DID Setting Register... 84 Table 4-21: Audio Buffer Pointer Offset Settings... 88 Table 4-22: Audio Channel Mapping Codes... 89 Table 4-23: Audio Sample Word Lengths... 90 Table 4-24: Audio Channel Status Information Registers... 91 Table 4-25: Audio Channel Status Block for Regenerate Mode Default Settings... 91 Table 4-26: Audio Mute Control Bits... 92 Table 4-27: GSPI Time Delay... 95 Table 4-28: GSPI Timing Parameters (50% levels; 3.3V or 1.8V operation)... 96 Table 4-29: Video Core Configuration and Status Registers... 97 Table 4-30: SD Audio Core Configuration and Status Registers... 111 Table 4-31: HD and 3G Audio Core Configuration and Status Registers... 126 Table 4-32: ANC Extraction FIFO Access Registers... 141 Table 6-1: SMPTE Standards Reference... 146 Table 7-1: Packaging Data... 148 8 of 150

1. Pin Out 1.1 Pin Assignment 1 2 3 4 5 6 7 8 9 10 A VBG LF LB_CONT VCO_ VDD STAT0 STAT1 IO_VDD PCLK DOUT18 DOUT17 B A_VDD PLL_ VDD RSV VCO_ GND STAT2 STAT3 IO_GND DOUT19 DOUT16 DOUT15 C SDI A_GND PLL_ VDD PLL_ VDD STAT4 STAT5 RESET _TRST DOUT12 DOUT14 DOUT13 D SDI A_GND A_GND PLL_ GND CORE _GND CORE _VDD SW_EN JTAG/ HOST IO_GND IO_VDD E EQ_VDD EQ_GND A_GND PLL_ GND CORE _GND CORE _VDD SDOUT_ TDO SDIN_ TDI DOUT10 DOUT11 F AGCP RSV A_GND PLL_ GND CORE _GND CORE _VDD CS_ TMS SCLK_ TCK DOUT8 DOUT9 G AGCN A_GND RC_BYP CORE _GND CORE _GND CORE _VDD SMPTE_ BYPASS DVB_ASI IO_GND IO_VDD H BUFF_ VDD BUFF_ GND AUDIO_ EN/DIS WCLK TIM_861 XTAL_ OUT 20bit/ 10bit IOPROC_ EN/DIS DOUT6 DOUT7 J SDO SDO_ EN/DIS AOUT _1/2 ACLK AOUT _5/6 XTAL2 IO_GND DOUT1 DOUT4 DOUT5 K SDO STANDBY AOUT _3/4 AMCLK AOUT _7/8 XTAL1 IO_VDD DOUT0 DOUT2 DOUT3 1.2 Pin Descriptions Table 1-1: Pin Description Pin Number Name Type Description A1 VBG Analog Input Band Gap voltage filter connection. A2 LF Analog Input Loop Filter component connection. A3 LB_CONT Analog Input Connection for loop bandwidth control resistor. A4 VCO_VDD Input Power POWER pin for the VCO. Connect to a 1.2V±5% analog supply followed by a RC filter (see 5.3 Typical Application Circuit). A 105Ω 1% resistor must be used in the RC filter circuit. VCO_VDD is nominally 0.7V. 9 of 150

Table 1-1: Pin Description (Continued) Pin Number Name Type Description MULTI-FUNCTIONAL OUTPUT PORT. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Each of the STAT [0:5] pins can be configured individually to output one of the following signals: A5, A6, B5, B6, C5, C6 STAT[0:5] Output Signal H/HSYNC V/VSYNC F/DE LOCKED Y/1ANC C/2ANC DATA ERROR VIDEO ERROR AUDIO ERROR EDH DETECTED CARRIER DETECT RATE_DET0 RATE_DET1 Default STAT0 STAT1 STAT2 STAT3 STAT4 STAT5 A7, D10, G10, K7 IO_VDD Input Power POWER connection for digital I/O. Connect to 3.3V or 1.8V DC digital. PARALLEL DATA BUS CLOCK Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. A8 PCLK Output 3G 10-bit or 20-bit mode HD 10-bit mode HD 20-bit mode SD 10-bit mode SD 20-bit mode PCLK @ 148.5 or 148.5/1.001MHz PCLK @ 148.5 or 148.5/1.001MHz PCLK @ 74.25 or 74.25/1.001MHz PCLK @ 27MHz PCLK @ 13.5MHz 10 of 150

Table 1-1: Pin Description (Continued) Pin Number Name Type Description PARALLEL DATA BUS Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. SMPTE mode (SMPTE_BYPASS = HIGH and DVB_ASI = LOW): Luma data output for SD and HD data rates; Data Stream 1 for 3G data rate DVB-ASI mode (SMPTE_BYPASS = LOW and DVB_ASI = HIGH): Not defined Data-Through mode (SMPTE_BYPASS = LOW and DVB_ASI = LOW): Data output A9, A10, B8, B9, B10,C8, C9, C10, E9, E10 DOUT18, 17, 19, 16, 15, 12, 14, 13, 10, 11 Output 20-bit mode 20bit/10bit = HIGH 10-bit mode 20bit/10bit = LOW SMPTE mode (SMPTE_BYPASS = HIGH and DVB_ASI = LOW): Multiplexed Luma/Chroma data output for SD and HD data rates; Multiplexed Data Stream 1&2 for 3G data rate DVB-ASI mode (SMPTE_BYPASS = LOW and DVB_ASI = HIGH): 8b/10b decoded DVB-ASI data Data-Through mode (SMPTE_BYPASS = LOW and DVB_ASI = LOW): Data output B1 A_VDD Input Power POWER pin for analog circuitry. Connect to 3.3V DC analog. B2, C3, C4 PLL_VDD Input Power POWER pins for the Reclocker PLL. Connect to 1.2V DC analog. B3, F2 RSV These pins must be left unconnected. B4 VCO_GND Input Power GND pin for the VCO. Connect to analog GND. B7, D9, G9, J7 IO_GND Input Power GND connection for digital I/O. Connect to digital GND. C1, D1 SDI, SDI Analog Input Serial Digital Differential Input. C2, D2, D3, E3, F3, G2 A_GND Input Power GND pins for sensitive analog circuitry. Connect to analog GND. C7 RESET_TRST Input CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to reset the internal operating conditions to default settings and to reset the JTAG sequence. Normal mode (JTAG/HOST = LOW): When LOW, all functional blocks are set to default conditions and all digital output signals become high impedance. When HIGH, normal operation of the device resumes. JTAG test mode (JTAG/HOST = HIGH): When LOW, all functional blocks are set to default and the JTAG test sequence is reset. When HIGH, normal operation of the JTAG test sequence resumes after RESET_TRST is de-asserted. 11 of 150

Table 1-1: Pin Description (Continued) Pin Number Name Type Description D4, E4, F4 PLL_GND Input Power GND pins for the Reclocker PLL. Connect to analog GND. D5, E5, F5, G4, G5 D6, E6, F6, G6 CORE_GND Input Power GND connection for device core. Connect to digital GND. CORE_VDD Input Power POWER connection for device core. Connect to 1.2V DC digital. D7 SW_EN Input D8 JTAG/HOST Input CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to enable switch-line locking, as described in Section 4.10.1. CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to select JTAG test mode or host interface mode. When JTAG/HOST is HIGH, the host interface port is configured for JTAG test. When JTAG/HOST is LOW, normal operation of the host interface port resumes. E1 EQ_VDD Input Power POWER pin for SDI buffer. Connect to 3.3V DC analog. E2 EQ_GND Input Power GND pin for SDI buffer. Connect to analog GND. E7 SDOUT_TDO Output E8 SDIN_TDI Input F1, G1 AGCP, AGCN F7 CS_TMS Input COMMUNICATION SIGNAL OUTPUT Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. GSPI serial data output/test data out. In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test results from the device. In host interface mode, this pin is used to read status and configuration data from the device. COMMUNICATION SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. GSPI serial data in/test data in. In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test data into the device. In host interface mode, this pin is used to write address and configuration data words into the device. Automatic Gain Control for the equalizer. Attach the AGC capacitor between these pins. COMMUNICATION SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Chip select / test mode start. In JTAG mode (JTAG/HOST = HIGH), this pin is Test Mode Start, used to control the operation of the JTAG test. In host interface mode (JTAG/HOST = LOW), this pin operates as the host interface chip select and is active LOW. 12 of 150

Table 1-1: Pin Description (Continued) Pin Number Name Type Description F8 SCLK_TCK Input COMMUNICATION SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Serial data clock signal. In JTAG mode (JTAG/HOST = HIGH), this pin is the JTAG clock. In host interface mode (JTAG/HOST = LOW), this pin is the host interface serial bit clock. All JTAG/host interface addresses and data are shifted into/out of the device synchronously with this clock. PARALLEL DATA BUS Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. F9, F10, H9, H10, J8, J9, J10, K8, K9, K10 DOUT8, 9, 6, 7, 1, 4, 5, 0, 2, 3 Output 20-bit mode 20bit/10bit = HIGH SMPTE mode (SMPTE_BYPASS = HIGH and DVB_ASI = LOW): Chroma data output for SD and HD data rates; Data Stream 2 for 3G data rate DVB-ASI mode (SMPTE_BYPASS = LOW and DVB_ASI = HIGH): Not defined Data-Through mode (SMPTE_BYPASS = LOW and DVB_ASI = LOW): Data output 10-bit mode 20bit/10bit = LOW Forced LOW G3 RC_BYP Input G7 SMPTE_BYPASS Input/Output CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. When this pin is LOW, the serial digital output is the buffered version of the input serial data. When this pin is HIGH, the serial digital output is the reclocked version of the input serial data. CONTROL SIGNAL INPUT/OUTPUT Please refer to the Input/Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Indicates the presence of valid SMPTE data. When the AUTO/MAN bit in the host interface register is HIGH (Default), this pin is an OUTPUT. SMPTE_BYPASS is HIGH when the device locks to a SMPTE compliant input. SMPTE_BYPASS is LOW under all other conditions. When the AUTO/MAN bit in the host interface register is LOW, this pin is an INPUT: No SMPTE scrambling takes place, and none of the I/O processing features of the device are available when SMPTE_BYPASS is set LOW. When SMPTE_BYPASS is set HIGH, the device carries out SMPTE scrambling and I/O processing. When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode. 13 of 150

Table 1-1: Pin Description (Continued) Pin Number Name Type Description G8 DVB_ASI Input/Output H1 BUFF_VDD Input Power CONTROL SIGNAL INPUT Please refer to the Input/Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to enable/disable DVB-ASI data extraction in manual mode. When the AUTO/MAN bit in the host interface is LOW, this pin is an input and when the DVB_ASI pin is set HIGH the device will carry out DVB_ASI data extraction and processing. The SMPTE_BYPASS pin must be set LOW. When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode. When the AUTO/MAN bit in the host interface is HIGH (default), DVB-ASI is configured as a status output (set LOW), and DVB-ASI input streams are not supported or recognized. POWER pin for the serial digital output 50Ω buffer. Connect to 3.3V DC analog. H2 BUFF_GND Input Power GND pin for the cable driver buffer. Connect to analog GND. H3 AUDIO_EN/DIS Input H4 WCLK Output H5 TIM_861 Input CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Enables or disables audio extraction. 48kHz word clock for Audio. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to select CEA-861 timing mode. When TIM_861 is HIGH, the device outputs CEA 861 timing signals (HSYNC/VSYNC/DE) instead of H:V:F digital timing signals. H6 XTAL_OUT Digital Output Buffered 27MHz crystal output. Can be used to cascade the crystal signal. H7 20bit/10bit Input H8 IOPROC_EN/DIS Input CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to select the output bus width. HIGH = 20-bit, LOW = 10-bit. CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to enable or disable audio and video processing features. When IOPROC_EN is HIGH, the audio and video processing features of the device are enabled. When IOPROC_EN is LOW, the processing features of the device are disabled, and the device is in a low-latency operating mode. 14 of 150

Table 1-1: Pin Description (Continued) Pin Number Name Type Description J1, K1 SDO, SDO Output J2 SDO_EN/DIS Input J3 AOUT_1/2 Output J4 ACLK Output J5 AOUT_5/6 Output Serial Data Output Signal. 50Ω CML buffer for interfacing to an external cable driver. Serial digital output signal operating at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s. CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to enable/disable the serial digital output stage. When SDO_EN/DIS is LOW, the serial digital output signals, SDO and SDO, are both pulled HIGH. When SDO_EN/DIS is HIGH, the serial digital output signals, SDO and SDO, are enabled. Serial Audio Output; Channels 1 and 2. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. 64fs sample clock for audio. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Serial Audio Output; Channels 5 and 6. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. J6, K6 XTAL2, XTAL1 Analog Input Input connection for 27MHz crystal. K2 STANDBY Input K3 AOUT_3/4 Output K4 AMCLK Output K5 AOUT_7/8 Output CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. When this pin is set HIGH, the device is placed in a power-saving mode. No data processing occurs, and the digital I/Os are powered down. In this mode, the serial digital output signals, SDO and SDO, are both pulled HIGH. Serial Audio Output; Channels 3 and 4. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Oversampled master clock for audio (128fs, 256fs, 512fs selectable). Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Serial Audio Output; Channels 7 and 8. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. 15 of 150

2. Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Supply Voltage, Digital Core (CORE_VDD) Supply Voltage, Digital I/O (IO_VDD) Supply Voltage, Analog 1.2V (PD_VDD, VCO_VDD) Supply Voltage, Analog 3.3V (EQ_VDD, BUFF_VDD, A_VDD) Input Voltage Range (digital inputs) Operating Temperature Range Functional Temperature Range Storage Temperature Range Value/Units -0.3V to +1.5V -0.3V to +4.0V -0.3V to +1.5V -0.3V to +4.0V -2.0V to +5.25V -20 C to +85 C -40 C to +85 C -50 C to +125 C Peak Reflow Temperature (JEDEC J-STD-020C) 260 C ESD Sensitivity, HBM (JESD22-A114) 2kV Note: Absolute Maximum Ratings are those values beyond which damage may occur. Functional operation under these conditions or at any other condition beyond those indicated in the AC/DC Electrical Characteristics sections is not implied. 2.2 Recommended Operating Conditions Table 2-2: Recommended Operating Conditions T A = -20 C to +85 C, unless otherwise shown. Parameter Symbol Conditions Min Typ Max Units Notes Supply Voltage, Digital Core CORE_VDD 1.14 1.2 1.26 V Supply Voltage, Digital I/O IO_VDD 1.8V mode 1.71 1.8 1.89 V 3.3V mode 3.13 3.3 3.47 V Supply Voltage, PLL PLL_VDD 1.14 1.2 1.26 V Supply Voltage, Analog A_VDD 3.13 3.3 3.47 V 1 Supply Voltage, Serial Digital Input EQ_VDD 3.13 3.3 3.47 V 1 Supply Voltage, CD Buffer BUFF_VDD 3.13 3.3 3.47 V 1 Note: 1. The 3.3V supplies must track the 3.3V supply of an external CD. 16 of 150

2.3 DC Electrical Characteristics Table 2-3: DC Electrical Characteristics Guaranteed over recommended operating conditions unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Notes System 10bit 3G 220 265 ma 20bit 3G 210 265 ma +1.2V Supply Current +1.8V Supply Current +3.3V Supply Current Total Device Power (IO_VDD = 1.8V) Total Device Power (IO_VDD = 3.3V) Digital I/O I 1V2 I 1V8 I 3V3 P 1D8 P 3D3 10/20bit HD 170 220 ma 10/20bit SD 140 185 ma DVB_ASI 130 170 ma 10bit 3G 37 45 ma 20bit 3G 16 20 ma 10/20bit HD 15 21 ma 10/20bit SD 4 7 ma DVB_ASI 4 6 ma 10bit 3G 150 180 ma 20bit 3G 115 130 ma 10/20bit HD 110 135 ma 10/20bit SD 90 100 ma DVB_ASI 90 95 ma 10bit 3G 560 680 mw 20bit 3G 525 640 mw 10/20bit HD 480 590 mw 10/20bit SD 420 520 mw DVB_ASI 410 500 mw Reset 390 mw Standby 23 45 mw 10bit 3G 750 930 mw 20bit 3G 620 760 mw 10/20bit HD 570 730 mw 10/20bit SD 460 560 mw DVB_ASI 440 540 mw Reset 410 mw Standby 23 45 mw Input Logic LOW V IL 3.3V or 1.8V operation IO_VSS -0.3 0.3 x IO_VDD V Input Logic HIGH V IH 3.3V or 1.8V operation 0.7 x IO_VDD IO_VDD +0.3 V 17 of 150

Table 2-3: DC Electrical Characteristics (Continued) Guaranteed over recommended operating conditions unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Notes Output Logic LOW V OL IOL = 5mA, 1.8V operation 0.2 V IOL = 8mA, 3.3V operation 0.4 V Output Logic HIGH V OH IOH = 5mA, 1.8V operation 1.4 V IOH = 8mA, 3.3V operation 2.4 V Serial Input Serial Input Common Mode Voltage 75Ω load 2.2 V Serial Output Serial Output Common Mode Voltage 50Ω load BUFF_VDD -(0.6/2) BUFF_VDD -(0.45/2) BUFF_VDD -(0.35/2) V Note: The output drive strength of the digital outputs can be programmed through the host interface. please see Table 4-29: Video Core Configuration and Status Registers, register 06Dh for details. 18 of 150

2.4 AC Electrical Characteristics Table 2-4: AC Electrical Characteristics Guaranteed over recommended operating conditions unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Notes System Device Latency: AUDIO_EN = 1, SMPTE mode, IOPROC_EN = 1 Device Latency: AUDIO_EN = 0, SMPTE mode, IOPROC_EN = 1 Device Latency: AUDIO_EN = 0, SMPTE mode, IOPROC_EN = 0 Device Latency: AUDIO_EN = 0, SMPTE bypass, IOPROC_EN = 0 3G (Level A) 80 83 PCLK 3G (Level B) 143 151 PCLK HD 80 83 PCLK SD 50 55 PCLK 3G (Level A) 44 48 PCLK 3G (Level B) 108 116 PCLK HD 44 48 PCLK SD 44 48 PCLK 3G (Level A) 33 36 PCLK HD 33 36 PCLK SD 32 35 PCLK 3G (Level A) 6 9 PCLK HD 6 9 PCLK SD 5 9 PCLK Device Latency: DVB-ASI SD 12 16 PCLK Reset Pulse Width t reset 1 ms Parallel Output Parallel Clock Frequency f PCLK 13.5 148.5 MHz Parallel Clock Duty Cycle DC PCLK 40 60 % 19 of 150

Table 2-4: AC Electrical Characteristics (Continued) Guaranteed over recommended operating conditions unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Notes SPI 1.5 ns 1 3G 10-bit 6pF C LOAD AUDIO 1.5 ns 1 DBUS 0.3 ns 1 Output Data Hold Time (1.8V) t oh STAT 0.3 ns 1 3G 20-bit DBUS 1.0 ns 1 6pF C LOAD STAT 1.0 ns 1 HD 10-bit DBUS 1.0 ns 1 6pF C LOAD STAT 1.0 ns 1 HD 20-bit DBUS 1.0 ns 1 6pF C LOAD STAT 1.0 ns 1 SD 10-bit DBUS 19.4 ns 1 6pF C LOAD STAT 19.4 ns 1 SD 20-bit DBUS 38.0 ns 1 6pF C LOAD STAT 38.0 ns 1 SPI 1.5 ns 2 3G 10-bit 6pF C LOAD AUDIO 1.5 ns 2 DBUS 0.3 ns 2 Output Data Hold Time (3.3V) t oh STAT 0.3 ns 2 3G 20-bit DBUS 1.0 ns 2 6pF C LOAD STAT 1.0 ns 2 HD 10-bit DBUS 1.0 ns 2 6pF C LOAD STAT 1.0 ns 2 HD 20-bit DBUS 1.0 ns 2 6pF C LOAD STAT 1.0 ns 2 SD 10-bit DBUS 19.4 ns 2 6pF C LOAD STAT 19.4 ns 2 SD 20-bit DBUS 38.0 ns 2 6pF C LOAD STAT 38.0 ns 2 20 of 150

Table 2-4: AC Electrical Characteristics (Continued) Guaranteed over recommended operating conditions unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Notes SPI 14.0 ns 3 3G 10-bit 15pF C LOAD AUDIO 7.0 ns 3 DBUS 1.8 ns 3 Output Data Delay Time (1.8V) t od STAT 2.5 ns 3 3G 20-bit DBUS 3.7 ns 3 15pF C LOAD STAT 4.4 ns 3 HD 10-bit DBUS 3.7 ns 3 15pF C LOAD STAT 4.4 ns 3 HD 20-bit DBUS 3.7 ns 3 15pF C LOAD STAT 4.4 ns 3 SD 10-bit DBUS 22.2 ns 3 15pF C LOAD STAT 22.2 ns 3 SD 20-bit DBUS 41.0 ns 3 15pF C LOAD STAT 41.0 ns 3 SPI 14.0 ns 4 3G 10-bit 15pF C LOAD AUDIO 7.0 ns 4 DBUS 1.9 ns 4 Output Data Delay Time (3.3V) t od STAT 2.2 ns 4 3G 20-bit DBUS 3.7 ns 4 15pF C LOAD STAT 4.1 ns 4 HD 10-bit DBUS 3.7 ns 4 15pF C LOAD STAT 4.1 ns 4 HD 20-bit DBUS 3.7 ns 4 15pF C LOAD STAT 4.1 ns 4 SD 10-bit DBUS 22.2 ns 4 15pF C LOAD STAT 22.2 ns 4 SD 20-bit DBUS 41.0 ns 4 15pF C LOAD STAT 41.0 ns 4 21 of 150

Table 2-4: AC Electrical Characteristics (Continued) Guaranteed over recommended operating conditions unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Notes STAT 0.4 ns 1 3G 10-bit 6pF C LOAD DBUS 0.3 ns 1 AUDIO 0.6 ns 1 Output Data Rise/Fall Time (1.8V) t r /t f All other modes 6pF C LOAD 3G 10-bit 15pF C LOAD STAT 0.4 ns 1 DBUS 0.4 ns 1 AUDIO 0.6 ns 1 STAT 1.5 ns 3 DBUS 1.1 ns 3 AUDIO 2.3 ns 3 All other modes 15pF C LOAD STAT 1.5 ns 3 DBUS 1.4 ns 3 AUDIO 2.3 ns 3 STAT 0.5 ns 2 3G 10-bit 6pF C LOAD DBUS 0.4 ns 2 Output Data Rise/Fall Time (3.3V) t r /t f All other modes 6pF C LOAD AUDIO 0.6 ns 2 STAT 0.5 ns 2 DBUS 0.4 ns 2 AUDIO 0.6 ns 2 STAT 1.6 ns 4 3G 10-bit 15pF C LOAD DBUS 1.5 ns 4 Output Data Rise/Fall Time (3.3V) t r /t f All other modes 15pF C LOAD AUDIO 2.2 ns 4 STAT 1.6 ns 4 DBUS 1.4 ns 4 AUDIO 2.2 ns 4 Serial Digital Input Serial Input Data Rate DR SDI 0.27 2.97 Gb/s Serial Input Voltage Swing ΔV SDI T A =25 C, differential, 270Mb/s & 1.485Gb/s T A =25 C, differential, 2.97Gb/s 720 800 950 mv p-p 6 720 800 880 mv p-p 6 Belden 1694A cable, 3G 150 m Achievable Cable Length Belden 1694A cable, HD 230 m Belden 1694A cable, SD 460 m 22 of 150

Table 2-4: AC Electrical Characteristics (Continued) Guaranteed over recommended operating conditions unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Notes Input Return Loss single ended 15 21 db 7 Input Resistance single ended 1.52 kω Input Capacitance single ended 1 pf Serial Digital Output Serial Output Data Rate DR SDO 0.27 2.97 Gb/s Serial Output Swing ΔV SDO Differential with 100Ω load 320 600 mv p-p Serial Output Rise Time 20% 80% Serial Output Fall Time 20% 80% tr SDO 180 ps tf SDO 180 ps 3G, PRBS23, Belden 1694A cable, 140m 100 ps Serial Output Jitter with loop-through mode t OJ HD, PRBS23, Belden 1694A cable, 210m 100 ps SD, PRBS23, Belden 1694A cable, 440m 470 ps Serial Output Duty Cycle Distortion DCD SDD 3G 10 ps HD 10 ps SD 20 ps Synchronous lock time 25 μs Asynchronous lock time 0.1 20 ms Lock time from power-up After 20 minutes at -20 C 5 s GSPI GSPI Input Clock Frequency f SCLK 60 MHz 5 GSPI Input Clock Duty Cycle DC SCLK 40 50 60 % 5 GSPI Input Data Setup Time 1.5 ns 5 GSPI Input Data Hold Time 1.5 ns 5 GSPI Output Data Hold Time 50% levels 3.3V or 1.8V operation 1.5 ns 5 CS low before SCLK rising edge 1.5 ns 5 Time between end of command word (or data in Auto-Increment mode) and the first SCLK of the following data word - write cycle 37.1 ns 5 23 of 150

Table 2-4: AC Electrical Characteristics (Continued) Guaranteed over recommended operating conditions unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Notes Time between end of command word (or data in Auto-Increment mode) and the first SCLK of the following data word - read cycle 50% levels 3.3V or 1.8V operation 148.4 ns 5 CS high after SCLK falling edge 37.1 ns 5 Notes: 1. 1.89V and 0ºC. 2. 3.47V and 0ºC. 3. 1.71V and 85ºC 4. 3.13V and 85ºC 5. Timing parameters defined in Section 4.20.3 6. 0m cable length 7. Tested on a 2971 board from 5MHz to 3GHz. 24 of 150

3. Input/Output Circuits IO_VDD 200Ω Input Pin Figure 3-1: Digital Input Pin with Schmitt Trigger (20BIT/10BIT, AUDIO_EN/DIS, CS_TMS, SW_EN, IOPROC_EN/DIS, JTAG/HOST, RC_BYP, RESET_TRST, SCLK_TCK, SDIN_TDI, SDO_EN/DIS, STANDBY, TIM_861) IO_VDD 200Ω Output Pin Figure 3-2: Bidirectional Digital Input/Output Pin - Configured to Output unless in Reset Mode. (ACLK, AMCLK, AOUT_1/2, AOUT_3/4, AOUT_5/6, AOUT_7/8, DVB_ASI, SMPTE_BYPASS, WCLK) 25 of 150

IO_VDD 200Ω Output Pin Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength. These pins are configured to output unless in Reset Mode; in which case they are high-impedance. The drive strength can be set by writing to address 06Dh in the host interface register. (DOUT0, DOUT1, DOUT2, DOUT3, DOUT4, DOUT5, DOUT6, DOUT7, DOUT8, DOUT9, SDOUT_TDO, STAT0, STAT1, STAT2, STAT3, STAT4, STAT5, XTAL_OUT, DOUT10, DOUT11, DOUT12, DOUT13, DOUT14, DOUT15, DOUT16, DOUT17, DOUT18, DOUT19, PCLK) XTAL1 XTAL2 XTAL_OUT Figure 3-4: XTAL1/XTAL2/XTAL_OUT A_VDD 2kΩ 50Ω VBG Figure 3-5: VBG 26 of 150

EQ_VDD Out <0> LB_CONT Out <1> Figure 3-6: LB_CONT PLL_VDD 25Ω LF 25Ω Figure 3-7: Loop Filter 50Ω 50Ω BUFF_VDD SDO SDO Figure 3-8: SDO/SDO 4k 4k SDI SDI 6k RC 6k Figure 3-9: Equalizer Input Equivalent Circuit 27 of 150

4. Detailed Description 4.1 Functional Overview The GS2971A is a multi-rate SDI integrated Receiver which includes complete SMPTE processing, as per SMPTE ST 425, SMPTE ST 292 and SMPTE ST 259-C. The SMPTE processing features can be bypassed to support signals with other coding schemes. The GS2971A integrates Semtech's adaptive cable equalizer technology, achieving unprecedented cable lengths and jitter tolerance. It features DC restoration to compensate for the DC content of SMPTE pathological signals. The device features an Integrated Reclocker with an internal VCO and a wide Input Jitter Tolerance (IJT) of 0.7UI. A serial digital loop through output is provided, which can be configured to output either reclocked or non-reclocked serial digital data. The Serial Digital Output can be connected to an external Cable Driver. The device operates in one of four basic modes: SMPTE mode, DVB-ASI mode, Data-Through mode or Standby mode. In SMPTE mode, the GS2971A performs SMPTE de-scrambling and NRZI to NRZ decoding and word alignment. Line-based CRC errors, line number errors, TRS errors and ancillary data check sum errors can all be detected. The GS2971A also provides ancillary data extraction. The entire ancillary data packet is extracted, and written to host-accessible registers. Other processing functions include H:V:F timing extraction, Luma and Chroma ancillary data indication, video standard detection, and SMPTE ST 352 packet detection and decoding. All of the processing features are optional, and may be enabled or disabled via the Host Interface. Both SMPTE ST 425 Level A and Level B inputs are supported. The GS2971A also provides user-selectable conversion from Level B to Level A for 1080p 50/60 4:2:2 10-bit formats only. In DVB-ASI mode, 8b/10b decoding is applied to the received data stream. In Data-Through mode, all forms of SMPTE and DVB-ASI decoding are disabled, and the device can be used as a simple serial to parallel converter. The device can also be placed in a lower power Standby mode. In this mode, no signal processing is carried out and the parallel output is held static. Placing the Receiver in Standby mode will automatically place the integrated equalizer in power down mode as well. Parallel data outputs are provided in 20-bit or 10-bit multiplexed format for 3Gb/s, HD and SD video rates. For 1080p 50/60 4:2:2 10-bit, the parallel data is output on the 20-bit parallel bus as Y on 10 bits and Cb/Cr on the other 10 bits. As such, this parallel bus can interface directly with video processor ICs. For other SMPTE ST 425 mapping structures, the video data is mapped to a 20-bit virtual interface as described in SMPTE ST 425. In all cases this 20-bit parallel bus can be multiplexed onto 10 bits for a low pin count interface with downstream devices. The associated Parallel Clock input signal operates at 148.5 or 148.5/1.001MHz (for all 3Gb/s HD 10-bit multiplexed modes), 74.25 or 74.25/1.001MHz (for HD 20-bit mode), 27MHz (for SD 10-bit mode) and 13.5MHz (for SD 20-bit mode). 28 of 150

Note: for 3Gb/s 10-bit mode the device operates in Dual Data Rate (DDR) mode, where the data is sampled at both the rising and falling edges of the clock. This reduces the I/O speed requirements of the downstream devices. Up to eight channels, in two groups, of serial digital audio may be extracted from the video data stream, in accordance with SMPTE ST 272 and SMPTE ST 299. The output signal formats supported by the device include AES/EBU and three other industry standard serial digital formats. 16, 20 and 24-bit audio formats are supported at 48kHz synchronous for SD modes and 48kHz synchronous or asynchronous in HD/3G mode. Additional audio processing features include group selection, channel swapping, ECC error detection and correction (HD mode only), and audio channel status extraction. Audio clock and control signals provided by the device include Word Clock (fs), Serial Clock (64fs), and Audio Master Clock at user-selectable rates of 128fs, 256fs or 512fs. 4.2 SMPTE ST 425 Mapping - 3G Level A and Level B Formats 4.2.1 Level A Mapping Direct image format mapping - the mapping structure used to define 1080p/50/59.94/60 4:2:2 YCbCr 10 bit data, as supported by the GS2971A. See Figure 4-1: Data Stream 1 3FF 000 000 XYZ LN0 LN1 CRC0 CRC1 Audio Ctl Audio Ctl Audio Ctl Audio Ctl YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data YANC data 3FF 000 000 XYZ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 EAV HANC SAV Active Video Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Data Stream 2 3FF 000 000 XYZ LN0 LN1 CRC0 CRC1 Audio data Audio data Audio data Audio data Audio data Audio data Audio data Audio data Audio data Audio data Audio data Audio data CANC data CANC data CANC data CANC data HBLANK HBLANK HBLANK HBLANK HBLANK HBLANK HBLANK HBLANK HBLANK HBLANK HBLANK HBLANK 3FF 000 000 XYZ Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 Cb10 Cr10 Cb11 Cr11 Cb12 Cr12 Cb13 Cr13 Cb14 Cr14 Cb15 Cr15 Cb16 Cr16 Cb17 Cr17 Figure 4-1: Level A Mapping 4.2.2 Level B Mapping The 2 x 292 HD SDI interface - this can be two distinct links running at 1.5Gb/s or one 3Gb/s link formatted according to SMPTE ST 292 on two 10-bit links (Y/C interleaved). For 1080p/50/59.94/60 4:2:2 video formats, each link should be line-interleaved as per SMPTE ST 372. See Figure 4-2: multiplexed Y/C data Data Stream 1 ( Link A ) Data Stream 2 ( Link 2 ) 3FF 3FF 000 000 000 000 XYZ XYZ LN0 LN0 LN1 LN1 CRC0 CRC0 CRC1 CRC1 Audio data[1] Audio Ctl[1] Audio data[1] Audio Ctl[1] Audio data[1] Audio Ctl[1] Audio data[1] Audio Ctl[1] Audio data[1] YANC data[1] Audio data[1] YANC data[1] Audio data[1] YANC data[1] Audio data[1] YANC data[1] 3FF 3FF 000 000 000 000 XYZ XYZ LN0 LN0 LN1 LN1 CRC0 CRC0 3FF 3FF 000 000 000 000 XYZ XYZ EAV HANC SAV Active Video CRC1 CRC1 Audio data[2] Audio Ctl[2] Audio data[2] Audio Ctl[2] Audio data[2] Audio Ctl[2] Audio data[2] Audio Ctl[2] Audio data[2] YANC data[2] Audio data[2] YANC data[2] Audio data[2] YANC data[2] Audio data[2] YANC data[2] 3FF 3FF 000 000 000 000 XYZ XYZ Cb[1] 0 Y[1] 0 Cr[1] 0 Y[1] 1 Cb[2] 0 Y[2] 0 Cr[2] 0 Y[2] 1 Cb[1] 1 Y[1] 2 Cr[1] 1 Y[1] 3 Cb[1] 2 Y[1] 4 Cr[1] 2 Y[1] 5 Cb[1] 3 Y[1] 6 Cr[1] 3 Y[1] 7 Cb[1] 4 Y[1] 8 Cr[1] 4 Y[1] 9 Cb[1] 5 Y[1] 10 Cr[1] 5 Y[1] 11 Cb[1] 6 Y[1] 12 Cr[1] 6 Y[1] 13 Cb[1] 7 Y[1] 14 Cr[1] 7 Y[1] 15 Cb[1] 8 Y[1] 16 Cr[1] 8 Y[1] 17 Cb[2] 1 Y[2] 2 Cr[2] 1 Y[2] 3 Cb[2] 2 Y[2] 4 Cr[2] 2 Y[2] 5 Cb[2] 3 Y[2] 6 Cr[2] 3 Y[2] 7 Cb[2] 4 Y[2] 8 Cr[2] 4 Y[2] 9 Cb[2] 5 Y[2] 10 Cr[2] 5 Y[2] 11 Cb[2] 6 Y[2] 12 Cr[2] 6 Y[2] 13 Cb[2] 7 Y[2] 14 Cr[2] 7 Y[2] 15 Cb[2] 8 Y[2] 16 Cr[2] 8 Y[2] 17 Figure 4-2: Level B Mapping double TRS headers from interleaved HD-SDI; 29 of 150

The GS2971A distinguishes between Level A and Level B mappings at 3Gb/s. When Level B data is detected, each 10-bit link is demultiplexed into its individual component streams, and most video processing features, including error detection and correction are enabled separately for Data Stream 1 and Data Stream 2 (Link A and Link B, respectively). Note that audio demultiplexing and ancillary data extraction can only be enabled for one link for 3Gb/s Level B data. Data Stream 1 or Data Stream 2 can be selected via the host interface. 4.3 Serial Digital Input The GS2971A can accept serial digital inputs compliant with SMPTE ST 424, SMPTE ST 292 and SMPTE ST 259-C. 4.3.1 Integrated Adaptive Cable Equalizer The GS2971A integrates Semtech's adaptive cable equalizer technology. The integrated adaptive equalizer can equalize 3Gb/s, HD and SD serial digital signals, and will typically equalize 150m of Belden 1694A cable at 2.97Gb/s, 250m at 1.485Gb/s and 480m at 270Mb/s.The integrated adaptive equalizer is powered from a single +3.3V power supply and consumes approximately 195mW of power. The equalizer can be bypassed by programming register 073h through the GSPI interface. 4.3.1.1 Serial Digital Inputs The Serial Data Signal may be connected to the input pins (SDI/SDI) in either a differential or single ended configuration. AC coupling of the inputs is recommended, as the SDI and SDI inputs are internally biased at approximately 1.8V. 4.3.1.2 Cable Equalization The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse of the cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by both an internal and an external AGC filter capacitor providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to AC coupling. 30 of 150

EQ Buffer Buffer Mux Crystal Buffer/ Oscillator Reclocker with Integrated VCO Serial to Parallel Converter GSPI and JTAG Controller Descramble, Word Align, Rate Detect Flywheel Video Standard Detect TRS Detect Timing Extraction Audio De-Embedder, Audio Clock Generation ANC/ Checksum /ST 352 Extraction DVB-ASI Decoder SMPTE ST 425 Level B Level A 1080p 50/60 4:2:2 10-bit Illegal code remap, TRS/ Line Number/ CRS Insertion, EDH Packet Insertion Mux Output Mux/ Demux I/O Control RESET_TRST STANDBY IOPROC_EN/DIS SMPTE_BYPASS 20BIT/10BIT TIM861 SW_EN DVB_ASI Host Interface VBG LB_CONT LF SDI SDO SDO LOCKED H/HSync V/VSync F/De Rate_det[1:0] Error Flags YANC/CANC SDO_EN/DIS RC_BYP EQ_VDD EQ_GND A_VDD A_GND BUFF_VDD BUFF_GND VCO_VDD VCO_GND PLL_VDD PLL_GND XTAL1 XTAL2 XTAL_OUT JTAG/HOST SDIN_TDI SCLK_TCLK CS_TMS SDOUT_TDO AUDIO_EN/DIS AOUT_1/2 AOUT_3/4 AOUT_5/6 AOUT_7/8 ACLK AMCLK WCLK CORE_VDD CORE_GND IO_VDD IO_GND SDI PCLK DOUT[19:0] AGCP AGCN LOCKED Figure 4-3: GS2971A Integrated EQ Block Diagram 4.4 Serial Digital Loop-Through Output The GS2971A contains a 100Ω differential serial output buffer which can be configured to output either a retimed or a buffered version of the serial digital input. The SDO and SDO outputs of this buffer can interface directly to a 3Gb/s-capable, SMPTE compliant Semtech cable driver. See 5.3 Typical Application Circuit on page 145. When the RC_BYP pin is set HIGH, the serial digital output is the re-timed version of the serial input. When the RC_BYP pin is set LOW, the serial digital output is simply the buffered version of the serial input, bypassing the internal reclocker. The output can be disabled by setting the SDO_EN/DIS pin LOW. The output is also disabled when the STANDBY pin is asserted HIGH. When the output is disabled, both SDO and SDO pins are set to VDD and remain static. The SDO output is muted when the RC_BYP pin is set HIGH and the PLL is unlocked (LOCKED pin is LOW). When muted, the output is held static at logic 0 or logic 1. Table 4-1: Serial Digital Output SDO_EN/DIS RC_BYP SDO/SDO 0 X Disabled 1 1 Re-timed 1 0 Buffered (not re-timed) Note: The serial digital output is muted when the GS2971A is unlocked. 31 of 150

4.5 Serial Digital Reclocker The GS2971A includes both a PLL stage and a sampling stage. The PLL is comprised of two distinct loops: A coarse frequency acquisition loop sets the centre frequency of the integrated Voltage Controlled Oscillator (VCO) using an external 27MHz reference clock A fine frequency and phase locked loop aligns the VCO s phase and frequency to the input serial digital stream The frequency lock loop results in a very fast lock time. The sampling stage re-times the serial digital input with the locked VCO clock. This generates a clean serial digital stream, which may be output on the SDO/SDO output pins and converted to parallel data for further processing. Parallel data is not affected by RC_BYP. Only the SDO is affected by this pin. 4.5.1 PLL Loop Bandwidth The fine frequency and phase lock loop in the GS2971A reclocker is non-linear. The PLL loop bandwidth scales with the jitter amplitude of the input data stream; automatically reduces bandwidth in response to higher jitter. This allows the PLL to reject more of the jitter in the input data stream and produce a very clean reclocked output. The loop bandwidth of the GS2971A PLL is defined with 0.2UI input jitter. The bandwidth is controlled by the LB_CONT pin. Under nominal conditions, with the LB_CONT pin floating and 0.2UI input jitter applied, the loop bandwidth is set to 1/1000 of the frequency of the input data stream. Connecting the LB_CONT pin to 3.3V reduces the bandwidth to half of the nominal setting. Connecting the LB_CONT pin to GND increases the bandwidth to double the nominal setting. Table 4-2 below summarizes this information. Table 4-2: PLL Loop Bandwidth Input Data Rate LB_CONT Pin Connection Loop Bandwidth (MHz) 1 3.3V 0.135 SD Floating 0.27 0V 0.54 3.3V 0.75 HD Floating 1.5 0V 3.0 3.3V 1.5 3G Floating 3.0 1 Measured with 0.2UI input jitter applied 0V 6.0 32 of 150

4.6 External Crystal / Reference Clock The GS2971A requires an external 27MHz reference clock for correct operation. This reference clock is generated by connecting a crystal to the XTAL1 and XTAL2 pins of the device. See Application Reference Design on page 144. Table 4-3 shows XTAL characteristics. Alternately, a 27MHz external clock source can be connected to the XTAL1 pin of the device, as shown in Figure 4-4. The frequency variation of the crystal including aging, supply and temperature variation, should be less than +/-100ppm. The equivalent series resistance (or motional resistance) should be a maximum of 50Ω. The external crystal is used in the frequency acquisition process. It has no impact on the output jitter performance of the part when the part is locked to incoming data. Because of this, the only key parameter is the frequency variation of the crystal that is stated above. External Crystal Connection External Clock Source Connection 16pF K6 XTAL1 K6 XTAL1 External Clock J6 XTAL2 NC J6 XTAL2 16pF Notes: 1. Capacitor values listed represent the total capacitance, including discrete capacitance and parasitic board capacitance. 2.XTAL1 serves as an input, which may alternatively accept a 27MHz clock source. Figure 4-4: 27MHz Clock Sources Table 4-3: Input Clock Requirements Parameter Min Typ Max Units XTAL1 Low Level Input Voltage (V il ) XTAL1 High Level Input Voltage (V ih ) 20% of VDD_IO V 80% of VDDIO V XTAL1 Input Slew Rate 2 V/ns 33 of 150

Table 4-3: Input Clock Requirements (Continued) Parameter Min Typ Max Units XTAL1 to XOUT Prop. Delay (High to Low) XTAL1 to XOUT Prop. Delay (Low to High) 1.3 1.5 2.3 ns 1.3 1.6 2.3 ns Note: Valid when the cell is used to buffer an external clock source which is connected to the XTAL1 pin, then nothing should be connected to the XTAL2 pin. 4.7 Lock Detect The LOCKED output signal is available by default on the STAT3 output pin, but may be programmed to be output through any one of the six programmable multi-functional pins of the device: STAT[5:0]. The LOCKED output signal is set HIGH by the Lock Detect block under the following conditions: Table 4-4: Lock Detect Conditions Mode of Operation Mode Setting Condition for Locked Data-Through Mode SMPTE Mode SMPTE Mode with Lock Noise-Immunity Enabled DVB_ASI Mode SMPTE_BYPASS = LOW DVB_ASI = LOW SMPTE_BYPASS = HIGH DVB_ASI = LOW SMPTE_BYPASS = HIGH DVB_ASI = LOW Bit 0x085[10] set to 1 AUTO/MAN = HIGH SMPTE_BYPASS = LOW DVB_ASI = HIGH Bit AUTO/MAN = LOW Reclocker PLL is locked. Reclocker PLL is locked. Two consecutive TRS words are detected in a two-line window. Reclocker PLL is locked. Two consecutive TRS words are detected in a two-line window. The last two detected TRS words must have the same alignment. Note: Auto mode only. Not supported in Manual mode. Reclocker PLL is locked. 32 consecutive DVB_ASI words with no errors are detected within a 128-word window. Note 1: The GS2971A will lock to ASI in auto mode, but could falsely unlock for some ASI input patterns. Note 2: In Standby mode, the reclocker PLL unlocks. However, the LOCKED signal retains whatever state it previously held. So, if before Standby assertion, the LOCKED signal is HIGH, then during standby, it remains HIGH regardless of the status of the PLL. 34 of 150

4.7.1 Asynchronous Lock The lock detection algorithm is a continuous process, beginning at device power-up or after a system reset. It continues until the device is powered down or held in reset. The device first determines if a valid serial digital input signal has been presented to the device. If no valid serial data stream has been detected, the serial data into the device is considered invalid, and the LOCKED signal is LOW. Once a valid input signal has been detected, the asynchronous lock algorithm enters a hunt phase, in which the device attempts to detect the presence of either TRS words or DVB-ASI sync words. By default, the device powers up in auto mode (the AUTO/MAN bit in the host interface is set HIGH). In this mode, the device operating frequency toggles between 3G, HD and SD rates as it attempts to lock to the incoming data rate. The PCLK output continues to operate, and the frequency may switch between 148.5MHz, 74.25MHz, 27MHz and 13.5MHz. When the device is operating in manual mode (AUTO/MAN bit in the host interface is LOW), the operating frequency needs to be set through the host interface using the RATE_DET[1:0] bits. In this mode, the asynchronous lock algorithm does not toggle the operating rate of the device and attempts to lock within a single standard. Lock is achieved within three lines of the selected standard. 4.7.2 Signal Interruption The device tolerates a signal interruption of up to 10μs without unlocking, as long as no TRS words are deleted by this interruption. If a signal interruption of greater than 10μs is detected, the lock detection algorithm may lose the current data rate, and LOCKED will de-assert until the data rate is re-acquired by the lock detection block. 4.8 SMPTE Functionality 4.8.1 Descrambling and Word Alignment The GS2971A performs NRZI to NRZ decoding and data descrambling according to SMPTE ST 424/SMPTE ST 292/SMPTE ST 259-C and word aligns the data to TRS sync words. When operating in manual mode (AUTO/MAN = LOW), the device only carries out SMPTE decoding, descrambling and word alignment when the SMPTE_BYPASS pin is set HIGH and the DVB_ASI pin is set LOW. When operating in Auto mode (AUTO/MAN = HIGH), the GS2971A carries out descrambling and word alignment to enable the detection of TRS sync words. When two consecutive valid TRS words (SAV and EAV), with the same bit alignment have been detected, the device word-aligns the data to the TRS ID words. TRS ID word detection is a continuous process. The device remains in SMPTE mode until TRS ID words fail to be detected. Note 1: Both 8-bit and 10-bit TRS headers are identified by the device. 35 of 150

Note 2: In 3G Level B mode, the device only supports Data Stream 1 and Data Stream 2 having the same bit width (i.e. both data streams contain 8-bit data, or both data streams contain 10-bit data). If the bit widths between the two data streams are different, the GS2971A cannot word align the input stream, and switches in Data-Through mode. 4.9 Parallel Data Outputs The parallel data outputs are aligned to the rising edge of the PCLK. 4.9.1 Parallel Data Bus Buffers The parallel data bus, status signal outputs and control signal input pins are all connected to high-impedance buffers. The device supports 1.8 or 3.3V (LVTTL and LVCMOS levels) supplied at the IO_VDD and IO_GND pins. All output buffers (including the PCLK output), are set to high-impedance in Reset mode (RESET_TRST = LOW). I/O Timing Specs: 10-bit SDR Mode: 6.734ns (HD 10-bit) 37.037ns (SD 10-bit) DBUS[19:10] Y0 Cr0 Y1 Cb1 PCLK_OUT 20% 80% 80% 20% toh tod tr tf 10bHD Mode 3.3V 1.8V toh tr/tf (min) C load tod tr/tf (max) C load toh tr/tf (min) C load tod tr/tf (max) C load dbus 1.000ns 0.400ns 3.700ns 1.400ns 1.000ns 0.400ns 3.700ns 1.400ns 6 pf 15 pf 6 pf 15 pf stat 1.000ns 0.500ns 4.100ns 1.600ns 1.000ns 0.400ns 4.400ns 1.500ns 10bSD Mode 3.3V 1.8V toh tr/tf (min) C load tod tr/tf (max) C load toh tr/tf (min) C load tod tr/tf (max) C load dbus 19.400ns 0.400ns 22.200ns 1.400ns 19.400ns 0.400ns 22.200ns 1.400ns 6 pf 15 pf 6 pf 15 pf stat 19.400ns 0.500ns 22.200ns 1.600ns 19.400ns 0.400ns 22.200ns 1.500ns Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 1 36 of 150

I/O Timing Specs: 20-bit SDR Mode: 6.734ns (3G 20-bit) 13.468ns (HD 20-bit) 74.074ns (SD 20-bit) DBUS[19:10] Y0 Y1 Y2 Y3 DBUS[9:0] Cb0 Cr0 Cb1 Cr1 PCLK_OUT 20% 80% 80% 20% toh tod tr tf 20b3G and 20bHD Modes 3.3V 1.8V toh tr/tf (min) C load tod tr/tf (max) C load toh tr/tf (min) C load tod tr/tf (max) C load dbus 1.000ns 0.400ns 3.700ns 1.400ns 1.000ns 0.400ns 3.700ns 1.400ns 6 pf 15 pf 6 pf 15 pf stat 1.000ns 0.500ns 4.100ns 1.600ns 1.000ns 0.400ns 4.400ns 1.500ns 20bSD Mode 3.3V 1.8V toh tr/tf (min) C load tod tr/tf (max) C load toh tr/tf (min) C load tod tr/tf (max) C load dbus 38.000ns 0.400ns 41.000ns 1.400ns 38.000ns 0.400ns 41.000ns 1.400ns 6 pf 15 pf 6 pf 15 pf stat 38.000ns 0.500ns 41.000ns 1.600ns 38.000ns 0.400ns 41.000ns 1.500ns Figure 4-6: PCLK to Data and Control Signal Output Timing - SDR Mode 2 I/O Timing Specs: DDR Mode: 3.367ns 6.734ns DBUS[19:10] Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 PCLK_OUT 80% 20% 80% 20% toh tod toh tod tr tf 10b3G Mode 3.3V 1.8V toh tr/tf (min) C load tod tr/tf (max) C load toh tr/tf (min) C load tod tr/tf (max) C load dbus 0.450ns 0.400ns 1.900ns 1.500ns 0.400ns 0.300ns 1.800ns 1.100ns 6 pf 15 pf 6 pf 15 pf stat 0.450ns 0.500ns 2.200ns 1.600ns 0.450ns 0.400ns 2.500ns 1.500ns Figure 4-7: PCLK to Data and Control Signal Output Timing - DDR Mode 37 of 150

The GS2971A has a 20-bit output parallel bus, which can be configured for different output formats as shown in Table 4-5. Table 4-5: GS2971A Output Video Data Format Selections Output Data Format 20BIT /10BIT RATE_ SEL0 Pin/Register Bit Settings RATE_ SEL1 SMPTE_ BYPASS DVB-ASI DOUT[9:0] DOUT[19:10] 20-bit demultiplexed HD format 20-bit data output HD format 20-bit demultiplexed SD format 20-bit data output SD format HIGH LOW LOW HIGH LOW Chroma Luma HIGH LOW LOW LOW LOW DATA DATA HIGH HIGH X HIGH LOW Chroma Luma HIGH HIGH X LOW LOW DATA DATA 10-bit multiplexed 3G DDR format LOW LOW HIGH HIGH LOW Driven LOW Data Stream One/ Data Stream Two* 10-bit multiplexed HD format 10-bit data output HD format 10-bit multiplexed SD format 10-bit data output SD format 20-bit demultiplexed 3G format LOW LOW LOW HIGH LOW Driven LOW Luma/Chroma LOW LOW LOW LOW LOW Driven LOW DATA LOW HIGH X HIGH LOW Driven LOW Luma/Chroma LOW HIGH X LOW LOW Driven LOW DATA HIGH LOW HIGH HIGH LOW Data Stream Two* Data Stream One* DVB-ASI format LOW HIGH X HIGH DOUT19 = WORD_ERR DOUT18 = SYNC_OUT DOUT17 = H_OUT DOUT16 = G_OUT DOUT15 = F_OUT DOUT14 = E_OUT DOUT13 = D_OUT DOUT12 = C_OUT DOUT11 = B_OUT DOUT10 = A_OUT *In 3G Mode, the data streams can be swapped at the output through the host interface. Note: When in Auto Mode, swap RATE_SEL with RATE_DET. 38 of 150

4.9.2 Parallel Output in SMPTE Mode When the device is operating in SMPTE mode (SMPTE_BYPASS = HIGH and DVB_ASI = LOW), data is output in either Multiplexed or Demultiplexed form depending on the setting of the 20bit/10bit pin. When operating in 20-bit mode (20bit/10bit = HIGH), the output data is demultiplexed Luma and Chroma data for SD and HD data rates, and Data Stream 1 and Data Stream 2 for the 3G data. When operating in 10-bit mode (20bit/10bit = LOW), the output data is multiplexed Luma and Chroma data for SD and HD data rates, and multiplexed Data Stream 1 and Data Stream 2 for the 3G data. In this mode, the data is presented on the DOUT[19:10] pins, with DOUT[9:0] being forced LOW. 4.9.3 Parallel Output in DVB-ASI Mode In DVB-ASI mode, the 20bit/10bit pin must be set LOW to configure the output parallel bus for 10-bit operation. DVB-ASI mode is enabled when the AUTO/MAN bit is LOW, SMPTE_BYPASS pin is LOW and the DVB_ASI pin is HIGH. The extracted 8-bit data is presented on DOUT[17:10] such that DOUT[17:10] = HOUT AOUT, where AOUT is the least significant bit of the decoded transport stream data. In addition, the DOUT19 and DOUT18 pins are configured as DVB-ASI status signals WORDERR and SYNCOUT respectively. SYNCOUT is HIGH whenever a K28.5 sync character is output from the device. WORDERR is HIGH whenever the device has detected a running disparity error or illegal code word. 4.9.4 Parallel Output in Data-Through Mode This mode is enabled when the SMPTE_BYPASS and DVB_ASI pins are LOW. In this mode, data is passed to the output bus without any decoding, descrambling or word-alignment. The output data width (10-bit or 20-bit) is controlled by the setting of the 20bit/10bit pin. Note: In order to use Data-Through Mode, a 3G-B input signal must not be connected at the input of the device when the switch is made from Auto Mode to Data Through Mode. 4.9.5 Parallel Output Clock (PCLK) The frequency of the PCLK output signal of the GS2971A is determined by the output data rate and the 20bit/10bit pin setting. Table 4-6 lists the output signal formats according to the data format selected in Manual mode (AUTO/MAN bit in the host interface is set LOW), or detected in Auto mode (AUTO/MAN bit in the host interface is set HIGH). 39 of 150

Table 4-6: GS2971A PCLK Output Rates Output Data Format 20bit/ 10bit RATE_DET0 Pin/Control Bit Settings RATE_DET1 SMPTE_ BYPASS DVB-ASI PCLK Rate 20-bit demultiplexed HD format 20-bit data output HD format HIGH LOW LOW HIGH LOW HIGH LOW LOW LOW LOW 74.25 or 74.25/1.001MHz 74.25 or 74.25/1.001MHz 20-bit demultiplexed SD format 20-bit data output SD format HIGH HIGH X HIGH LOW 13.5MHz HIGH HIGH X LOW LOW 13.5MHz 20-bit demultiplexed 3G format 10-bit multiplexed 3G DDR format 10-bit multiplexed HD format 10-bit data output HD format HIGH LOW HIGH HIGH LOW LOW LOW HIGH HIGH LOW LOW LOW LOW HIGH LOW LOW LOW LOW LOW LOW 148.5 or 148.5/1.001MHz 148.5 or 148.5/1.001MHz 148.5 or 148.5/1.001MHz 148.5 or 148.5/1.001MHz 10-bit multiplexed SD format 10-bit data output SD format 10-bit ASI output SD format LOW HIGH X HIGH LOW 27MHz LOW HIGH X LOW LOW 27MHz LOW HIGH X LOW HIGH 27MHz 4.9.6 DDR Parallel Clock Timing The GS2971A has the ability to transmit 10-bit parallel video data with a DDR (Dual Data Rate) pixel clock over a single-ended interface. DDR Mode can be enabled when the SDI data bandwidth is 3Gb/s. In this case, the 10-bit parallel data rate is 297Mb/s, and the frequency of the DDR clock is 148.5MHz (10-bit output in 3G mode). The DDR pixel clock avoids the need to operate a high-drive pixel clock at 297MHz. This reduces power consumption, clock drive strength, and noise generation. It precludes from generating excessive EMI if PCLK on the board has to run at 297MHz. It also enables easier board routing and avoids the need to use the higher-speed I/Os on FPGAs, which may require more expensive speed grades. Figure 4-8 and Figure 4-9 show how the DDR interface operates. The pixel clock is transmitted at half the data rate, and the interleaved data is sampled at the receiver on both clock edges. 40 of 150

20-bit bus (transition rate = 74.25MHz) Y0 Cb0 Y1 Cr0 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 10-bit bus (transition rate = 148.5MHz) Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y5 Cb3 Y6 Cr3 Y7 Cb4 Y8 Cr4 Y9 PCLK (148.5MHz) Figure 4-8: DDR Video Interface - 3G Level A 20-bit bus (transition rate = 74.25MHz) DOUT0[9:0] Data Stream 1 Cb[2] 0 Y[2] 0 Cr[2] 0 Y[2] 1 Cb[2] 1 Y[2] 2 Cr[2] 1 Y[2] 3 Cb[2] 2 Y[2] 4 DOUT1[9:0] Data Stream 2 Cb[3] 0 Y[3] 0 Cr[3] 0 Y[3] 1 Cb[3] 1 Y[3] 2 Cr[3] 1 Y[3] 3 Cb[3] 2 Y[3] 4 10-bit bus (transition rate = 148.5MHz) DOUT1[9:0] Cb[3] 0 Cb[2] 0 Y[3] 0 Y[2] 0 Cr[3] 0 Cr[2] 0 Y[3] 1 Y[2] 1 Cb[3] 1 Cb[2] 1 Y[3] 2 Y[2] 2 Cr[3] 1 Cr[2] 1 Y[3] 3 Y[2] 3 Cb[3] 2 Cb[2] 2 Y[3] 4 Y[2] 4 PCLK (148.5MHz) Figure 4-9: DDR Video Interface - 3G Level B The GS2971A has the ability to shift the Setup/Hold window on the receive interface, by using an on-chip delay line to shift the phase of PCLK with respect to the data bus. The timing of the PCLK output, relative to the data, can be adjusted through the host interface registers. Address 06Ch contains the delay line controls: Bit[5] (DEL_LINE_CLK_SEL) is a coarse delay adjustment that selects between the default (nominal) PCLK phase and a quadrature phase, for a 90º phase shift. Bits[4:0] (DEL_LINE_OFFSET) comprise a fine delay adjustment to shift the PCLK in 40ps increments (typical conditions). The maximum fine delay adjustment is approximately 1.2ns under nominal conditions. An example delay adjustment over min/typ/max conditions is illustrated in Figure 4-10. The target delay is 0.84 ns under typical conditions (approximately 45º PCLK phase shift), and requires a control word setting of 0x0014 for address 0x006C. 41 of 150

90º phase shift 3.367ns 6.734ns 1.684ns PCLK 0.842ns offset [5] = 1 (90º phase shift) Typical 45º phase shift 3.367ns 6.734ns 1.684ns PCLK (MIN) 0.58ns delay Ranges: PCLK (TYP) 0.84ns delay PCLK (MAX) 1.38ns delay Figure 4-10: Delay Adjustment Ranges 4.10 Timing Signal Generator The GS2971A has an internal timing signal generator which is used to generate digital FVH timing reference signals, to detect and correct certain error conditions and automatic video standard detection. The timing signal generator is only operational in SMPTE mode (SMPTE_BYPASS = HIGH). The timing signal generator consists of a number of counters and comparators operating at video pixel and video line rates. These counters maintain information about the total line length, active line length, total number of lines per field/frame and total active lines per field/frame for the received video standard. It takes one video frame to obtain full synchronization to the received video standard. Note: Both 8-bit and 10-bit TRS words are identified by the device. Once synchronization has been achieved, the timing signal generator continues to monitor the received TRS timing information to maintain synchronization. The timing signal generator re-synchronizes all pixel and line based counters on every received TRS ID. Note that for correct operation of the timing signal generator, the SW_EN input pin must be set LOW, unless manual synchronous switching is enabled (Section 4.10.1). 42 of 150