ECE 3610 MICROPROCESSING SYSTEMS: A SPEECH RECORDER AND PLAYER. Using the Polling I/O Method

ECE 3610 MICROPROCESSING SYSTEMS: A SPEECH RECORDER AND PLAYER Using the Polling I/O Method 1

PROBLEM SPECIFICATION Design a microprocessing system to record and playback speech. Use a RED and GREEN LED to indicate the process. You may use any part from the following in your design: A basic micro-processor (You may use the HC11 or HSC12 instruction set). Three 512x8 ROM chips. Each ROM chip has one active high chip select (CS). One 256x8 ROM chip, with one active high chip select (CS). Eight 32Kx8 RAM chips. Each RAM chip has one active high chip select (CS). One 64x8 RAM chip, with one active high chip select (CS). Many 4-port PCIA chips. Each PCIA has one active high chip select (CS). Keypad with given truth table An ADC converter with the given specifications A DAC with the given specifications A square wave generator with the given specifications GREEN and RED LEDs 2

KEYPAD Example: R Pressed KP1 KP0 R S P V DD V SS 0 V 5 V KP1 KP0 R S P V DD V SS 5 V 0 V Power Supply KP1 (V) KP0 (V) FUNCTION 0 0 KEY NOT PRESSED 0 5 RECORD (R) PRESSED 5 0 PLAYBACK (P) PRESSED 5 5 STOP (S) PRESSED R P S 0 V 0 V Example: Key Not Pressed KP1 KP0 R S P V DD V SS Typically, one cannot press and release a key in less than 50 ms. 5 V 0 V Power Supply 3

GIVEN: SQUARE WAVE GENERATOR SQUARE WAVE GENERATOR F1 F0 V DD V SS SQ Power Supply From PCIA 0 V 5 V 5 V 0 V Example: 8 khz F1 F0 V DD V SS SQ 1 125 8 To PCIA F1 (V) F0 (V) 0 0 0 0 5 8 5 0 4 5 5 2 SQ Frequency (k Hz) Power Supply From PCIA 0 V 0 V 5 V 0 V F1 F0 V DD V SS Example: 0 V SQ 0 V To PCIA 4

GIVEN: Analog to Digital Converter (ADC) In general, and ADC periodically, converts an input analog voltage to an n-bit digital code output. The given ADC periodically converts an analog signal having FS=10.0 V (Range is 0.0 10.0 V) to a sequence of 8-bit digital codes. The ADC requires a take next sample control input (TNS). This input should be a periodic square wave whose positive edge tells the ADC when to take the next sample. After receiving the TNS signal, the ADC converts the analog sample to an 8-bit digital representation, which takes a certain amount of time. When complete, the ADC outputs the 8-bit sample, and provides a negative edge on the Data Ready (DR) pin. The DR pulse lasts for 10 μs. 10.0 V 0.0 V Analog Representation of Signal Analog Input TNS ADC DR 8 Digital Output RAM 00000101 11110111 11111100 11111101 11111011 11110111 Digital Representation of Signal 5

ADC: Converts an input analog voltage (0.0 10.0 V) to a sequence of 8-bit digital codes. Input Voltage Output Code 10.00 -------- 9.961 11111111 9.922 11111110 9.883 11111101 9.844 11111100 9.805 11111011 9.766 11111010 9.727 11111001 9.688 11111000 9.648 11110111 Example analog signal 0.273 0.234 0.195 0.156 0.117 0.078 0.039 0.000 00000111 00000110 00000101 00000100 00000011 00000010 00000001 00000000 Sample Time 1 2 3 4 5 6 RAM 00000101 11110111 11111100 11111101 11111011 11110110 Code Produced 00000101 11110111 11111100 11111101 11111011 11110110 Equal sampling intervals (assume Sampling Rate is 1000/s) 6

GIVEN: Digital to Analog Converter (DAC) In general, a DAC periodically, converts a sequence of digital codes to an analog output. The given DAC periodically converts a sequence of 8-bit digital codes to an analog signal having Range from 0.0 to 10.0 V, corresponding to codes from 00000000 to 11111111. The DAC requires a Convert Next Sample control input (CNS). This input should be a periodic square wave whose negative edge tells the DAC when to convert the next sample. RAM 00000101 11110111 11111100 11111101 11111011 11110110 Digital Input 8 CNS DAC Analog output Sequence of digital codes 7

Digital to Analog Converter (DAC) RAM 00000101 11110111 11111100 11111101 11111011 11110110 Digital Input 8 CNS DAC Analog output The given Digital to Analog Converter converts 8-bit digital samples to analog. The DAC needs a Convert Next Sample (CNS) to tell it when to convert the next digital sample to analog. DAC Output Original Analog Input CNS CNS CNS CNS CNS CNS Passing the DAC output through a Low Pass Filter would smoothen the edges, resulting in a signal which would more closely resemble the input signal. 00000101 11110111 11111100 11111101 11111011 11110110 Sequence Input to DAC 8

The user shall be able to control the system through the key pad. At any time the user can select the STOP, RECORD, or PLAYBACK function. For instance, during either playback or record, the user may select stop. Or, during record, the user may select stop or playback. The Keypad should be responsive. In other words, when a user presses a key, the system should execute that requested function immediately, without any perceived delay. 9

SOLUTION STARTS HERE 10

+ 5V PowerOn/Reset Device MIC NMIn VMA Address Decoder IRQn φ2 ROM_CS SpRAM_CS SyRAM_CS PCIA_CS LPF AMP DR ADC TNS SQ SQUARE WAVE GENERATOR RESETn CBUS ABUS μp DBUS A15-A13 F1 F0 8 A8-A0 A8-A0 D7-D0 CS 512x8 ROM A14-A0 A14-A0 D7-D0 CS 32Kx8 SpRAM A5-A0 A5-A0 D7-D0 CS 64x8 SyRAM A4-A0 RS4-RS0 D7-D0 CS 4-Port PCIA PC6 PD0 PA7-PA0 PB7-PB0 PC7 CS PC4 PC5 PC1-PC0 PC2 PC3 D7-D0 D7-D0 D7-D0 D7-D0 8 2 CNS DAC For the record function, I am using the SWG to provide the TNS signal for the ADC (8 khz square wave). The μp will take a sample from the ADC and store it into SpRAM on each negedge of DR, and this corresponds to each period of the SWG clock. LPF AMP KEYPAD R P S RED LED GRN LED 11

+ 5V PowerOn/Reset Device MIC NMIn VMA Address Decoder IRQn φ2 ROM_CS SpRAM_CS SyRAM_CS PCIA_CS LPF AMP DR ADC TNS SQ SQUARE WAVE GENERATOR RESETn CBUS ABUS μp DBUS A15-A13 F1 F0 8 A8-A0 A8-A0 D7-D0 CS 512x8 ROM A14-A0 A14-A0 D7-D0 CS 32Kx8 SpRAM A5-A0 A5-A0 D7-D0 CS 64x8 SyRAM A4-A0 RS4-RS0 D7-D0 CS 4-Port PCIA PC6 PD0 PA7-PA0 PB7-PB0 PC7 CS PC4 PC5 PC1-PC0 PC2 PC3 D7-D0 D7-D0 D7-D0 D7-D0 8 2 CNS DAC For the playback function, I am also using the SWG to provide my software a playback clock. The μp will send one speech sample from SpRAM to the DAC every period of this clock. Thus, speech recording and playback are done at the same rate. LPF AMP KEYPAD R P S RED LED GRN LED 12

+ 5V PowerOn/Reset Device NMIn IRQn RESETn CBUS ABUS μp DBUS For the record function: The μp turns the green LED on. MIC VMA Address Decoder φ2 ROM_CS SpRAM_CS SyRAM_CS PCIA_CS LPF AMP DR ADC TNS SQ SQUARE WAVE GENERATOR A15-A13 F1 F0 8 A8-A0 A8-A0 D7-D0 CS 512x8 ROM A14-A0 A14-A0 D7-D0 CS 32Kx8 SpRAM A5-A0 A5-A0 D7-D0 CS 64x8 SyRAM A4-A0 RS4-RS0 D7-D0 CS 4-Port PCIA PC6 PD0 PA7-PA0 PB7-PB0 PC7 CS PC4 PC5 b7 IFRC b0 PC1-PC0 PC2 PC3 D7-D0 D7-D0 D7-D0 D7-D0 8 2 CNS DAC The analog speech signal is digitized by the ADC each posedge of the TNS (sampling clock). After conversion is completed, the ADC outputs the 8-bit digital code and pulses DR. The μp polls interrupt flag PC6 to determine if DR has been pulsed. LPF AMP KEYPAD R P S RED LED GRN LED 13

+ 5V PowerOn/Reset Device MIC NMIn VMA Address Decoder IRQn φ2 ROM_CS SpRAM_CS SyRAM_CS PCIA_CS LPF AMP DR ADC TNS SQ SQUARE WAVE GENERATOR RESETn CBUS ABUS μp DBUS A15-A13 F1 F0 8 A8-A0 A8-A0 D7-D0 CS 512x8 ROM A14-A0 A14-A0 D7-D0 CS 32Kx8 SpRAM A5-A0 A5-A0 D7-D0 CS 64x8 SyRAM A4-A0 RS4-RS0 D7-D0 CS 4-Port PCIA PC6 PD0 PA7-PA0 PB7-PB0 PC7 CS PC4 PC5 PC1-PC0 PC2 PC3 D7-D0 D7-D0 D7-D0 D7-D0 8 2 CNS DAC For the record function (Cont d): When the IFRC6 flag is set, the μp reads the 8-bit sample and stores it into the Speech Buffer RAM (SpRAM), and then clears the flag. When the SpRAM becomes full the μp lights the RED and GREEN LEDs to indicate memory full, and then stops recording. LPF AMP KEYPAD R P S RED LED GRN LED 14

+ 5V PowerOn/Reset Device MIC NMIn VMA Address Decoder IRQn φ2 ROM_CS SpRAM_CS SyRAM_CS PCIA_CS LPF AMP DR ADC TNS SQ SQUARE WAVE GENERATOR RESETn CBUS ABUS μp DBUS A15-A13 F1 F0 8 A8-A0 A8-A0 D7-D0 CS 512x8 ROM A14-A0 A14-A0 D7-D0 CS 32Kx8 SpRAM A5-A0 A5-A0 D7-D0 CS 64x8 SyRAM A4-A0 RS4-RS0 D7-D0 CS 4-Port PCIA PC6 PD0 PA7-PA0 PB7-PB0 PC7 CS PC4 PC5 PC1-PC0 PC2 PC3 D7-D0 D7-D0 D7-D0 D7-D0 8 2 CNS DAC For the playback function: The μp turns the red LED on. Playback of speech samples always begins at the start of the SpRAM. The μp polls the flag for PC7 (IFRC7) to determine when the next sample should be sent to the DAC. LPF AMP KEYPAD R P S RED LED GRN LED 15

+ 5V PowerOn/Reset Device MIC NMIn VMA Address Decoder IRQn φ2 ROM_CS SpRAM_CS SyRAM_CS PCIA_CS LPF AMP DR ADC TNS SQ SQUARE WAVE GENERATOR RESETn CBUS ABUS μp DBUS A15-A13 F1 F0 8 A8-A0 A8-A0 D7-D0 CS 512x8 ROM A14-A0 A14-A0 D7-D0 CS 32Kx8 SpRAM A5-A0 A5-A0 D7-D0 CS 64x8 SyRAM A4-A0 RS4-RS0 D7-D0 CS 4-Port PCIA PC6 PD0 PA7-PA0 PB7-PB0 PC7 CS PC4 PC5 PC1-PC0 PC2 PC3 D7-D0 D7-D0 D7-D0 D7-D0 8 2 CNS DAC For the playback function (Cont d): When the flag becomes set, the μp reads an 8-bit sample from SpRAM and sends it to the DAC, pulses CNS, and then clears the flag. When the SpRAM becomes empty the μp lights the RED and GREEN LEDs to indicate memory empty, and then stops playing back. LPF AMP KEYPAD R P S RED LED GRN LED 16

Device A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VMA φ2 ROM PCIA SyRAM SpRAM 1 1 1 x x x x y y y y y y y y y 1 1 1 1 0 x x x x x x x x y y y y y 1 1 1 0 0 x x x x x x x y y y y y y 1 1 0 y y y y y y y y y y y y y y y 1 1 ROM_CS = A15 A14 A13 VMA φ2 PCIA_CS = A15 A14 A13n VMA φ2 SyRAM_CS = A15 A14n A13n VMA φ2 SpRAM_CS = A15n VMA φ2 ROM_SA: FE00 ROM_EA: FFFF PCIA_SA: C000 PCIA_EA: C01F SyRAM_SA: 8000 SyRAM_EA: 803F SpRAM_SA: 0000 SpRAM_EA: 7FFF 17

PCIA EQUATES/MEMORY MAP PCI_BASE EQU $C000 CRA EQU $C000 DRA EQU $C001 DIRA EQU $C002 IERA EQU $C003 IFRA EQU $C004 PRA EQU $C005 CRB EQU $C008 DRB EQU $C009 DIRB EQU $C00A IERB EQU $C00B IFRB EQU $C00C PRB EQU $C00D CRC EQU $C010 DRC EQU $C011 DIRC EQU $C012 IERC EQU $C013 IFRC EQU $C014 PRC EQU $C015 Memory Address Memory Contents PCIA_BASE C000 CRA C001 DRA C002 DIRA C003 IERA C004 IFRA C005 PRA C006 C007 C008 CRB C009 DRB C00A DIRB C00B IERB C00C IFRB C00D PRB C00E C00F C010 CRC C011 DRC C012 DIRC C013 IERC C014 IFRC C015 PRC 18

ROM_BASE EQU $FE00 SpRAM_BASE EQU $0000 SyRAM_BASE EQU $8000 19

0000 7FFF 8000 803F 8040 23K x 8 SpRAM 64 x 8 SyRAM NOT USED The SpRAM is used for the Speech Buffer. The SyRAM is used variables and the stack. A ROM is placed at the top of the memory space, because the vector table is designed to be at the top of the memory space in the architecture of the basic μp we are studying in this course. The 4-Port PCIA is mapped from C000 to C01F. BFFF C000 C01F C020 FDFF FE00 FFFF 4-PORT PCIA NOT USED 512 x 8 ROM The 4 th port (Port D) is not used. 20

SOLUTION #1 POLLING METHOD These slides demonstrate the polling I/O method design for the speech recorder and player. Next set of slides show the interrupt I/O method design. 21

Power On or Hardware Reset Reset mops See Lecture 17 LDS StackSA Hardware Function PCIAINIT The polling subroutine will simultaneously poll the keypad for user function, the ADC for recording speech, and the DAC for playing back speech. Software Function BUFFINIT LEDINIT SWGINIT Do Polling 22

Enter CMD STOP P_PTR SBUF_BASE R_PTR SBUF_BASE PC1 PC0 KEYPAD R P S KP1 KP0 FUNCTION 0 0 KEY NOT PRESSED 0 5 RECORD (R) PRESSED 5 0 PLAYBACK (P) PRESSED 5 5 STOP (S) PRESSED ORG SpRAM_BASE SBUF_BASE DS.B 32767 BEND DS.B ORG SyRAM_BASE P_PTR DS.W 1 R_PTR DS.W 1 CMD DS.B 1 A KP A A %00000011 FILTER OUT UNWANTED BITS Next KP EQU N DRC A==0 Key Not Pressed? N Y CMD A UPDATE CMD CMD== REC? Y Record Subroutine N CMD== PLAY? Y Playback Subroutine N CMD== STOP? Y Stop Subroutine Processes the Last Key Pressed 23

ADC DR 8 SBUF_BASE 0000 During Recording RED LED GRN LED One 8-bit speech sample sent from ADC to RAM each 125 μs (8 khz). ORG SpRAM_BASE SBUF_BASE DS.B 32767 BEND DS.B ORG SyRAM_BASE P_PTR DS.W 1 R_PTR DS.W 1 CMD DS.B 1 BEND 7FFF When Full RED LED GRN LED 24

SBUF_BASE 0000 During Recording RED LED GRN LED 8 CNS DAC One 8-bit speech sample sent from RAM to DAC each 125 μs (8 khz). BEND 7FFF When Full RED LED GRN LED ORG SpRAM_BASE SBUF_BASE DS.B 32767 BEND DS.B ORG SyRAM_BASE P_PTR DS.W 1 R_PTR DS.W 1 CMD DS.B 1 25

PCIAINIT FLOW CHART (PORT A) ADC DR TNS 8 PCIA CLR DIRA BSET PRA, $FF PA7-PA0 Enter PCIAINIT BSET CRA, $01 Enable PortA: CRA0 1 Establish PA7-PA0 as input to receive the 8-bit sample from the ADC: DIRA %0000 0000 We don t care about the polarity on the data lines PA7-PA0, but choose something. PRA $FF Since we re not using interrupts, we need to disable interrupts on these bits for safety. IERA %0000 0000 We don t care about the flags of these bits of Port A, but clear them anyway: IFRA 0 Configure Port B CLR IERA BCLR IFRA, $FF 26

PCIAINIT FLOW CHART (PORT B) PCIA PD0 PB7-PB0 8 CNS DAC BSET DIRB, $FF BSET PRB, $FF LPF AMP Configure Port B Enable PortB: CRB0 1 BSET CRB, $01 Establish PB7-PB0 as output to send speech samples to the DAC: DIRB %1111 1111 We don t care about the polarity on the data lines PB7-PB0, but choose something. PRB $FF CLR IERB Not using interrupts on these pins, but need to disable interrupts on these bits for safety. IERB %0000 0000 BCLR IFRB, $FF We don t care about the flags of these bits of Port B, but clear them anyway: IFRB 0 Configure Port C 27

PCIAINIT FLOW CHART (PORT C) SQ SQUARE WAVE GENERATOR PC1-PC0 PC2 PC3 2 F1 F0 Enable PortC: CRC0 1 BSET CRC, $01 Establish PC5-PC4 as output to set the sampling frequency of the SWG; PC2-PC3 as output to drive the LEDs; PC6 as input to receive DR from the ADC; PC7 as input to receive the square wave; and PC1-PC0 as input to receive the Keypad code: DIRC %0011 1100 BSET DIRC, %00111100 BCLR DIRC, %11000011 BSET PRC, $80 BCLR PRC, $7F PC7 PC4 PC5 KEYPAD R P S RED LED GRN LED Configure Port C Configure the polarity of PC7 and PC6 to be positive and negative edge sensitive, respectively, to receive do next sample and DR signals, and don t care about the others. PRC %10000000 DR ADC TNS 8 PC6 CLR IERC Not using interrupts in this example. Need to disable interrupts on these bits for safety. IERC %0000 0000 BCLR IFRC, $FF Need to clear the flags IFRC7-6; may as well clear them all: IFRC 0 Configure Port D 28

PCIAINIT FLOW CHART (PORT D) PCIA PD0 PB7-PB0 8 CNS DAC BSET DIRD, $FF BSET PRD, $FF LPF AMP Configure Port D Enable PortD: CRD0 1 BSET CRD, $01 Establish PD0 as output to send CNS to the DAC: DIRB %1111 1111 We don t care about the polarity on the data lines PD7-PD0, but choose something. PRD $FF CLR IERD Not using interrupts on these pins, but need to disable interrupts on these bits for safety. IERD %0000 0000 BCLR IFRD, $FF We don t care about the flags of these bits of Port B, but clear them anyway: IFRD 0 RTS 29

PCIAINIT BSET CRA, $01 CLR DIRA BSET PRA, $FF CLR IERA BCLR IFRA, $FF BSET CRB, $01 BSET DIRB, $FF BSET PRB, $FF CLR IERB BCLR IFRB, $FF BSET CRC, $01 BSET DIRC, %00111100 BCLR DIRC, %11000011 BSET PRC, $80 BCLR PRC, $7F CLR IERC BCLR IFRC, $FF BSET CRD, $01 BSET DIRD, %11111111 BSET PRD, $FF CLR IERD BCLR IFRD, $FF RTS 30

SPEECH BUFFER INITIALIZATION SpRAM_BASE EQU $0000 SyRAM_BASE EQU $8000 ORG SpRAM_BASE SBUF_BASE DS.B 32767 BEND DS.B 1 ORG SyRAM_BASE P_PTR DS.W 1 R_PTR DS.W 1 CMD DS.B 1 Allocation of speech buffer RAM and variables. 32K = 32768 Speech buffer variables initialization. X SBUF_BASE P_PTR X R_PTR X Return BUFFINIT ldx #SBUF_BASE stx P_PTR stx R_PTR rts 31

ON EQU 1 OFF EQU 0 PCIA PC2 PC3 RED LED GRN LED RED_LED OFF GRN_LED OFF LEDINIT bclr DRC, %00001100 rts Return 32

NOFUNC EQU 0 REC EQU 1 PLAY EQU 2 STOP EQU 3 KP EQU DRC KP1 KP0 FUNCTION 0 0 KEY NOT PRESSED 0 1 RECORD (R) PRESSED 1 0 PLAYBACK (P) PRESSED 1 1 STOP (S) PRESSED KEYPAD PC1 PC0 R P S 33

F1 F0 SQ FREQUENCY (khz) 0 0 NONE 0 5 8 5 0 4 5 5 2 8 khz: F1 0 F0 1 PC7 Return SQ SQUARE WAVE GENERATOR F1 F0 PC4 PC5 SWGINIT bclr DRC, %00010000 bset DRC, %00100000 rts 34

DO POLLING FLOW CHART Enter CMD STOP P_PTR SBUF_BASE R_PTR SBUF_BASE Next A KP A A %00000011 FILTER OUT UNWANTED BITS A==0 Key Not Pressed? N Y CMD A UPDATE CMD crec NOFUNC EQU 0 REC EQU 1 PLAY EQU 2 STOP EQU 3 Polling ldaa #STOP staa CMD ldx #SBUF_BASE stx P_PTR stx R_PTR next ldaa KP CMD= REC? PC1-PC0 CMD= Nanda N PLAY #%00000011? cmpa #NOFUNC beq crec update staa CMD crec N CMD= S? Y Y Y Record Playback Stop 2 KEYPAD R P S KP EQU DRC ORG P_PTR DS.W 1 R_PTR DS.W 1 CMD DS.B 1 SyRAM_BASE 35

DO POLLING FLOW CHART crec ldab CMD cmpb Enter #REC bne s1 CMD STOP jsr record P_PTR SBUF_BASE R_PTR bra SBUF_BASE next s1 cmpb #PLAY A KP A bne A %00000011 s2 FILTER OUT UNWANTED BITS jsr play bra next A=0 Y s2 cmpb #STOP? bne s3 N jsr stop s3 bra next CMD A UPDATE CMD NOFUNC EQU 0 REC EQU 1 PLAY EQU 2 STOP EQU 3 Next crec CMD= REC? Record Subroutine N s1 CMD= PLAY? Playback Subroutine ORG SpRAM_BASE SBUF_BASE DS.B 32767 BEND DS.B 1 ORG SyRAM_BASE P_PTR DS.W 1 R_PTR DS.W 1 CMD DS.B 1 N s3 N CMD= STOP? Y Y Y s2 Stop Subroutine 36

Enter Reset P_PTR Get R_PTR R_PTR == BEND+1? N GRN_LED ON RED_LED OFF recording Next Sample Ready? Y Clear DR Flag. Get Sample. Store Sample. Increment R_PTR. N stopr Y ADC DR TNS 8 GRN_LED ON RED_LED ON memory full Clear DR Flag Y R_PTR == BEND+1? PC6 PA7-PA0 N rtnr Return record ldx #SBUF_BASE stx P_PTR ldx R_PTR cpx #BEND+1 beq stopr bset DRC,%00001000 bclr DRC,%00000100 brclr IFRC,$40,rtnR bclr IFRC,$40 ldaa DRA staa 0,x PC2 inx PC3 stx R_PTR cpx #BEND+1 bne rtnr stopr bset DRC,%00001100 bclr IFRC,$40 rtnr rts RED LED GRN LED 37

playback Reset R_PTR Get P_PTR P_PTR == BEND+1? N GRN_LED OFF RED_LED ON playing Time To Output Next Sample? Y Clear SWG Flag Get Sample. Write Sample. Increment P_PTR. stopp N Y SQ SQUARE WAVE GENERATOR Y P_PTR == BEND+1? PC7 GRN_LED ON RED_LED ON memory empty Clear SQ Flag N rtnp Return playback ldx #SBUF_BASE stx R_PTR ldx P_PTR cpx #BEND+1 beq stopp PC2 PC3 bset DRC,%00000100 bclr DRC,%00001000 brclr IFRC,$80,rtnP bclr IFRC,$80 ldaa 0,x PD0 staa DRB PB7-PB0 BCLR DRD,$01 BSET DRD,$01 inx 8 stx P_PTR cpx #BEND+1 bne rtnp stopp bset DRC,%00001100 bclr IFRC,$80 rtnp rts RED LED GRN LED CNS DAC 38

Enter Return 39

SpRAM_BASE EQU $0000 SyRAM_BASE EQU $8000 0000 23K x 8 SpRAM ORG SpRAM_BASE SBUF_BASE DS.B 32767 BEND DS.B 1 7FFF 8000 803F 8040 64 x 8 SyRAM NOT USED ORG SyRAM_BASE P_PTR DS.W 1 R_PTR DS.W 1 CMD DS.B 1 ORG SyRAM_BASE+$30 ESTACK DS.B 15 StackSA DS.B 1 BFFF C000 C01F C020 FDFF FE00 FFFF 4-PORT PCIA NOT USED 512 x 8 ROM 40

FIRMWARE: ASSEMBLY LANGUAGE IMAGE (1) CRA EQU $C000 DRA EQU $C001 DIRA EQU $C002 IERA EQU $C003 IFRA EQU $C004 PRA EQU $C005 CRB EQU $C008 DRB EQU $C009 DIRB EQU $C00A IERB EQU $C00B IFRB EQU $C00C PRB EQU $C00D CRC EQU $C010 DRC EQU $C011 DIRC EQU $C012 IERC EQU $C013 IFRC EQU $C014 PRC EQU $C015 NOFUNC EQU 0 REC EQU 1 PLAY EQU 2 STOP EQU 3 KP EQU DRC ROM_BASE EQU $FE00 SpRAM_BASE EQU $0000 SyRAM_BASE EQU $8000 ORG SpRAM_BASE SBUF_BASE DS.B 32767 BEND DS.B 1 ORG SyRAM_BASE P_PTR DS.W 1 R_PTR DS.W 1 CMD DS.B 1 BSET CRD, $01 BSET DIRD, %11111111 BSET PRD, $FF CLR IERD BCLR IFRD, $FF RTS ORG SyRAM_BASE+$30 ESTACK DS.B 15 StackSA DS.B 1 ORG $FFF8 ISR_Vector FDB Main_SA SWI_Vector FDB Main_SA NMI_Vector FDB Main_SA RESET_Vector FDB Main_SA Main_SA ORG ROM_BASE lds #StackSA jsr PIAINIT jsr BUFFINIT jsr LEDINIT jsr SWGINIT Loop jsr Polling bra Loop PCIAINIT BSET CRA, $01 CLR DIRA BSET PRA, $FF CLR IERA BCLR IFRA, $FF BSET CRB, $01 BSET DIRB, $FF BSET PRB, $FF CLR IERB BCLR IFRB, $FF BSET CRC, $01 BSET DIRC, %00111100 BCLR DIRC, %11000011 BSET PRC, $80 BCLR PRC, $7F CLR BCLR IERC IFRC, $FF 41

FIRMWARE: ASSEMBLY LANGUAGE IMAGE (2) BUFFINIT ldx #SBUF_BASE stx P_PTR stx R_PTR rts LEDINIT bclr DRC, %00001100 rts SWGINIT bclr DRC, %00010000 bset DRC, %00100000 rts Polling ldaa #STOP staa CMD ldx #SBUF_BASE stx P_PTR stx R_PTR next ldaa DRC 3, 30 anda #%00000011 4, 31 cmpa #NOFUNC 5, 32 beq crec 6, 33 update staa CMD 7, crec ldab CMD 8, 34 cmpb #REC 9, 35 bne s1 10,36 jsr record 11, 28, 37 bra next 2, 29 s1 cmpb #PLAY bne s2 jsr play bra next s2 cmpb #STOP bne s3 jsr stop s3 bra next record ldx #SBUF_BASE 12, 38 stx P_PTR 13, 39 ldx R_PTR 14, 40 cpx #BEND+1 15, 41 beq stopr 16, 42 rec bset DRC,%00001000 17, 43 bclr DRC,%00000100 18, 44 brclr IFRC,$40,rtnR 19 bclr IFRC,$40 20 ldaa DRA 21 staa 0,x 22 inx 23 stx R_PTR 24 cpx #BEND+1 25 bne rtnr 26 stopr bset DRC,%00001100 bclr IFRC,$40 rtnr rts 1, 27 playback ldx #SBUF_BASE stx R_PTR ldx P_PTR cpx #BEND+1 beq stopp play bset DRC,%00000100 bclr DRC,%00001000 brclr IFRC,$80,rtnP bclr IFRC,$80 ldaa 0,x BCLR DRD,$01 staa DRB BSET DRD,$01 inx stx P_PTR cpx #BEND+1 bne rtnp stopp bset DRC,%00001100 bclr IFRC,$80 rtnp rts stop rts 42

SPEECH BUFFER MEMORY MAP Memory Address SBUF_BASE 0000 Memory Contents The BUFFER holds speech samples; It can hold a maximum of 32,768 samples. For a sampling rate of 8000 S/s, this means it can holds about 4s of speech. When the end of the SBUF is reached, the system stops the record process and shines the RED and GRN LEDs to indicate the buffer is full. BEND 7FFF 43

Memory Address P_PTR 8000 8001 R_PTR 8002 8003 CMD 8004 Allocated Stack end 8030 Memory Contents Analyzing the firmware, we see that the stack grows to its largest size when it enters the record, playback or stop subroutines in the polling routine. Therefore, we need to allocate a minimum of 4 locations for the stack. Note: we actually allocated 16 locations, for safety. The record and play pointers are stored in sys RAM as well. Actual StackEA StackSA 803C 803F Finally, the CMD is stored in SyRAM. 44

DETAILED ROM MEMORY MAP Memory Address Main_SA FE00 Main_EA???? Memory Contents Analyzing the firmware, we see that Main requires? 10 =? 16 bytes. Main_EA = FE00 +? -1 =? The IRQ, SWI, and NMI routines are the same as the RESET routine. IRQ Vector FFF8 Main_SA HB FFF9 Main_SA LB SWI Vector FFFA Main_SA HB FFFB Main_SA LB NMI Vector FFFC Main_SA HB FFFD Main_SA LB RESET Vector FFFE Main_SA HB FFFF Main_SA LB 45

ANALYSIS: MAX RECORDING TIME 1. How many speech samples can this system store in memory? Answer: 32768 Samples. 2. What is the maximum length of time of speech that can be recorded? Answer: 32768 S/8000 S/s = 4.096 s. 46

ANALYSIS: PROCESSING TIME 3. What is the maximum amount of time required by the μp to read a sample, store it into memory, and be ready for the next sample? Can the processor keep up to the sampling rate? Will it miss any samples? ADC Conversion Time ADC Conversion Time DR 125 μs(1/8 khz) Processing Time 47

WORST CASE SCENARIO The maximum time is found by considering that DR is asserted immediately after the software checks for it. This means the software will have to make another round trip around the polling routine to check it again. record rtnr brclr IFRC,$40,rtnR rts Worst case: DR is asserted immediately after this instruction checks for it. In this case, software must do a round trip to get back to check the flag for DR again. 48

next ldaa DRC 3, 29 anda #%00000011 4, 30 cmpa #NOFUNC 5, 31 beq crec 6, 32 staa CMD 7, crec ldab CMD 8, 33 cmpb #REC 9, 34 bne s1 10,35 jsr record 11,36 bra next 2, 28 record ldx #SBUF_BASE 12, 37 stx P_PTR 13, 38 ldx R_PTR 14, 39 cpx #BEND+1 15, 40 beq stopr 16, 41 rec bset DRC,%00001000 17, 42 bclr DRC,%00000100 18, 43 brclr IFRC,$40,rtnR 19, 44 bclr IFRC,$40 20 ldaa DRA 21 ;Record continuation staa 0,x 22 inx 23 stx R_PTR 24 cpx #BEND+1 25 bne rtnr 26 stopr bset DRC,%00001100 rtnr rts 1, 27 49

TRACING DIFFERENT PATHS (THREADS) FIND MAX PATH Analyzing the firmware, we see that the at most 44 instructions are required in the worst case. (See the numbered instructions.) If each instruction takes 4 cycles on average, then 176 cycles are required. For a clock speed of 2 MHz, this will take 88 μs. 125 μs(1/8 khz) Processing Time 88μs 50