EM MICROELECTRONIC - MARIN SA EM616 Digitally programmable 65 and 81 multiplex rate LCD Controller and Driver Features Slim IC for COG, COF and COB technologies I C & Serial bus interface Internal display data RAM digitally programmable multiplex rates : - 81 rows x 1 columns - 65 rows x 118 columns LCD supply voltage internally generated and digitally programmable from 4.5V to 11V Low operating current consumption: 14μA (typ) No external components needed except one V LCD and one VDD capacitor On chip - 4 intermediate bias voltages generation - Oscillator for LCD refresh (no external components required) High noise immunity on inputs Row and column drivers mirroring for COG or COF connections flexibility Partial display mode with 17 active rows for current consumption reduction Sleep mode for a nearly zero current consumption Wide V DD supply voltage from.4v to 3.3V Wide temperature range: -4 C to +85 C Typical Applications Mobile phones Smart cards Portable, battery operated products Balances and scales, utility meters Typical Operating Configuration 41 row drivers EM616 4 row drivers 1 columns outputs SDA SCL V LCD RES Vss1 Vss V DD1 V DD V HV Pin Configuration Mark 4 S1 S SDA SCL S13 Figure 1 S9 Mark S3 Description The EM616 is a bit map controller and driver for full dot matrix monochrome STN LCD displays. The driving capability is 81 rows x 1 columns (1 rows of characters + one row of icons) or 65 rows x 118 columns (8 rows of characters + one row of icons). There is a one to one relation between LCD pixels and bits of the Display Data RAM. The EM616 is an extremely low power consumption LCD controller and driver product. The typical current consumption is about 14μA with no external component except the capacitors connected to V LCD and VDD. One important feature on EM616 is the partial display mode, which enables important current consumption reduction. With this function selected, only 17 rows remain active, needed V LCD decreases and the commutation frequencies of row and column drivers are also decreased. These three effects of partial display mode reduce drastically current consumption. V DD V LCD V LCD V LCD test fr reset CS I V DD V DD V DD V DD V PP V HV V HV V HV V HV S183 EM616 S91 S9 S171 S153 Mark 3 Mark 1 S17 S154 Figure 1 www.emmicroelectronic.com
Features 1 Description 1 Typical Applications 1 Typical Operating Configuration 1 Pin Configuration 1 1 Absolute Maximum Ratings 4 Handling Procedures 4 3 Operating Conditions 4 4 Electrical Characteristics 4 5 Timing Characteristics 5 5.1 Timing Waveforms 6 6 Block diagram 8 7 Pin description 9 8 Functional description 1 8.1 Selection of interface type 1 8. Serial interface 1 8.3 I C interface 1 8.3.1 Start and stop conditions 1 8.3. Bit transfer 1 8.3.3 Acknowledge 1 8.4 I C protocol 1 8.4.1 Write mode 1 8.4. Read Mode (RW = 1) 13 8.5 Display Data RAM 13 8.5.1 DDRAM description 13 8.5. DDRAM addressing 17 8.6 Initialization of EM616 8.7 Description of instructions 3 8.7.1 Initialization 3 8.7.1.1 Mux Mode 3 8.7.1. TC[1:] 3 8.7.1.3 Inv. Row 4 8.7.1.4 MX 5 8.7.1.5 Blank 5 8.7.1.6 Checker 5 8.7.1.7 Inv. Video 5 8.7. Initialization 1 8 8.7..1 X[6:] 8 8.7.. V 8 8.7.3 Initialization 8 8.7.3.1 Y[3:] 8 8.7.3. Vlcd Dischg. 8 8.7.3.3 DEC 8 8.7.3.4 LSB 8 8.7.4 Initialization 3 8 8.7.4.1 Vlcd Level[7:] 8 8.7.5 Initialization 4 9 8.7.5.1 Mult[1:] 9 www.emmicroelectronic.com
8.7.5. Partial Display 9 8.7.5.3 First Row PD[3:] 9 8.7.5.4 Sleep 9 8.7.6 Test to 3 9 8.8 LCD outputs 3 8.9 LCD refresh frequency 31 8.1 V LCD depending on V HV 31 8.11 LCD driver waveforms 3 8.11.1 Partial Display 35 9 Typical Application 37 Power ON recommended flow 4 1 Pad location 43 11 Ordering Information 46 3 www.emmicroelectronic.com
1 Absolute Maximum Ratings Parameter Symbol Conditions Supply voltage range V DD1, -.3V to +3.6V Supply voltage range V HV -.3V to +3.6V Supply voltage range V LCD V HV -.3V to +1V All input voltages V LOGIC -.3V to V DD1, +.3V Voltages at S to S 184 V DISPLAY -.3V to V LCD +.3V Storage temperature range T STO -65 C to +15 C Maximum soldering conditions T SMAX 5 C 1 s Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction. Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. 3 Operating Conditions Parameter Symbol Min. Typ. Max. Operating temperature T A -4 +85 C Logic supply voltage V DD1,.4.5 3.3 V High voltage generator V HV.4.5 3.3 V supply voltage LCD supply voltage V LCD 4.5 8 11 V 4 Electrical Characteristics 1, = V, V DD1 = V DD =.4V, V HV =.4V, unless otherwise specified. T A = -4 C to +85 C unless otherwise specified. Minimum required capacitor: 1μF on V LCD, 1nF on V DD1, and V HV. Parameter Symbol Test conditions Min. Typ. Max. Units Supply Current Sleep mode I DD T A = 5 C, Sleep = 1 1 na Sleep mode I HV T A = 5 C, Sleep = 1.8 μa Normal LCD refresh mode I DD T A = 5 C, (note 1) 17 μa Normal LCD refresh mode I HV T A = 5 C, (note ) 14 18 μa Partial LCD refresh mode I HV T A = 5 C, (note 3) 5 9 μa Control Input Signals Input leakage I IN V i = V ss1 or V DD1-1 1 μa Low level input voltage V IL.3xV DD1 V High level input voltage V IH.7xV DD1 V Low Level Output Current SDA I OL_SDA V OL_SDA =.4V 1.6 ma LCD Outputs Internally generated LCD supply voltage T A = 5 C, V LCD 1111b (Hex: B) 4.53 V T A = 5 C, V LCD 1111b (Hex: 8E) 8. V V LCD step between consecutive programmed V LCD Level V LCD step 35. mv V bias tolerance V bias tol. (note 4) -8 8 mv Typical load C LOAD 1. pf/pixel Note 1: Measured on V DD1 + V DD, all outputs open, SDA and SCL at, RES at V DD1, multiplex rate 81, x5 voltage multiplier, V LCD = 1111b, DDRAM loaded with checker pattern Note : Measured on V HV, same conditions as (note 1). Note 3: Measured on V HV, all outputs open, SDA and SCL at, RES at V DD1, partial display mode, voltage multiplier, V LCD = 1111b, DDRAM loaded with checker pattern. Note 4: V 1, V, V 3 and V 4 bias levels measured with V LCD = 7V, on 1 LCD row driver output and 1 LCD column driver output, multiplex rate 81, T A = 5 C, load = ±1μA, I load = 1µA to or V LCD V bias_tol is: ½(Vbias_ +1µA + Vbias_ -1µA ) Vbias_ theor (Vbias_ theor : see 8.8; e.g. for V1:.9xV LCD at Mux=81) 4 www.emmicroelectronic.com
5 Timing Characteristics 1, = V, V DD1 = V DD =.4V, V HV =.4V, T A = -4 C to +85 C unless otherwise specified. Parameter Symbol Test conditions Min. Typ. Max. Units Internal frame frequency for LCD refresh f FR (note 1) Minimum reset pulse width t RW 1 us IC timing characteristics SCL frequency f IC 16 khz SCL low period t LOW 35 ns SCL high period t HIGH 1 ns SDA setup time t SUDAT 1 ns SDA hold time t HDDAT ns SCL and SDA rise time t R ns SCL and SDA fall time t F ns Setup time for a repeated start condition Hold time for a start condition Setup time for a stop condition 75 x mux t SUSTA ns t HDSTA ns t SUSTO ns Spike width on SCL and SDA t SW 1 ns Time before a new transmission can start t BUF 1 ns Capacitive bus line load C b 4 pf Serial bus timing characteristics SCL frequency f SER 4 MHz SCL low period t CL 8 ns SCL high period t CH 13 ns SDA setup time t DS ns SDA hold time t DH 7 ns SCL rise time t CR ns SCL fall time t CF ns CS setup time t SUCS 1 ns CS hold time t HDCS 13 ns Time before a new transmission can start, CS minimum high time. Note 1: Measured on pad FR. t BUFCS 7 ns Hz 5 www.emmicroelectronic.com
5.1 Timing Waveforms SDA SCL Data line stable, data valid Change of data allowed Figure 3: I C 1 bit transfer SDA SCL S P Start condition Figure 4: I C start and stop conditions Stop condition SDA By transmitter Not Acknowledge SDA By receiver Acknowledge SCL S 1 8 9 Start condition Clock pulse for acknowledgement Figure 5: Acknowledgement on the I C bus 6 www.emmicroelectronic.com
SDA tbuf tlow tf SCL thigh thdsta tr thddat tsudat SDA tsusta Figure 6: I C timing diagram. tsusto Data stable, data valid Change of data allowed SDA SDA sampled on SCL falling edge SCL Data input setup time Data input hold time Figure 7: Serial interface, 1 bit transfer. Data input setup time Data input hold time tdh tds SDA tcl tcf SCL tch tcr tbufcs tsucs thdcs CS Figure 8: Serial interface timing diagram. 7 www.emmicroelectronic.com
6 Block diagram S to S183 V HV Voltage Multiplier Intermediate voltages generation LCD levels selection V LCD Gating 1 uf external capacitor Internal Oscillator 81 bits sequenceur Blank, Video, Checker V PP V DD 1 V DD 1 DB7 to DB Display Data RAM 1x118 8x(8x118) x(8x1) x-address y-address RES IC / serial 3 wires interface x-address and y-address generator SDA SCL CS I Figure 9: Block diagram. 8 www.emmicroelectronic.com
7 Pin description Symbol Pad Type Description S to S 183 Output LCD driver outputs S to S 3 and S 151 to S 183 Output LCD row driver outputs S = S 183 S 33 to S 4 and S 143 to S 15 Output LCD row driver outputs when multiplex rate 81 is selected LCD column driver outputs when multiplex rate 65 is selected S 41 to S 14 Output LCD column driver outputs V HV Positive power supply Supply voltage for internal voltage multiplier V DD1, Positive power supply Supply voltage for logical and analog parts V PP Positive power supply Supply voltage for OTP 1, Ground power supply Ground power supply I Input Interface protocol selection input RES Input External reset input, active low CS Input Chip select input FR Input/output Frame frequency input/output TEST Input/output Test SDA Input/output Serial data input SCL Input Serial clock V LCD Positive power supply LCD supply voltage Table 1: Pin description S to S183: Connected to LCD electrodes, it should be left open if not used. S and S183 are internally connected together. V HV : Supply voltage for internal voltage multiplier, it could be a different voltage value than for V DD1,. V DD1, V PP : 1, : Logic and analog power supplies. V DD1, V DD and V PP are not connected inside EM616but have to be connected outside to the same potential. For chip on glass application, it is advised to keep V DD1 and V DD separated until their connection to 1 μf capacitor. Ground supply for logic and high voltage generator. 1 is connected to substrate. Same precautions than for V DD1, should be taken to connect these pads. I: Selects the chosen interface protocol. For chip on glass applications, it can be directly connected to 1 or V DD1 on glass. RES: CS: FR: TEST: SDA: SCL: V LCD : External reset, a reset cycle must be applied at power on (reset at low level when power on). Note that the outputs S = S 183 are at VLCD level when reset is active. If this static state is applied during long time the LCD could be damaged. Active low chip select, when serial interface is used it enables data transfer. If I C is used, it must be connected at 1 or V DD1 pads. Outputs LCD refresh frame frequency, used for test. It must be left open. Test pad, it must be left open. Serial data input used for I C interface as for 3 wires serial interface. Serial clock input used to latch SDA for I C interface as for 3 wires serial interface. LCD voltage supply (generation of LCD waveforms applied to S to S183). It is normally internally generated from V HV supply voltage. 1 μf capacitor is required between V LCD and. A forward biased diode is connected between V HV and V LCD, therefore V LCD must be programmed higher than V HV. External power supply is also possible; in this configuration, V LCD must be programmed at its lowest value and V HV connected to. 9 www.emmicroelectronic.com
8 Functional description 8.1 Selection of interface type There are two different serial interfaces available on EM616. Selection depends on logical value applied on input I. If I =, serial interface is selected: 3 wires with Chip Select CS, Serial Clock SCL and Serial Data SDA. If I = 1, I C protocol is selected: wires with Serial Clock SCL and Serial Data SDA. CS must be connected to or V DD1. I Interface 3 wires serial interface 1 I C Table : Interface selection 8. Serial interface The serial interface consists of 3 wires: Chip Select CS, Serial Clock SCL and Serial Data SDA. The information is exchanged byte-wide and is shifted serially in the LCD driver at SCL falling edge. SDA Data sampled on SCL fall edge SCL Data stable, data valid Change of data allowed Figure 1: Serial interface, 1 bit transfer Transfer data direction is from microcontroller to EM616. When CS is activated at low level, the communication is enabled and CS must stay low for the rest of the transmission. Data transfer begins with one control byte. This control byte is transfered MSB first; it consists in: MSB LSB C DC Test[] Test[1] Test[] Ini[] Ini[1] Ini[] C is the continuation bit: If C = 1, the control byte is followed by 1 data byte only, the next byte is a new control byte. If C =, all the following bytes are data bytes until data transfer is stopped. DC selects data bytes or command bytes to be sent after the control byte: If DC = 1, the following data byte(s) is (are) written into the Display Data RAM. First data byte is stored at the address specified by the x-address and y-address pointers. Data pointers are automatically updated for each byte written in the DDRAM (see DDRAM description). IF DC =, the following data byte is a command byte. It enables initialization of functions (multiplex rate, number of voltage multiplier stages, V LCD programming, partial display settings ). 1 www.emmicroelectronic.com
Bytes ini, ini1 and ini select the initialization register which will be set by the following command byte (see Table 4: EM616 instructions). CS start stop Control Byte Data Byte Control Byte Data Byte Control Byte Data Byte C = 1 Command byte C = 1 DDRAM Data byte C = DDRAM Data byte DC = n bytes DC = 1 DC = 1 n bytes n bytes Figure 11: serial interface protocol Data byte is transfered with MSB bit first, LSB bit last: MSB LSB DB7 DB6 DB5 DB4 DB3 DB DB1 DB If CS goes high during a byte transfer, this byte is invalid, but all previously transmitted data are valid. While CS is high, the serial interface is kept in reset and data transfer is disabled. To prevent transmission errors, CS should be at high level when transfer is stopped. 11 www.emmicroelectronic.com
8.3 I C interface The EM616 can be interfaced with a slave I C protocol (see description IC protocol). The I C bus consists in wires: SCL (Serial Clock Line) and SDA (Serial Data Line). Both lines must be connected to V DD1, via pull up resistors. EM616 pad SCL is input, pad SDA is bi-directional with open drain NMOS driver. EM616 supports initialization and RAM write and status read access. 8.3.1 Start and stop conditions Data transfer begins by a falling edge on SDA when SCL is at high level, this is the start condition (S), initiated by the I C bus master. It is stopped with a rising edge on SDA when SCL isat high level, this is the stop condition (P) (see Figure 4: IC start and stop conditions). 8.3. Bit transfer One data bit is transfered by each SCL pulse. The data on the SDA line must remain stable during the high period of SCL pulses, as any changes at this time would be interpreted as start or stop conditions. Data is always transfered with MSB first. 8.3.3 Acknowledge After a start condition, data bits are transfered to EM616. Each byte is followed by an acknowledge bit: the transmitter lets the SDA line at high level (by pull up resistor) and generates an SCL pulse; if transfer concerns the EM616 slave receiver and has performed correctly, EM616 generates a low SDA level (NMOS activated). SDA remains stable during the high period of the acknowledge related SCL pulse. After acknowledge, EM616 lets SDA line free, enabling the transmitter to continue transfer or to generate a stop condition. 8.4 I C protocol The EM616 has the slave address coded on 7 bits:. After a start condition, the slave address + RW bit must be sent first. If the slave address does not match with the EM616 one, there is no acknowledge from LCD driver and the following data transfer will not affect the EM616. If the slave address corresponds to EM616 slave address, it will acknowledge (pull SDA down to logical low level) and data transfer is enabled. The 8th bit RW sets the chip in write mode or read status mode, it is read for data transfer. 8.4.1 Write mode If RW =, data are written into EM616 by the microcontroller. Data transfer bytes can be either control bytes or data bytes. Data transfer always begins with a control byte (described in fig.1). It sets bits C, DC, ini, ini1 and ini C is the continuation bit: If C = 1, the control byte is followed by 1 data byte only, the next byte is a new control byte. If C =, all the following bytes are data bytes until data transfer is stopped. DC selects data bytes or command bytes to be sent after the control byte: If DC = 1, the following data byte(s) is (are) written into the Display Data RAM. First data byte is stored at the address specified by the x-address and y-address pointers. Data pointers are automatically updated for each byte written in the DDRAM (see DDRAM description). IF DC =, the following data byte is a command byte. It enables initialization of functions (multiplex rate, number of voltage multiplier stages, V LCD programming, partial display settings ). Bytes ini, ini1 and ini select the initialization register to be set by the following command byte (see Table 4: EM616 instructions). 1 www.emmicroelectronic.com
8.4. Read Mode (RW = 1) EM616 will output one status byte after slave address. This status byte consists in 8 initialization bits previously set by command bytes or the reset cycle (see Table 4: EM616 instructions). First byte sent: Control Byte: Data Byte: MSB LSB MSB LSB RW C DC Test[]Test[1]Test[] Ini[] Ini[1] Ini[] A DB7 DB6 DB5 DB4 DB3 DB DB1 DB A EM616 Slave Address Write mode: Acknowledge from EM616 Acknowledge from EM616 Acknowledge from EM616 Acknowledge from EM616 Acknowledge from EM616 S A 1 Control Byte A Data Byte A 1 Control Byte A Data Byte A P MSB LSB Slave Address C n bytes C 1 byte n bytes Write Mode Read mode: Acknowledge from EM616 Acknowledge from master S 1 A 1 Status Byte A P Slave Address Figure 1: I C protocol description 8.5 Display Data RAM The EM616 contains a RAM, which stores the display data; there is a one to one correspondence between the bit stored in the RAM and one LCD pixel. 8.5.1 DDRAM description DDRAM consists in: 1 bank of 118 bits (row ) 8 banks of 118 bytes (rows 1 to 64) banks of 1 bytes (rows 65 to 8) DDRAM is read row by row for display refresh. Each row corresponds to one row output pad, which is activated when the corresponding row in the DDRAM is read. DDRAM is accessed via the serial interface. Bytes are stored at the column specified by x-address pointer and the bank specified by y-address pointer. These pointers are set by the corresponding instruction Initialization 1 and Initialization and are automatically incremented or decrement after each byte written in the DDRAM (see DDRAM addressing and Table 5: Internal functions after reset.) For bank only data byte 7 (DB7) is stored in row, DB6 to DB are not used. For bank 1 to 1 (y-address = 1 to 1), DBX is stored at row ((8 x y-address)-x). 13 www.emmicroelectronic.com
If Mux Mode =, the DDRAM provides a 65 rows and 118 columns matrix. Bank 9 and 1 are not used for display refresh, the cells can not be addressed. - - - - - - - - - - - - - - - - - - - - - - - x-address - - - - - - - - - - - - - - - - - - - - - - - 117 Bank Bank 1 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 Row DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 Row 1 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 Row DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 Row 3 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 Row 4 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 Row 5 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Row 6 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 Row 7 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Row 8 Row 9 Row 1 8 Bank 8 Row 55 Row 56 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 Row 57 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6 Row 58 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5 Row 59 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4 Row 6 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 Row 61 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Row 6 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 Row 63 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Row 64 Bank 9 Rows not used Bank 1 Rows not used Figure 13: DDRAM description with Mux Mode = and LSB = 14 www.emmicroelectronic.com
If Mux Mode = 1, the DDRAM provides a 81 rows and 1 columns matrix. 8 columns on the left + 8 columns on the right are not used for display refresh, the cells can not be addressed. - - - - x-address - - - - 11 Columns not used Columns not used Bank DB7 DB7 DB7 DB7 DB7 DB7 Row DB7 DB7 DB7 DB7 DB7 DB7 Row 1 DB6 DB6 DB6 DB6 DB6 DB6 Row DB5 DB5 DB5 DB5 DB5 DB5 Row 3 Bank 1 DB4 DB4 DB4 DB4 DB4 DB4 Row 4 DB3 DB3 DB3 DB3 DB3 DB3 Row 5 DB DB DB DB DB DB Row 6 DB1 DB1 DB1 DB1 DB1 DB1 Row 7 DB DB DB DB DB DB Row 8 DB7 DB7 DB7 DB7 DB7 DB7 Row 9 DB6 DB6 DB6 DB6 DB6 DB6 Row 1 DB5 DB5 DB5 DB5 DB5 DB5 DB4 DB4 DB4 DB4 DB4 DB4 DB3 DB3 DB3 DB3 DB3 DB3 Bank 8 Bank 9 1 Bank 1 DB DB DB DB DB DB DB1 DB1 DB1 DB1 DB1 DB1 Row 55 DB DB DB DB DB DB Row 56 DB7 DB7 DB7 DB7 DB7 DB7 Row 57 DB6 DB6 DB6 DB6 DB6 DB6 Row 58 DB5 DB5 DB5 DB5 DB5 DB5 Row 59 DB4 DB4 DB4 DB4 DB4 DB4 Row 6 DB3 DB3 DB3 DB3 DB3 DB3 Row 61 DB DB DB DB DB DB Row 6 DB1 DB1 DB1 DB1 DB1 DB1 Row 63 DB DB DB DB DB DB Row 64 DB7 DB7 DB7 DB7 DB7 DB7 Row 65 DB6 DB6 DB6 DB6 DB6 DB6 Row 66 DB5 DB5 DB5 DB5 DB5 DB5 Row 67 DB4 DB4 DB4 DB4 DB4 DB4 Row 68 DB3 DB3 DB3 DB3 DB3 DB3 Row 69 DB DB DB DB DB DB Row 7 DB1 DB1 DB1 DB1 DB1 DB1 Row 71 DB DB DB DB DB DB Row 7 DB7 DB7 DB7 DB7 DB7 DB7 Row 73 DB6 DB6 DB6 DB6 DB6 DB6 Row 74 DB5 DB5 DB5 DB5 DB5 DB5 Row 75 DB4 DB4 DB4 DB4 DB4 DB4 Row 76 DB3 DB3 DB3 DB3 DB3 DB3 Row 77 DB DB DB DB DB DB Row 78 DB1 DB1 DB1 DB1 DB1 DB1 Row 79 DB DB DB DB DB DB Row 8 Figure 14: DDRAM description with Mux Mode = 1 and LSB = 15 www.emmicroelectronic.com
If Mux Mode = 1 and LSB=1. - - - - x-address - - - - 11 Columns not used Columns not used Bank DB DB DB DB DB DB Row DB DB DB DB DB DB Row 1 DB1 DB1 DB1 DB1 DB1 DB1 Row DB DB DB DB DB DB Row 3 Bank 1 DB3 DB3 DB3 DB3 DB3 DB3 Row 4 DB4 DB4 DB4 DB4 DB4 DB4 Row 5 DB5 DB5 DB5 DB5 DB5 DB5 Row 6 DB6 DB6 DB6 DB6 DB6 DB6 Row 7 DB7 DB7 DB7 DB7 DB7 DB7 Row 8 DB DB DB DB DB DB Row 9 DB1 DB1 DB1 DB1 DB1 DB1 Row 1 DB DB DB DB DB DB DB3 DB3 DB3 DB3 DB3 DB3 DB4 DB4 DB4 DB4 DB4 DB4 Bank 8 Bank 9 1 Bank 1 DB5 DB5 DB5 DB5 DB5 DB5 DB6 DB6 DB6 DB6 DB6 DB6 Row 55 DB7 DB7 DB7 DB7 DB7 DB7 Row 56 DB DB DB DB DB DB Row 57 DB1 DB1 DB1 DB1 DB1 DB1 Row 58 DB DB DB DB DB DB Row 59 DB3 DB3 DB3 DB3 DB3 DB3 Row 6 DB4 DB4 DB4 DB4 DB4 DB4 Row 61 DB5 DB5 DB5 DB5 DB5 DB5 Row 6 DB6 DB6 DB6 DB6 DB6 DB6 Row 63 DB7 DB7 DB7 DB7 DB7 DB7 Row 64 DB DB DB DB DB DB Row 65 DB1 DB1 DB1 DB1 DB1 DB1 Row 66 DB DB DB DB DB DB Row 67 DB3 DB3 DB3 DB3 DB3 DB3 Row 68 DB4 DB4 DB4 DB4 DB4 DB4 Row 69 DB5 DB5 DB5 DB5 DB5 DB5 Row 7 DB6 DB6 DB6 DB6 DB6 DB6 Row 71 DB7 DB7 DB7 DB7 DB7 DB7 Row 7 DB DB DB DB DB DB Row 73 DB1 DB1 DB1 DB1 DB1 DB1 Row 74 DB DB DB DB DB DB Row 75 DB3 DB3 DB3 DB3 DB3 DB3 Row 76 DB4 DB4 DB4 DB4 DB4 DB4 Row 77 DB5 DB5 DB5 DB5 DB5 DB5 Row 78 DB6 DB6 DB6 DB6 DB6 DB6 Row 79 DB7 DB7 DB7 DB7 DB7 DB7 Row 8 Figure 15: DDRAM description with Mux Mode = 1 and LSB = 1 16 www.emmicroelectronic.com
8.5. DDRAM addressing The x-address and the y-address pointers are used to address RAM cells. They are set by instructions initialization 1 and initialization. As EM616 offers digitally programmable multiplex rates, number of row drivers and number of column drivers are not fixed. As DDRAM is an image of LCD display, address ranges also depend on multiplex rate (Mux Mode): If Mux Mode = : x-address 117 y-address 8 If Mux Mode = 1: x-address 11 y-address 1 Addresses outside these ranges are not allowed. There are three functions that affects the pointers: DEC, V and MX. They are set by instructions initialization 1 and initialization (see Table 4: EM616 instructions). Instruction DEC increment or decrement x-address: If DEC =, x-address increments after each byte written into the RAM. After the last x-address, x-address is reset to and y-address increments. If DEC = 1, x-address decrements after each byte written to the RAM. After x-address=, x-address is set back to the highest x-address for the selected mux mode and y-address increments. DEC allows writing easily to the RAM in two ways, right and left. Instruction V horizontal or vertical mode addressing: If V = (horizontal mode addressing), x-address increments or decrements after each byte written into the RAM. After the last x-address, x-address is reset to or to the highest x-address, and y-address increments. If V = 1 (vertical mode addressing), y-address increments after each byte written to the RAM. After the last y- address, y-address is set back to and x-address increments or decrements. Instruction MX mirrored the DDRAM columns: If MX =, x-address b corresponds to DDRAM column. If MX = 1, x-address b corresponds to DDRAM column 117 or 11. The table below represents the next address selected after pointers are in the last allowed address: Mux DEC Last allowed address Next address Mode x-address y-address x-address y-address 117 8 1 11 1 1 8 117 1 1 1 11 Table 3 The following tables represent the way that the pointers x-address and y-address are working according to the setting of the instructions Mux Mode, V, MX and DEC. 17 www.emmicroelectronic.com
Mux Mode =, V =, DEC =, MX = : 1 3 -- x-address -- -- 114 115 116 117 1 y-address 6 7 8 Pad S33 Pad S15 Mux Mode =, V =, DEC =1, MX = : Figure 16 1 3 -- x-address -- -- 114 115 116 117 1 y-address 6 7 8 Pad S33 Pad S15 Mux Mode = 1, V =, DEC =, MX = : Figure 17 1 3 -- x-address -- -- 98 99 1 11 1 y-address 8 9 1 Pad S41 Pad S14 Mux Mode = 1, V =, DEC =1, MX = : Figure 18 1 3 -- x-address -- -- 98 99 1 11 1 y-address 8 9 1 Pad S41 Pad S14 Figure 19 18 www.emmicroelectronic.com
Mux Mode =, V = 1, DEC =,MX = : 1 3 -- x-address -- -- 114 115 116 117 1 y-address 6 7 8 Pad S33 Pad S15 Mux Mode =, V = 1, DEC =1,MX = : Figure 1 3 -- x-address -- -- 114 115 116 117 1 y-address 6 7 8 Pad S33 Pad S15 Mux Mode = 1, V = 1, DEC =, MX = : Figure 1 1 3 -- x-address -- -- 98 99 1 11 1 y-address 8 9 1 Pad S41 Pad S14 Mux Mode = 1, V = 1, DEC =1, MX = : Figure 1 3 -- x-address -- -- 98 99 1 11 1 y-address 8 9 1 Pad S41 Pad S14 Figure 3 19 www.emmicroelectronic.com
Mux Mode =, V =, DEC =, MX = 1: 117 116 115 114 -- x-address -- -- 3 1 1 y-address 6 7 8 Pad S33 Pad S15 Mux Mode =, V =, DEC =1, MX = 1: Figure 4 117 116 115 114 -- x-address -- -- 3 1 1 y-address 6 7 8 Pad S33 Pad S15 Mux Mode = 1, V =, DEC =, MX = 1: Figure 5 11 1 99 98 -- x-address -- -- 3 1 1 y-address 8 9 1 Pad S41 Pad S14 Mux Mode = 1, V =, DEC =1, MX = 1: Figure 6 11 1 99 98 -- x-address -- -- 3 1 1 y-address 8 9 1 Pad S41 Pad S14 Figure 7 www.emmicroelectronic.com
Mux Mode =, V = 1, DEC =,MX = 1: 117 116 115 114 -- x-address -- -- 3 1 1 y-address 6 7 8 Pad S33 Pad S15 Mux Mode =, V = 1, DEC =1,MX = 1: Figure 8 117 116 115 114 -- x-address -- -- 3 1 1 y-address 6 7 8 Pad S33 Pad S15 Mux Mode = 1, V = 1, DEC =, MX = 1: Figure 9 11 1 99 98 -- x-address -- -- 3 1 1 y-address 8 9 1 Pad S41 Pad S14 Mux Mode = 1, V = 1, DEC =1, MX = 1: Figure 3 11 1 99 98 -- x-address -- -- 3 1 1 y-address 8 9 1 Pad S41 Pad S14 Figure 31 1 www.emmicroelectronic.com
8.6 Initialization of EM616 Data loaded into EM616 can be divided in two parts: The bits stored in the DDRAM, which are corresponding to LCD pixels. The command bits, which are used to set functions of the LCD controller. The way of addressing these bits is described in table below: Control Byte Control Byte Instruction RW CO DC test[] test[1] test[] ini[] ini[1] ini[] DB7 DB6 DB5 DB4 DB3 DB DB1 DB Description Initialization of functions Test Initialization 1 Mux Mode TC [1] TC [] Inv. Row MX Blank Checker Initialization 1 1 1 X[6] X[5] X[4] X[3] X[] X[1] X[] V Initialization 1 1 Y[3] Y[] Y[1] Y[] Initialization 3 1 1 1 Initialization 4 1 1 Vlcd Level [7] Mult [1] Vlcd Level [6] Mult [] Vlcd Level [5] Partial Display Vlcd Level [4] First Row PD [3] Vlcd Level [3] First Row PD [] Vlcd Dischg Vlcd Level [] First Row PD [1] DEC Vlcd Level [1] First Row PD [] Inv. Video LSB Vlcd Level [] Sleep Set functions Set column adress for DDRAM write access and vertical/horizontal addressing Set bank adress for DDRAM write access, increment /decrement pointer and LSB/MSB mode Programming the internally generated LCD voltage supply V LCD Number of voltage multiplier stages Partial display parameters Sleep mode Test 1 1 Byte test, all bits must be set to Test 1 1 1 1 Byte test 1, all bits must be set to Test 1 1 1 Byte test, all bits must be set to Test 3 1 1 1 1 Byte test 3, all bits must be set to Write DDRAM Write 1 byte in DDRAM 1/ 1 DB7 DB6 DB5 DB4 DB3 DB DB1 DB Write data byte to the Display Data Ram Read Status Read 1 byte in initialization 1 - - - - - - - - Mux Mode TC [1] TC [] Inv. Row MX Blank Checker Inv. Video Read Status Byte from EM616 Status Byte = initialization using I C interface Table 4: EM616 instructions Instruction bits from Table 4, active levels and state after reset: Bits 1 State after reset Mux Mode Multiplex rate 65 Multiplex rate 81 TC[1:] Select V LCD Temperature Coefficient b Inv. Row. Normal row drivers Mirrored row drivers MX Normal column drivers Mirrored column drivers Blank Display DDRAM content LCD blanked (all OFF) Checker Display DDRAM content LCD = checker board Inv. Video LCD = DDRAM LCD = NOT (DDRAM) X[6:] x-address pointer. Selects DDRAM columns to be accessed b V Horizontal addressing Vertical addressing Y[3:] y-address pointer. Selects DDRAM bank to be accessed b V LCD Dischg Normal Mode Discharge Capacitor b DEC x-address pointer incremented x-address pointer decrement LSB DB7 copied to the higher row of the selected bank DB copied to the higher row of the selected bank V LCD Level[7:] Program the required LCD supply voltage b Mult[1:] Number of voltage multiplier stages b Partial Display Mux Mode multiplex rate 17 LCD rows active only First RowPD[3:] Position of first active row when partial display mode b Sleep Normal mode Sleep mode: No LCD pixel active, low power consumption Table 5: Internal functions after reset. www.emmicroelectronic.com
8.7 Description of instructions 8.7.1 Initialization 8.7.1.1 Mux Mode Set the multiplex rate. Mux Mode 1 Multiplex rate 65 81 (number of row drivers) Row drivers S S3 S151 S18 S S4 S143 S18 Number of column drivers 118 1 Column drivers S33 S15 S41 S14 Bias system 1/9 1/1 Table 6 The bias system sets the voltages V 1, V, V 3 and V 4 applied to row and column drivers. Assuming these voltages come from a resistive divider, we have: R R VLCD V 1 The value of the corresponding bias system is: V 1 / V LCD = 1/(n+4). The value of the RMS voltage, applied to an LCD pixel ON, divided by the RMS voltage, applied to an LCD pixel OFF, (V ON ) RMS /(V OFF ) RMS, is optimized. This condition leads to: nr V 1 = (n + 4) 1 (1 + MultiplexRate ) R R V 3 V 4 bias systems 1/5 for multiplex rate 17 (partial display mode) bias systems 1/9 for multiplex rate 65 bias systems = 1/1 for multiplex rate 81 8.7.1. TC[1:] These two bits set the V LCD temperature compensation. 4 temperature coefficients are available for the internally generated voltage supply V LCD. One of these coefficients is selected depending on the LCD display needs. The temperature coefficient is proportional to V LCD. VLCD Temperature Coefficients 8.8 TC[1] TC[] V LCD Temperature coefficient (mv/ C) 1 -.39 V LCD 1 -.86 V LCD 1 1-1.34 V LCD Table 7 8.6 8.4 8. 8. 7.8 7.6 7.4 - -1 1 3 4 5 6 7 Temperature [ C] 3 www.emmicroelectronic.com
8.7.1.3 Inv. Row Row driver read direction in the DDRAM can be mirrored to give more flexibility for LCD interconnects. This function acts on the row driver that is activated when a given DDRAM row is read: it becomes active with no need of rewriting the RAM (see Table 8 and Figure 34: LCD output pads configuration in mux 65 depending on Inv. Row and MX). Read data when Inv. Row=: x-address -- -- -- -- -- 1 3 11 or 117 1 y-address 8 or 1 Read data when Inv. Row=1: Figure 3 x-address -- -- -- -- -- 1 3 11 or 117 1 y-address 8 or 1 Figure 33 Inv. Row 1 1 Mux Mode 1 1 S Row Row 64 Row Row 8 S1 Row 1 Row 63 Row 1 Row 79 S3 Row 3 Row 3 Row 3 Row 48 S33 x-addreess = Row 33 Row 47 S34 x-addreess = 1 Row 34 Row 46 S35 x-addreess = Row 35 Row 45 S36 x-addreess = 3 Row 36 Row 44 S37 x-addreess = 4 Row 37 Row 43 S38 x-addreess = 5 Row 38 Row 4 S39 x-addreess = 6 Row 39 Row 41 S4 x-addreess = 7 Row 4 Row 4 S41 to S14 x-addreess = 8 to x-addreess = 19 x-addreess = to x-addreess = 11 S143 x-addreess = 11 Row 8 Row S144 x-addreess = 111 Row 79 Row 1 S145 x-addreess = 11 Row 78 Row S146 x-addreess = 113 Row 77 Row 3 S147 x-addreess = 114 Row 76 Row 4 S148 x-addreess = 115 Row 75 Row 5 S149 x-addreess = 116 Row 74 Row 6 S15 x-addreess = 117 Row 73 Row 7 S151 Row 64 Row Row 7 Row 8 S15 Row 63 Row 1 Row 71 Row 9 S18 Row 33 Row 31 Row 41 Row 39 S183 = S Row Row 64 Row Row 8 Table 8 4 www.emmicroelectronic.com
8.7.1.4 MX Column driver pads can also be mirrored to give more flexibility for LCD interconnects. This function changes the x-address pointer to reverse columns of the DDRAM accessed during a write cycle: a rewrite cycle is required to observe changes on outputs (see Figure 34: LCD output pads configuration in mux 65 depending on Inv. Row and MX) Table 9 shows how the DDRAM is connected to LCD output pads, depending on bits Mux Mode, MX and Inv. Row. MX 1 1 Mux Mode 1 1 S Row Row S3 Row 3 Row 3 S33 x-address = x-address = 117 Row 33 S34 x-address = 1 x-address = 116 Row 34 S35 x-address = x-address = 115 Row 35 S36 x-address = 3 x-address = 114 Row 36 S37 x-address = 4 x-address = 113 Row 37 S38 x-address = 5 x-address = 11 Row 38 S39 x-address = 6 x-address = 111 Row 39 S4 x-address = 7 x-address = 11 Row 4 S41 x-address = 8 x-address = 19 x-address = x-address = 11 S4 x-address = 9 x-address = 18 x-address = 1 x-address = 1 S43 x-address = 1 x-address = 17 x-address = x-address = 99 S44 to S139 x-address =11 to x-address =16 x-address =16 to x-address =11 x-address =3 to x-address = 98 x-address = 98 to x-address = 3 S14 x-address = 17 x-address = 1 x-address = 99 x-address = S141 x-address = 18 x-address = 9 x-address = 1 x-address = 1 S14 x-address = 19 x-address = 8 x-address = 11 x-address = S143 x-address = 11 x-address = 7 S144 x-address = 111 x-address = 6 S145 x-address = 11 x-address = 5 S146 x-address = 113 x-address = 4 S147 x-address = 114 x-address = 3 S148 x-address = 115 x-address = S149 x-address = 116 x-address = 1 S15 x-address = 117 x-address = S151 Row 64 Row 8 Row 79 Row 78 Row 77 Row 76 Row 75 Row 74 Row 73 Row 7 S18 S183 = S Row 33 Row 41 Row Row Table 9: Relation between LCD output pads and row and columns of DDRAM The combination of Mux Mode, Inv. Row and MX gives the following figures (next page) of output pads. 8.7.1.5 Blank Sets all the LCD pixels OFF. Every row driver and column driver is at level. DDRAM content is not affected by this instruction. 8.7.1.6 Checker Sets all the LCD pixels in a checker board pattern, LCD displays alternately ON and OFF pixels. DDRAM content is not affected by this instruction. 8.7.1.7 Inv. Video Sets an inverse video mode. If Inv. Video =, a logical 1 level stored in the DDRAM leads to an ON pixel displayed on the LCD. If Inv. Video = 1, a logical 1 level stored in the DDRAM leads to an OFF pixel displayed on the LCD. DDRAM content is not affected by this instruction. 5 www.emmicroelectronic.com
Row 61 Row 45 Row 6 Row 44 x-addr=117 Row 33 Row Mux Mode = Inv. Row = MX. = Row x-addr = Row 3 Row 1 Row 9 Row 13 Row 35 Row 51 Row 3 Row 19 Row 61 Row 45 Row Row 1 Row 6 Row 44 x-addr=117 x-addr= Row 31 Row 64 Row 33 Row Mux Mode = Mux Mode = Inv. Row = 1 Inv. Row = MX. = MX. = 1 Row 64 Row x-addr = x-addr = 117 Row 34 Row 5 Row 3 Row 1 Figure 34: LCD output pads configuration in mux 65 depending on Inv. Row and MX 6 www.emmicroelectronic.com
Row 51 Row 67 Row 11 Row 7 Row 1 Row 8 Row x-addr=11 Row39 Row 8 Mux Mode = 1 Inv. Row = 1 MX. = x-addr = Row 4 Row 8 x-addr = 11 Row 5 Row 68 Row 9 Row 13 Row 69 Row 53 Row 7 Row 5 Row 8 x-addr= Row41 Row Mux Mode = 1 Inv. Row = MX. = 1 Row 4 Row Row 3 Row 1 Row 9 Row 13 Row 69 Row 53 Row 7 Row 5 Row 8 x-addr=11 Row41 Row Mux Mode = 1 Inv. Row = MX. = x-addr = Row 4 Row Row 3 Row 1 Figure 35: LCD output pads configuration in mux 81 depending on Inv. Row and MX 7 www.emmicroelectronic.com
8.7. Initialization 1 8.7..1 X[6:] These 7 bits set the x-address pointer of the DDRAM. Data are written into column x-address with: X[6] = MSB, X[] = LSB. As the number of column drivers depends on the selected multiplex rate, the DDRAM x-address pointer should also satisfy the following conditions: If Mux Mode = then x-address 11111b. (117). If Mux Mode = 1 then x-address 1111b. (11). 8.7.. V Vertical addressing: If V =, DDRAM x-address pointer is incremented or decremented after each data byte sent. If V = 1, DDRAM y-address pointer is incremented or decremented after each data byte sent. 8.7.3 Initialization 8.7.3.1 Y[3:] These 4 bits set the y-address pointer of the DDRAM. Data are written into bank y-address with Y[3]= MSB, Y[]= LSB. As the multiplex rate is digitally programmable, the DDRAM y-address pointer should also satisfy the following conditions: If Mux Mode = then y-address 1b. If Mux Mode = 1 then y-address 11b. 8.7.3. Vlcd Dischg. The V LCD discharge function can discharge the capacitor connected to PAD V LCD. This operation becomes necessary when changing from Mux 65 or 81 mode to Partial Display Mode. In this case, a lower V LCD is required than the voltage used for Mux 65 or 81 operation, the display at beginning of partial mode operation could be completely ON until V LCD has decreased to its new correct value. To avoid this effect, an internal pull down helps the V LCD voltage to drop down and to reach the new optimum value in a short time. This pull down is active until bit Vlcd Dischg is reset to low level. Typical use of Vlcd Dischg command: Normal mux 65 or mux 81 mode V LCD = 8V Blank = 1 Partial Display = 1 V LCD_Level = Bh (4.5V) V LCD Dischg = 1 V LCD Dischg = Blank = T 3ms, depending on V LCD capacitor Using this command with external power supply on V LCD can damage the IC. 8.7.3.3 DEC DEC controls the DDRAM writing direction: If DEC = then x-address pointer increments after each byte written into the DDRAM. If DEC = 1 then x-address pointer decrements after each byte written into the DDRAM. 8.7.3.4 LSB This instruction changes the bytes send to the DDRAM before writing them. For instance, for bank 1 we have: If LSB = then DB7 is written on Row 1. If LSB = 1 then DB is written on Row 1 (see Figure 14 and Figure 15). 8.7.4 Initialization 3 8.7.4.1 Vlcd Level[7:] This byte sets the internally generated voltage level. These 8 bits generate integer V LCD Level, V LCD Level [7] = MSB, V LCD Level [] = LSB. V LCD is given by the following formula: VLCD = 3. +.35 V LCD _Level 8 www.emmicroelectronic.com
8.7.5 Initialization 4 8.7.5.1 Mult[1:] These two bits set the internal voltage multiplier factor. These bits should be defined depending on the V HV supply voltage level and the current consumption due to LCD load, to have a correct V LCD voltage. If low V LCD is required, for instance when partial display mode is enabled, lower voltage multiplier range should be used, resulting in a current consumption reduction (due to better voltage multiplier efficiency at lower multiplication rate). Mult1 Mult Voltage multiplier 1 3 1 4 1 1 5 Table 1 8.7.5. Partial Display Set the partial display configuration of the driver (multiplex ratio 17). In this configuration, 17 rows are active: The row which corresponds to RAM address. 16 selectable rows, first one is defined by First Row PD [3:]. Partial Display Multiplex rate 65 or 81 (depending on Mux Mode) 1 17 Table 11 8.7.5.3 First Row PD[3:] Partial display mode yields to an LCD with activated banks. Row is always active, it could be used to drive icons. The 16 other active rows are selected from 64 or 8 rows, as shown in following table: Mux Mode or 1 1 First Row PD[3] First Row PD[] First Row PD[1] First Row PD[] First active row (DDRAM) Last active row (DDRAM) Activated banks Row 1 Row 16,1, 1 Row 9 Row 4,,3 1 Row 17 Row 3,3,4 1 1 Row 5 Row 4,4,5 1 Row 33 Row 48,5,6 1 1 Row 41 Row 56,6,7 1 1 Row 49 Row 64,7,8 1 1 1 Row 57 Row 7,8,9 1 Row 65 Row 8,9,1 Table 1 If Mux Mode =, First_Row PD [3:] 11b. If Mux Mode = 1, First_Row PD [3:] 1b. Values for First_Row PD [3:] outside these ranges are not allowed. 8.7.5.4 Sleep This function stops all functionality, internal oscillator and voltage multiplier are off, and LCD is blanked. It yields to a very low current consumption with leakage currents only. 8.7.6 Test to 3 All bits must be set to (see example in typical application page 37). 9 www.emmicroelectronic.com
8.8 LCD outputs The LCD output signals and voltages are optimized for the best LCD contrast and minimum DC component of voltage applied to the LCD display. Table 13 gives bias voltages referring to V LCD. Multiplex Rate V LCD V 1 V V 3 V 4 1 n 1 1 1 n + 1 n + 1 1 n + 1 n + 1 81 (Mux Mode = 1) 1.9.8..1 65 (Mux Mode = ) 1.89.78..11 17 (Partial Display = 1) 1.8.6.4. Table 13: Values of intermediate bias voltages Table 14 gives ratios of V LCD in reference to RMS voltage of an OFF pixel, and the RMS voltage ratios between an ON pixel and an OFF pixel (achievable contrasts). These values correspond to bias voltages described in Table 13. Programmed multiplex rate LCD Bias configuration V OFF VLCD (RMS) V V ON OFF (RMS) (RMS) 81 6 levels = 7.5 n( ( n + 1) n 1) n + 1 = 1.118 n 1 65 6 levels = 6.847 n( ( n + 1) n 1) n + 1 = 1.133 n 1 17 6 levels = 4.16 n( ( n + 1) n 1) n + 1 = 1.81 n 1 The selected LCD display gives the value of Table 14: Required LCD supply voltage and achieved LCD contrast V OFF (RMS) and the value of V VLCD gives the needed V LCD voltage (RMS) supply. The Partial Display mode decreases V LCD, leading to lower power consumption. Lower V LCD decreases consumption because less stages for voltage multiplier can be selected. OFF 3 www.emmicroelectronic.com
8.9 LCD refresh frequency LCD refresh frequency depends on an internal RC oscillator. Pad FR outputs this frequency, multiplied by the multiplex rate. Following figures display typical variations depending on V DD power supply and temperature. FR=f(V DD) @5 C 77 76 75 74 73 1.8.3.8 3.3 3.8 4.3 4.8 VDD LCD refresh frequency depending on temperature 85 83 81 79 77 75 73 71 69 67 65 - -1 1 3 4 5 6 7 Temperature [ C] 8.1 V LCD depending on V HV V LCD (V HV) 8.1 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8. 8.1 8.4.9 3.4 3.9 4.4 4.9 VHV [V ] 31 www.emmicroelectronic.com
8.11 LCD driver waveforms Row and Column Multiplexing Waveform EM616 Mux = 81 VLCD V1 V frame n frame n+1 Row 1 V state1 (t) V state (t) Row 1 V3 V4 VSS VLCD V1 V Row Row V3 V4 VSS VLCD V1 V Col Col V3 V4 VSS Col 1 VLCD V1 V Col 1 V3 V4 VSS VLCD V VSS V state1 (t) = Col1 (t) Row1 (t) VLCD V1 V V V1 V3 V4 V VSS V4 Vstate1 (t) V3 - VLCD VLCD VLCD V VSS V state (t) = Col1 (t) Row (t) VLCD V1 V V V1 V3 V4 V VSS V4 V state (t) V3 - VLCD VLCD 1 3 4 5 6 7 8 8 1 3 4 5 6 7 8 8 3 www.emmicroelectronic.com
Figure 36 33 www.emmicroelectronic.com
Row and Column Multiplexing Waveform EM616 Mux = 65 VLCD V 1 V frame n frame n+1 Row 1 V state1 (t) V state (t) Row 1 V3 V 4 VSS VLCD V1 V Row Row V3 V 4 VLCD V1 V Col 1 Col 1 V3 V 4 Col VLCD V1 V Col V3 V4 VLCD V V state1 (t) = Col1 (t) Row1 (t) V LCD V 1 V V V 1 V 3 V 4 V V 4 V state1 (t) V 3 - V LCD VLCD V LCD V V state (t) = Col (t) Row (t) V LCD V 1 V V V1 V 3 V 4 V VSS V4 V state (t) V 3 - V LCD VLCD 1 3 4 5 6 7 8 64 1 3 4 5 6 7 8 64 Figure 37 34 www.emmicroelectronic.com
8.11.1 Partial Display Row and Column Multiplexing Waveform EM616 Mux = 17 frame n frame n+1 V state1 (t) V state (t) V LCD V 1 Row 1 V Row 1 V 3 V 4 V LCD V 1 Row V V 3 V 4 Row V LCD V 1 Col V V 3 V 4 Col Col 1 V LCD V 1 Col 1 V V 3 V 4 V LCD V state1 (t) V V LCD V 1 V V 3 V 4 V V state1 (t) = Col1 (t) Row1 (t) V V 1 V 4 V 3 - V LCD V LCD V LCD V state (t) V V LCD V 1 V V 3 V 4 V V state (t) = Col1 (t) Row (t) V V 1 V 4 V 3 - V LCD V LCD 1 3 4 5 6 7 8 9 1 11 1 13 14 15 16 1 3 4 5 6 7 8 9 1 11 1 13 14 15 16 35 www.emmicroelectronic.com
Figure 38 36 www.emmicroelectronic.com
9 Typical Application 9.1 Power supply connection SDA SCL V DD SDA SCL V DD V LCD V LCD V LCD V LCD 1μF V LCD test fr reset CS I 1μF V LCD test fr reset CS I EM616 EM616 1μF 1μF V DD V DD V DD V DD V DD V DD V DD V DD V DD V DD 1μF V PP V PP V HV V HV V HV V HV V HV V HV V HV V HV V HV Typical Application using two separate power supplies Typical Application using a single power supply Figure 39: Power Supply connection 9. Connection and communication with the display This example gives typical programming steps for EM616 with I C interface, for serial interface, start and stop conditions should be replaced by CS at L and CS at 1L. LCD display is connected as described on Figure 4: Example Liquid Crystal Display 81 row x 1 columns 41 rows 1 columns 4 rows Row 3 Row 4 Col Col 11 Row 8 Row7 Row 9 Row 69 EM616 Row 13 Row 53 Row 1 Row 1 Row Row Row 41 Row 5 Figure 4: Connection between EM616 and LCD for the application example 37 www.emmicroelectronic.com
Step DB7 DB6 DB5 DB4 DB3 DB DB1 DB Comment Display 1 Power on Undefined Reset A reset cycle must always follow the power on Blank 3 IC start condition Blank 4 x x x x x x x EM616 slave address + write mode Blank 5 1 Control byte for initialization Blank 6 1 1 Data byte = initialization Multiplex Rate = 81 Vlcd Temperature Coefficient = -.39 x Vlcd (mv/ C) Blank No row or column mirroring No blank, Checker or Video functions. 7 1 1 1 Control byte for initialization 3 Blank 8 1 1 1 1 Data byte = initialization 3 Programmed Vlcd_level = 1111b (8Eh=14) Blank Vlcd = 3. + 14*.35 = 8.V 9 1 1 Control byte for initialization 4 Blank 1 1 1 Data byte = initialization 4 x 5 Voltage Multiplier Undefined No partial display mode. No sleep mode 11 1 1 Control byte for test 1 bits test must be set to L 13 1 1 1 Control byte for test 1 14 bits test must be set to L 15 1 1 1 Control byte for test Undefined 16 bits test must be set to L 17 1 1 1 1 Control byte for test 3 18 bits test must be set to L 38 www.emmicroelectronic.com
Step DB7 DB6 DB5 DB4 DB3 DB DB1 DB Comment 19 1 Last control byte DDRAM write selected Fisrt DDRAM byte stored at x-address =, y-address = Horizontal addressing is selected (state after reset) Display Undefined x x x x x x x Only DB7 is stored at row of DDRAM, column 1 to 11 x x x x x x x Only DB7 is stored at row, columns 1 to 11 1 DB7 to DB are stored at column, rows 1 to 8 13 1 1 1 1 1 1 1 DB7 to DB are stored at column 1, rows 1 to 8 14 1 1 1 DB7 to DB are stored at column, rows 1 to 8 15 1 1 1 DB7 to DB are stored at column 3, rows 1 to 8 39 www.emmicroelectronic.com
Step DB7 DB6 DB5 DB4 DB3 DB DB1 DB Comment 16 1 1 DB7 to DB are stored at column 4, rows 1 to 8 Display 17 to 9 DB7 to DB are stored at column 5 to 11, rows 1 to 8 column to 5, rows 9 to 16 3 31 1 1 1 1 1 1 1 3 1 33 1 34 1 35 1 1 1 1 1 1 1 36 to 35 Write letter M DB7 to DB are stored at column 1 to 11, rows 9 to 16 36 IC stop condition + new start condition 37 x x x x x x x EM616 slave address + write mode 38 1 1 Control byte for initialization 1 39 1 1 x-address = 1, Horizontal mode addressing 33 1 1 Control byte for initialization 331 1 y-address = 1 33 1 DDRAM write selected 333 Write 6 334 1 1 1 1 1 335 1 1 1 336 1 1 1 337 1 1 1 338 1 1 1 339 x x x x x x x x Continuation Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged 4 www.emmicroelectronic.com
Step DB7 DB6 DB5 DB4 DB3 DB DB1 DB Comment 1 IC start condition x x x x x x x EM616 slave address + write mode 3 1 Control byte for initialization 4 1 1 1 Blank = 1 5 1 1 1 Control byte for initialization 3 6 1 1 1 1 Vlcd_level = Bh 7 1 1 Control byte for initialization 8 1 Vlcd_Dischg = 1 9 1 1 Control byte for initialization 4 1 1 1 1 Partial display on banks:, 1 and Wait 3 ms 11 1 1 Control byte for initialization 3 1 Vlcd_Dischg = 13 1 Control byte for initialization 14 1 1 Blank = Partial display on banks:, 1 and Display Previously set Unchanged Unchanged All pixels OFF All pixels OFF All pixels OFF All pixels OFF All pixels OFF All pixels OFF All pixels OFF All pixels OFF All pixels OFF All pixels OFF 15 1 1 Control byte for initialization 4 16 1 1 1 1 Partial display on banks:, and 3 Remark: This typical application example shows an LCD display ON before the DDRAM is completely written, parts of the LCD are undefined as DDRAM data is undefined at power on. To avoid this effect, blank function can remain active until DDRAM is completed to avoid randomly ON or OFF pixels to appear on the LCD display. 41 www.emmicroelectronic.com
9.3 Power ON recommended flow Power ON RESET MODIFIED CUSTOMER INITIALISATION (as defined table4 page 3 of datasheet) initialisation (16bits) initialisation 1 (16bits) initialisation (16bits) initialisation 3 (16bits) initialisation 4 (16bits) >> 11 xxxxxxx (sleep function disable) test (16bits) >> 11 1 test 1 (16bits) test (16bits) test 3 (16bits) DELAY (15ms) STANDARD CUSTOMER INITIALISATION (as defined table4 page 3 of datasheet) initialisation (16bits) initialisation 1 (16bits) initialisation (16bits) initialisation 3 (16bits) initialisation 4 (16bits) test (16bits) >> 11 test 1 (16bits) test (16bits) test 3 (16bits) DATA (as defined in datasheet) 4 www.emmicroelectronic.com