ow SolarFlare Communications roke the 10Gbps on UP arrier SolarFlare Communications eadquarters: rvine, CA Product Focus: 10Gbps UP Ethernet chip set Fabless business model with foundry CMOS process Key P: SP algorithm deriving its roots from NASA deep space communications echnology first demonstrated in March 2004 9/4/2004 2 1
9/4/2004 3 Why UP? t s not just about running on installed cable Optical Fiber and Modules erminations are very expensive and require skilled labor to install Optical modules necessarily involve the mechanical assembly of many technologies: VCSELs, PN diodes, laser drivers, trasimpedance amps and Seres chips. Optical modules are, by construction, one per port Optical modules are designed to operate at only one data rate and only purchased in applications where that data rate is needed UP and 10GASE- Ps J45 is cheap, plastic, installed in field by any manager UP Ps are implemented in vanilla CMOS and are on a roadmap to single chip integration lower COGs by construction UP Ps are capable of multiport-on -a-chip implementations as lithography progresses dramatically lowering price per port UP Ps are rate adaptive making them attractive for PC LOM adoption where they are sold as future proofing 9/4/2004 4 2
What s s wrong with CX-4? Short reach Standardized to 15m; Some solutions up to 30m he problem: Sweet Spot of ata Center applications is between 40m and 70m ecause of patch panel connections Expensive Cabling $200 for 15m link with connectors (compare to $15 for same link on Cat6) hick cumbersome cable and large connectors Can not be terminated in the field 15m CX-4: $200 15m Cat6: $15 Source: computercablestore.com 9/4/2004 5 echnology ehind Ethernet Evolution Speed Canceling noise allows data to be transmitted faster Perceived Channel Capacity Conventional Wisdom Channel Capacity 1000ASE- New model Channel Capacity 10GASE- Perceived Channel Capacity 10ASE- 100ASE- ransitions require new technology allowing to emerge Analog Linear nter-symbol nterference Near-End Crosstalk And Echo Far-End Crosstalk ime 9/4/2004 6 3
Why is 10G on UP so difficult? Very small receive signals swamped by Many sources of noise: Far-End Echo Near Echo Alien Crosstalk, EM Far Echo Near-End Crosstalk (NEX) Far-End Crosstalk (FEX) nter-symbol interference (S) Electromagnetic nterference (EM) FEX12 NEX12 NEX13 FEX13 FEX14 NEX14 9/4/2004 7 esign Philosophy Evolutionary build on 1000ASE- evolutionary complexity/ performance enhancers Need to enhance treatment of media impairments NEX mitigation (less noise) FEX mitigation (less noise) EM friendly/ Spectral efficiency (more bits/ baud) est complexity / performance tradeoff while being Standards compatible Solarflare Communications nc. 9/4/2004 8 4
Comparison w/ 1000ASE- 1000-ASE- Multilevel coded PAM signaling (2-bits/ symbol) 5-level with trellis code across pairs Full duplex echo-cancelled transmission 125 Mbaud, ~ 80 Mz used bandwidth Moderate NEX cancellation No specified FEX cancellation 10GbE Solution [ UP] Multilevel coded PAM signaling (3-bits/ symbol) 10-level with trellis code across pairs Full duplex echo-cancelled transmission 833 Mbaud, ~ 400 Mz used bandwidth igh-performance NEX cancellation igh-performance FEX cancellation 9/4/2004 9 Measured adiated Emissions Electric field (duv/m) 80 70 60 50 40 30 100 meter channel 50 meter span Cat 5e FCC Class A limit 20 10 0 0 2 4 6 8 10 Frequency (z) x 10 8 9/4/2004 10 5
Chipset lock iagram Cat 5 Cable J -45 Connector Magnetics Line river LNA/ ybrid x x AC AC Ex x AC AC x AC PMA_x Pulse Shaper PMA_x Equalizer r Echo/ NEX/ FEX Canceller r PCS_x Scrambler Forward ECC Modulation PCS_x escrambler ECC ecode emodulation XGM nterface x xc xclk x xc xclk Antialiasing Filter PGA PLL Clock Generation Module Control Status Control Status Control Control MO MO MO nterface Processor egisters nterface MC AFE ias Generator ALU LE rivers SP eceive Elements ransmit Elements Control Elements ias Voltage LEs & Port Address Passive Elements 9/4/2004 11 Noise Cancellation eceive Signal Echo Cancelled NEX Cancelled FEX Cancelled S emoval Error Correction 9/4/2004 12 6
SolarFlare P Platform Key ntellectual Property Multilevel Coded Modulation Adaptive Line Equalization New Echo and NEX mitigation architecture Combined FEX and equalization circuits nterwoven A/ and SP architecture Solarflare Uniqueness etter bandwidth utilization Much higher performance 7x circuit area reduction for function 6x circuit area reduction for function igital implementation of traditionally analog circuit attributes mpact on esign Enhanced tolerance to cable variability Mitigates S Fabrication feasibility Economic circuit realization Enable utilization of CMOS A/ 9/4/2004 13 Chipset etails SP: 0.13u CMOS 25 x 25 mm 575 pin GA package 5.4 million gates + 2 Mbits memory AFE: 0.18u CMOS 23 X 23 mm 473 pin GA package 2.76 million transistors (0.7 million eq. Gates) 9/4/2004 14 7
AFE ighlights ntegrates: Four 10-bit, 1Gsps analog-to-digital converters Programmable gain amplifiers PLL clock multiplication and distribution circuits 0.18u CMOS technology Low risk, low cost 2.7 Million ransistors 9/4/2004 15 AFE lock iagram XAL or External 25 Mz Clock Opt. External 1.67 Gz est Clock 833.3 Mz LVS "low jitter" Power-On PO eset pulse XAL OSC 25 Mz PLL 1.67 Gz VCO CLK uffer Autoneg etect igital Logic igital Controls Phase Control LNA OU from each channel Serial nterface from SP iming ecovery from SP Phase Adjustors igital Controls Phase Control igital Controls GAL CONOLS clocks w/baud timing adjustments igital Controls GAL CONOLS Channel A N PGA & AC GAL OU AS Channel C PGA & N AC GAL AS OU igital Controls PGA/S G PGA/S G igital Controls GAL CONOLS AS AS GAL CONOLS Channel N PGA & AC GAL OU Channel PGA & N AC GAL OU igital Controls estmux 4 Channels of 10 -bit LVS data plus 4 LVS clocks 9/4/2004 16 8
AFE ie Layout AC PGA PO Phase Adjustors PLL XL OSC 9/4/2004 17 Key Challenges and Mitigation Strategies igh input bandwidth (500Mz) needs Custom sampling circuit with very short sampling aperture and high bandwidth PGA front end. Low jitter and low skew clock distribution Self adjusting PLL based closed- loop architecture Low front -end noise and high linearity requirements Careful partitioning of gain elements in signal path Channel to channel noise coupling edicated power and ground systems per channel solation guard rings and on-chip shielding structures Extensive packaging/ substrate modeling Flip -chip packaging for bond- wire inductance elimination 9/4/2004 18 9
EEE Standard imeline Source: EEE P802.3an agenda_1_0504. pdf 9/4/2004 19 10