Lecture 23 Design for Testability (DFT): Full-Scan (chapter14)

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Lecture 23 Design for Testability (DFT): Full-Scan (chapter14) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system Summary Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 1

Definition Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan DFT method for mixed-signal circuits: Analog test bus Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 2

Ad-Hoc DFT Methods Good design practices learnt through experience are used as guidelines: Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. Consider ATE requirements (tristates, etc.) Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods: Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 3

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 4

Observation Point Insertion Control Point Insertion TM=0 Normal operation TM=1 CONTROL OPERATION Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 5

Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 6

Scan Design Rules Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 7

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 8

Correcing a Rule Violation CK All clocks must be controlled from PIs. Comb. logic D2 D1 FF Q Comb. logic Q* = DC + C Q Q * = D 1 D 2 C k + (D 2 C k ) Q = D 1 D 2 C k + D 2 Q +C k Q Comb. logic D2 D1 CK FF Q Comb. logic Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 9

Fixing BUS Conection Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 10

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 11

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 12

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 13

Scan Flip-Flop (SFF) D Master latch Slave latch TC Logic overhead Q SD MUX Q CK D flip-flop CK Master open Slave open t TC Normal mode, D selected Scan mode, SD selected t Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 14

Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF) Master latch Slave latch D Q MCK Q SCK D flip-flop SD TCK Logic overhead MCK TCK SCK MCK TCK Normal mode t Scan mode SCK t Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 15

Adding Scan Structure PI PO Combinational SFF SCANOUT logic SFF SFF TC or TCK SCANIN Not shown: CK or MCK/SCK feed all SFFs. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 16

Comb. Test Vectors PI I2 I1 O1 O2 PO SCANIN TC Combinational logic SCANOUT Presen t state S1 S2 N1 N2 Next state Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 17

Comb. Test Vectors PI I1 I2 Don t care or random bits SCANIN S1 S2 TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 PO O1 O2 SCANOUT N1 N2 Sequence length = (nsff + 1) ncomb + nsff + 4 + nsff clock periods = (ncomb + 2) nsff + ncomb + 4 clock perod n comb = number of combinational vectors n sff = number of scan flip-flops Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 18

Testing Scan Register Scan register must be tested prior to application of scan test sequences. A shift sequence 00110011... of length n sff +4 in scan mode (TC=0) produces 0 0, 0 1, 1 1 and 1 0 transitions in all flip-flops and observes the result at SCANOUToutput. Total scan test length: (n comb + 2) n sff + 4 + ncomb clock periods. Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 10 6 clocks. Multiple scan registers reduce test length. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 19

A modulo-3 circuit Three with outputs scan,z, Q1, design Q2 and test generation ( Exm.14.1) Non Scan circuit [ 72] has 42 Faults ;34 test vectors detect 36 out of 42 Faults ATPG Program produces 12 Test vectors for Combinational part, with 4 inputs C,R,P1,P2 and Scan Circuit : test sequence = (12+2)2+4+12 =44 Fault simulation shows: all faults are detected including 6 undetectable faults in original circuit and Those in multiplexers Normal INPUTS R and C OUTPUT R =1 Q1Q2 = 00 C=1, R=0 00 01 10 00 Z 0 0 1 0 C=R=0 Q 1+ = Q 1, Q 2+ =Q 2 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 20

Multiple Scan Registers Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. Test sequence length is determined by the longest scan shift register. Just one test control (TC) pin is essential. PI/SCANIN Combinational logic SFF M U X PO/ SCANOUT SFF SFF TC CK Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 21

Scan Overheads IO pins: One pin necessary. Area overhead: Gate overhead = [4 n sff /(n g )] x 100%, where n g = comb. gates; n ff = flip-flops; Example n g = 100k gates, n ff = 2k flip-flops, overhead = 8%. More accurate estimate must consider scan wiring and layout area. Performance overhead: Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fan-out; approx. 5-6%. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 22

Hierarchical Scan Scan flip-flops are chained within subnetworks before chaining subnetworks. Advantages: Automatic scan insertion in netlist Circuit hierarchy preserved helps in debugging and design changes Disadvantage: Non-optimum chip layout. Scanin SFF1 SFF4 Scanout Scanin SFF1 SFF3 Scanout SFF2 SFF3 SFF4 SFF2 Hierarchical netlist Flat layout Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 23

Optimum Scan Layout X X IO pad SFF cell Flipflop cell Y Y SCANIN TC SCAN OUT Routing channels Interconnects Active areas: XY and X Y Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 24

Scan Area Overhead Linear dimensions of active area: X = (C + S) / r X = (C + S + S) / r Y = Y + ry = Y + Y(1-- ) / T Area overhead X Y --XY = -------------- x 100% XY 1-- = [(1+ s)(1+ -------) 1] x 100% T 1-- = ( s + ------- ) x 100% T y = track dimension, wire width+separation C = total comb. cell width S = total non-scan FF cell width s = fractional FF cell area = S/(C+S) = SFF cell width fractional increase r = number of cell rows or routing channels = routing fraction in active area T = cell height in track dimension y Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 25

Example: Scan Layout 2,000-gate CMOS chip Fractional area under flip-flop cells, s = 0.478 Scan flip-flop (SFF) cell width increase, = 0.25 Routing area fraction, = 0.471 Cell height in routing tracks, T = 10 Calculated overhead = 17.24% Actual measured data: Scan implementation Area overhead Normalized clock rate None 0.0 1.00 Hierarchical 16.93% 0.87 Optimum layout 11.90% 0.91 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 26

ATPG Example: S5378 Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II, 200MHz processor Number of ATPG vectors Scan sequence length Original 2,781 179 0 0.0% 4,603 35/49 70.0% 70.9% 5,533 s 414 414 Full-scan 2,781 0 179 15.66% 4,603 214/228 99.1% 100.0% 5 s 585 105,662 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 27

Automated Scan Design Rule violations Combinational vectors Scan design rule audits Combinational ATPG Scan sequence and test program generation Behavior, RTL, and logic Design and verification Gate-level netlist Scan chain order Scan hardware insertion Scan netlist Chip layout: Scanchain optimization, timing verification Test program Design and test data for manufacturing Mask data Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 28

Timing and Power Small delays in scan path and clock skew can cause race condition. Large delays in scan path require slower scan clock. Dynamic multiplexers: Skew between Ck and TC signals can cause momentary shorting of D and SD inputs. Random signal activity in combinational circuit during scan can cause excessive power dissipation. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 29

Summary Scan is the most popular DFT technique: Rule-based design Automated DFT hardware insertion Combinational ATPG Advantages: Design automation High fault coverage; helpful in diagnosis Hierarchical scan-testable modules are easily combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overheads Disadvantages: Large test data volume and long test time Basically a slow speed (DC) test Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 30

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