Introduction to Serial I/O CS/ECE 6780/5780 Al Davis Serial I/O Today s topics: general concepts in preparation for Lab 8 1 CS 5780 2 CS 5780 A Serial Channel Definitions 3 CS 5780 4 CS 5780 Page 1
Bandwidth More Basics Classic UART: DTE & DCE communications UART is the port» for Freescale this is SCI (serial communications interface) this is just one instance as usual signaling levels are TTL interface logic can be used to convert to RS232 levels e.g. MAX232, MC145407 chips» parity is generated by Tx side and checked by Rx side 5 CS 5780 6 CS 5780 Half Duplex Signalling Other Issues Half Duplex normal usage» fixed Tx and Rx side a.k.a. Simplex signalling expanded version» send can come from either side but only in one direction at a time» problem = collisions solution same as with Ethernet CDMA transmit & receive + compare if Tx & Rx values aren t the same then collision & retry Full Duplex more wires but 2 independent communication channels» concurrent send and receive buffers Timing send and receive baud rates must be the same Asynchronous (e.g. SCI) separate send and receive clocks» start sequence is used to synch clocks for the frame model is that drift won t be enough to cause errors intra-frame in high speed signaling (e.g. HT, QPI, etc.) this is a big problem and requires complex and energy hungry circuitry long transmission paths also require significant pre- and post-emphasis circuits Synchronous: multiple options common clock (e.g. SPI) Tx side clock source synchronous signaling 7 CS 5780 8 CS 5780 Page 2
SCI & SPI Illustrated Protocols & Specifications There are many Each one has specifications electrical» what voltage levels mean what logical value» current sink and source requirements cables» often limited to some max length mechanical» what does the connector look like & pin function 9 CS 5780 10 CS 5780 2 Common Freescale Options RS232 Output Specifications Simple SCI SCI to RS232 conversion 11 CS 5780 12 CS 5780 Page 3
RS232 DB9 Pin Assignments A Simple Serial Network 13 CS 5780 14 CS 5780 RS422/RS423/RS485 Specifications Universal Serial Bus (USB) 15 CS 5780 16 CS 5780 Page 4
Optical SCI Channel SCI Where & Why would you want to do this? 17 CS 5780 18 CS 5780 Transmitting in Asynchronous Mode Control Bits for the Transmitter NOTE: Tx Data Reg Empty (TDRE) flag signals that the SCDR register is empty, TDRE is cleared by reading it. Different from previous flag clearing methods where you had to write a 1 to the flag. Read of TC flag (transmit complete) similarly clears it Then write to the SCDR 19 CS 5780 20 CS 5780 Page 5
Transmission Illustrated Pseudo Code for Transmission Process 21 CS 5780 22 CS 5780 Receiving in Asynchronous Mode Control Bits for the Receiver 23 CS 5780 24 CS 5780 Page 6
Status Bits Generated by the Receiver Receiving Illustrated 25 CS 5780 26 CS 5780 Pseudo Code for Receive Process 9S12C32 SCI Details 27 CS 5780 28 CS 5780 Page 7
More SCI Details SCI I/O Interrupts 29 CS 5780 30 CS 5780 SCI Rx, Tx, & ISR s SCI Interface Ritual TxFifo full wait until there is space RxFifo full data was lost due to Rx buffer over run 31 CS 5780 32 CS 5780 Page 8
SCI Interface ISR SCI In/Out Character 33 CS 5780 34 CS 5780 Serial Port Printer Interfaces SCI Simplex Printer Interface (w/ DTR handshake) Note: 2 approaches DTR is a handshake saying send me another frame Xoff is a shut up signal more efficient for larger buffers but some timing complexity for on the fly & response time issues 35 CS 5780 36 CS 5780 Page 9
Serial Output w/ DTR DTR Handshake ISR 37 CS 5780 38 CS 5780 Serial Output to Printer Using XON/XOFF (busy waiting) 39 CS 5780 40 CS 5780 Page 10
Synchronous = SPI (3 options) SPI Master/Slave Example 41 CS 5780 42 CS 5780 SPI Fundamentals More SPI Fundamentals Mode fault occurs when master and slave synchronization is wrong e.g. 2 masters 43 CS 5780 44 CS 5780 Page 11
SPI Pseudo Code SPI Modes CPOL sets SCLK polarity e.g. what is IDLE CPHA sets even or odd clock edges for the receiver shift register 45 CS 5780 46 CS 5780 9S12C32 SPI Details (Port M) SPI Control Registers SPIBR register 47 CS 5780 48 CS 5780 Page 12
SPI Modes SPI Mode Selections 49 CS 5780 50 CS 5780 Concluding Remarks Serial I/O is very common USB is obviously everywhere SPI & SCI are more prevalent in embedded systems» primarily because it s low cost» most controllers support this your kits support both» difference is synch vs. asynch Too much detail already but advise that you take a look at the DAC application we ll go through the full SCI ritual next lecture» in prep for Lab 8 SPRING BREAK hope you have some fun hope I can catch up 51 CS 5780 Page 13