SiI9127A/SiI1127A HDMI Receiver with Deep Color Output

SiI9127A/SiI1127A HDMI Receiver wih Deep Color Oupu SiI-DS-1059-D May 2017

Conens Acronyms in This Documen... 6 1. General Descripion... 7 Inpus... 7 Digial Video Oupu... 7 Digial Audio Inerface... 8 Consumer Elecronic Conrol... 8 Sysem Applicaions... 8 Package... 8 2. Produc Family... 9 3. Funcional Descripion... 10 TMDS Digial Cores... 10 Acive Por Deecion and Selecion... 10 HDCP Decrypion Engine/XOR Mask... 11 HDCP Embedded Keys... 12 Daa Inpu and Conversion... 12 Mode Conrol Logic... 12 Video Daa Conversion and Video Oupu... 12 Deep Color Suppor... 13 xvycc... 13 3D Video Formas... 13 Auomaic Video Configuraion... 15 Audio Daa Oupu Logic... 15 S/PDIF... 15 I 2 S... 15 Conrol and Configuraion... 16 Regiser/Configuraion Logic... 16 I 2 C Serial Pors... 16 EDID FLASH and RAM Block... 17 CEC Inerface... 17 Sandby and HDMI Por Power Supplies... 17 4. Elecrical Specificaions... 19 Absolue Maximum Condiions... 19 Normal Operaing Condiions... 20 DC Specificaions... 21 Digial I/O Specificaions... 21 DC Power Supply Pin Specificaions... 22 AC Specificaions... 24 Video Oupu Timings... 24 Audio Oupu Timings... 25 Miscellaneous Timings... 26 Inerrup Timings... 26 5. Timing Diagrams... 28 TMDS Inpu Timing Diagrams... 28 Power Supply Conrol Timings... 28 Power Supply Sequencing... 28 Rese Timings... 29 Digial Video Oupu Timing Diagrams... 29 Oupu Transiion Times... 29 Oupu Clock o Oupu Daa Delay... 30 Digial Audio Oupu Timings... 30 Calculaing Seup and Hold Times for Video Bus... 32 24/30/36-Bi Mode... 32 2 SiI-DS-1059-D

12/15/18-Bi Dual-Edge Mode... 33 Calculaing Seup and Hold Times for I 2 S Audio Bus... 34 6. Pin Diagram and Descripions... 35 Pin Diagram... 35 Pin Descripions... 36 Digial Video Oupu Daa Pins... 36 Digial Video Oupu Conrol Pins... 37 Digial Audio Oupu Pins... 37 Configuraion/Programming Pins... 38 HDMI Conrol Signal Pins... 38 TMDS Differenial Signal Pins... 39 Power and Ground Pins... 39 Reserved and No Conneced Pins... 39 7. Video Pah... 40 HDMI Inpu Modes o SiI9127A/SiI1127A Oupu Modes... 41 HDMI RGB 4:4:4 Inpu Processing... 41 HDMI YCbCr/xvYCC 4:4:4 Inpu Processing... 42 HDMI YCbCr/xvYCC 4:2:2 Inpu Processing... 43 SiI9127A/SiI1127A Oupu Mode Configuraion... 44 RGB and YCbCr 4:4:4 Formas wih Separae Syncs... 45 YC 4:2:2 Formas wih Separae Syncs... 47 YC 4:2:2 Formas wih Embedded Syncs... 50 YC Mux (4:2:2) Formas wih Separae Syncs... 53 YC Mux 4:2:2 Formas wih Embedded Syncs... 55 12/15/18-Bi RGB and YCbCr 4:4:4 Formas wih Separae Syncs... 57 8. I 2 C Inerfaces... 59 HDCP E-DDC / I 2 C Inerface... 59 Local I 2 C Inerface... 60 Video Requiremen for I 2 C Access... 60 I 2 C Regisers... 60 9. Design Recommendaions... 61 Power Conrol... 61 Power-on Sequencing... 61 Power Pin Curren Demands... 61 HDMI Receiver DDC Bus Proecion... 62 Decoupling Capaciors... 62 ESD Proecion... 62 HDMI Receiver Layou... 63 EMI Consideraions... 64 Typical Circui... 65 Power Supply Decoupling... 65 HDMI Por Connecions... 66 Digial Video Oupu Connecions... 67 Digial Audio Oupu Connecions... 68 Conrol Signal Connecions... 69 Layou... 70 TMDS Inpu Por Connecions... 70 10. Package Informaion... 71 epad Requiremens... 71 PCB Layou Guidelines... 71 Package Dimensions... 72 Marking Specificaion... 73 Ordering Informaion... 73 References... 74 SiI-DS-1059-D 3

Sandards Documens... 74 Sandards Groups... 74 Laice Semiconducor Documens... 74 Technical Suppor... 74 Revision Hisory... 75 Figures Figure 1.1. Digial Television Sysem Diagram... 7 Figure 3.1. Digial Television Receiver Block Diagram... 10 Figure 3.2. Funcional Block Diagram... 11 Figure 3.3. Defaul Video Processing Pah... 14 Figure 3.4. I 2 C Regiser Domains... 16 Figure 3.5. Power Island... 18 Figure 4.1. Tes Poin VCCTP for VCC Noise Tolerance Specificaion... 20 Figure 4.2. Audio Crysal Schemaic... 25 Figure 4.3. SCDT and CKDT Timing from DE or RXC Inacive/Acive... 27 Figure 5.1. TMDS Channel-o-Channel Skew Timing... 28 Figure 5.2. Power Supply Sequencing... 28 Figure 5.3. RESET# Minimum Timings... 29 Figure 5.4. Video Digial Oupu Transiion Times... 29 Figure 5.5. Receiver Clock-o-Oupu Delay and Duy Cycle Limis... 30 Figure 5.6. I 2 S Oupu Timings... 30 Figure 5.7. S/PDIF Oupu Timings... 31 Figure 5.8. MCLK Timings... 31 Figure 5.9. 24/30/36-Bi Mode Receiver Oupu Seup and Hold Times... 32 Figure 5.10. 12/15/18-Bi Mode Receiver Oupu Seup and Hold Times... 33 Figure 6.1. Pin Diagram... 35 Figure 7.1. Receiver Video and Audio Daa Processing Pahs... 40 Figure 7.2. HDMI RGB 4:4:4 Inpu o Video Oupu Transformaions... 41 Figure 7.3. HDMI YCbCr/xvYCC 4:4:4 Inpu o Video Oupu Transformaions... 42 Figure 7.4. HDMI YCbCr/xvYCC 4:2:2 Inpu o Video Oupu Transformaions... 43 Figure 7.5. 4:4:4 Timing Diagram... 46 Figure 7.6. YC Timing Diagram... 49 Figure 7.7. YC 4:2:2 Embedded Sync Timing Diagram... 52 Figure 7.8. YC Mux 4:2:2 Timing Diagram... 54 Figure 7.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram... 56 Figure 7.10. 18-Bi Oupu 4:4:4 Timing Diagram... 57 Figure 7.11. 15-Bi Oupu 4:4:4 Timing Diagram... 58 Figure 7.12. 12-Bi Oupu 4:4:4 Timing Diagram... 58 Figure 8.1. I 2 C Bye Read... 59 Figure 8.2. I 2 C Bye Wrie... 59 Figure 8.3. Shor Read Sequence... 59 Figure 9.1. Decoupling and Bypass Capacior Placemen... 62 Figure 9.2. Cu-ou Reference Plane Dimensions... 63 Figure 9.3. HDMI o Receiver Rouing Top View... 64 Figure 9.4. Power Supply Decoupling and PLL Filering Schemaic... 65 Figure 9.5. HDMI Por Connecions Schemaic... 66 Figure 9.6. Digial Display Schemaic... 67 Figure 9.7. Audio Oupu Schemaic... 68 Figure 9.8. Conroller Connecions Schemaic... 69 Figure 9.9. TMDS Inpu Signal Assignmens... 70 Figure 10.1. 128-Pin TQFP Package Diagram... 72 Figure 10.2. Marking Diagram of SiI9127A... 73 Figure 10.3. Alernae Marking Diagram... 73 4 SiI-DS-1059-D

Tables Table 2.1. Summary of New Feaures... 9 Table 3.1. Digial Video Oupu Formas... 12 Table 3.2. Suppored 3D Video Formas... 14 Table 3.3. Defaul Video Processing... 14 Table 3.4. AVI InfoFrame Video Pah Deails... 15 Table 3.5. Digial Oupu Formas Configurable hrough Auo Oupu Forma Regiser... 15 Table 3.6. Suppored MCLK Frequencies... 16 Table 5.1. Calculaion of 24/30/36-Bi Oupu Seup and Hold Times... 32 Table 5.2. Calculaion of 12/15/18-Bi Oupu Seup and Hold Times... 33 Table 5.3. I 2 S Seup and Hold Time Calculaions... 34 Table 7.1. Translaing HDMI Formas o Oupu Formas... 41 Table 7.2. Oupu Video Formas... 44 Table 7.3. 4:4:4 Mappings... 45 Table 7.4. YC 4:2:2 Separae Sync Pin Mappings... 47 Table 7.5. YC 4:2:2 (Pass Through Only) Separae Sync Pin Mapping... 48 Table 7.6. YC 4:2:2 Embedded Sync Pin Mappings... 50 Table 7.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping... 51 Table 7.8. YC Mux 4:2:2 Mappings... 53 Table 7.9. YC Mux 4:2:2 Embedded Sync Pin Mapping... 55 Table 7.10. 12/15/18-Bi Oupu 4:4:4 Mappings... 57 Table 8.1. Conrol of he Defaul I 2 C Addresses wih he CI2CA Pin... 60 Table 9.1. Maximum Power Domain Currens versus Video Mode... 61 SiI-DS-1059-D 5

Acronyms in This Documen A lis of acronyms used in his documen. Acronym Definiion ACR AVI CBUS CEC CPI CPU CSC DDC DSC DSD DTV EDDC EDID ESD GPIO HDCP HDMI HPD I 2 C I 2 S KSV NVM PCM S/PDIF TMDS TQFP Audio Clock Regeneraion Auxiliary Video Informaion Conrol Bus Consumer Elecronics Conrol CEC Programming Inerface Cenral Processing Uni Color Space Converer Display Daa Channel Display Sream Compression Direc-Sream Digial Digial Television Enhanced Display Daa Channel Exended Display Idenificaion Daa Elecrosaic Discharge General Purpose Inpu/Oupu High-bandwidh Digial Conen Proecion High-Definiion Mulimedia Inerface Ho Plug Deec Iner-Inegraed Circui Iner-IC Sound, Inegraed Inerchip Sound Key Selecion Vecor Non Volaile Memory Pulse Code Modulaion Sony/Philips Digial Inerface Forma Transiion Minimized Differenial Signaling Thin Quad Fla Pack 6 SiI-DS-1059-D

1. General Descripion The SiI9127A/SiI1127A HDMI Receiver wih Deep Color Oupus from Laice Semiconducor Corporaion is a 2-por receiver ha allows DTVs ha can display 10/12-bi color deph o provide he highes qualiy proeced digial audio and video over a single cable. The SiI9127A/SiI1127A receiver can receive Deep Color video up o 12-bi, 1080p a 60 Hz. Efficien color space conversion receives RGB or YCbCr video daa and sends eiher sandard-definiion or high-definiion RGB or YCbCr formas. The SiI9127A/SiI1127A receiver suppors he exended gamu YCC or xvycc color space described in he IEC 61966-2-4 Specificaion, which suppors approximaely 1.8 imes he number of colors as he RGB color space. The xvycc color space also makes full use of he range provided by he sandard 8-bi resoluion per pixel forma. The SiI9127A receiver is preprogrammed wih High-bandwidh Digial Conen Proecion (HDCP) keys and conains an inegraed HDCP decrypion engine for receiving proeced audio and video conen. This se of keys helps reduce programming overhead, lowers manufacuring coss, and provides he highes level of securiy. The SiI1127A receiver is funcionally equien o he SiI9127A receiver excep ha he HDCP keys are no preprogrammed, herefore SiI1127A does no suppor HDCP decrypion. An inegraed Exended Display Idenificaion Daa (EDID) block sored in non-volaile memory (NVM) can be programmed a he ime of manufacure using he local I 2 C bus. On-board RAM can also be loaded hrough he I 2 C bus wih EDID daa from he sysem microconroller during iniializaion if he EDID conen of he NVM is no used. Up o 2 HDMI Sources (DVD Player, Se Top Box, HD Camcorder, Game Console, ec.) The EDID is refleced on he wo HDMI pors hrough he DDC bus. The device allows differen EDID formas o be mixed in an applicaion. Having he flexibiliy o provide EDID conen from he sources described above or from exernal ROM can eliminae up o wo EDID ROMs and save board space. Flexible power managemen provides exremely low sandby power consumpion. Sandby power can be supplied from an HDMI 5 V signal or from a separae sandby power pin. If he NVM sores he EDID, only he 5 V power from he source device is needed o read he EDID. Inpus Two HDMI/DVI-compaible pors The TMDS core runs a 25 MHz 225 MHz Dynamic cable equalizaion auomaically deecs he equalizaion required for he incoming signal Digial Video Oupu xvycc o exended RGB 36-bi RGB/YCbCr 4:4:4 16/20/24-bi YCbCr 4:2:2 8/10/12-bi YCbCr 4:2:2 (ITU BT.656) True 12-bi accurae oupu daa using an inernal 14-bi wide processing pah Drive srengh is programmable from 2 ma o 14 ma Display (DTV, LCD, Plasma, Projecor) HD Camcorder HDMI SiI9127A/ SiI1127A HDMI Receiver Video Audio Video Processor Blu-ray DVD L Audio DAC/Amp R Figure 1.1. Digial Television Sysem Diagram SiI-DS-1059-D 7

Digial Audio Inerface Sends and receives up o wo channels of uncompressed digial audio a he rae of 192 khz. I 2 S oupu wih one daa signal for sereo formas S/PDIF oupu suppors PCM, Dolby Digial, DTS digial audio ransmission wih a 32 khz 192 khz Fs sample rae Inelligen audio mue capabiliy avoids pops and noise wih auomaic sof mue and unmue IEC60958 or IEC61937 compaible Consumer Elecronic Conrol Consumer Elecronics Conrol (CEC) inerface incorporaes an HDMI CEC I/O An inegraed CEC Programming Inerface (CPI) relieves he burden of he microconroller having o wrie low-level commands Auomaic Feaure Abor response for unsuppored commands Auomaic Message Rery on ransmi Sysem Applicaions The SiI9127A/SiI1127A receiver is designed for digial elevisions ha require suppor for HDMI Deep Color. The device allows receip of 10/12-bi color deph up o 1080p resoluions. A single receiver chip provides wo HDMI inpu pors. The video oupu inerfaces o a video processor and he audio oupu can inerface direcly o an audio DAC or an audio DSP for furher processing as shown in Figure 3.1. Package 14 mm 14 mm 128-pin TQFP package wih an exposed pad (epad). 8 SiI-DS-1059-D

2. Produc Family Table 2.1 summarizes he funcional differences among he SiI9127A/SiI1127A, SiI9125, SiI9135A, SiI9223A and he SiI9233A receivers. Table 2.1. Summary of New Feaures Feaure SiI9125 SiI9127A/SiI1127A SiI9135A SiI9223A SiI9233A HDMI Inpu Connecions TMDS Inpu Pors 2 2 2 4 4 Color Deph 8/10/12-bi 8/10/12-bi 8/10/12-bi 8/10/12-bi 8/10/12-bi DDC Inpu Pors 2 2 2 4 4 Maximum TMDS Inpu Clock 225 MHz 225 MHz 225 MHz 225 MHz 225 MHz Video Oupu Digial Video Oupu Pors 1 1 1 1 1 Maximum Oupu Pixel Clock 165 MHz 165 MHz 165 MHz 165 MHz 165 MHz Maximum Oupu Bus Widh 36 36 36 36 36 Audio Formas S/PDIF Oupu Pors 1 1 1 1 1 I 2 S Oupu 2 channel 2 channel 8 channel 2 channel 8 channel DSD Oupu 2 channel NA 6 channel NA 8 channel High Bi Rae Audio Suppor Compressed DTS-HD and Dolby True-HD Maximum Audio Sample Rae (Fs) Video Processing Color Space Converer No No Yes No Yes 192 khz 192 khz 192 khz 192 khz 192 khz RGB o/from YCbCr RGB o/from YCbCr xvycc o RGB RGB o/from YCbCr RGB o/from YCbCr xvycc o RGB RGB o/from YCbCr xvycc o RGB Pixel Clock Divider 4, 2 4, 2 4, 2 4, 2 4, 2 Digial Video Bus Mapping swap Cb, Cr pins swap Cb, Cr pins swap Cb, Cr pins swap Cb, Cr pins swap Cb, Cr pins Oher Feaures Local fixed I 2 C Device Address 1 Programmable I 2 C Device Address 1 0x60/0x68 or 0x62/0x6A 0x60/0x68 or 0x62/0x6A 0x60/0x68 or 0x62/0x6A 0x60/0x68 or 0x62/0x6A 0x60/0x68 or 0x62/0x6A NA 0x64, 0xC0, 0xE0 NA 0x64, 0xC0, 0xE0 0x64, 0xC0, 0xE0 Reserved I 2 C Device Address 2 NA 0x90, 0xD0, 0xE6 NA 0x90, 0xD0, 0xE6 0x90, 0xD0, 0xE6 3D Suppor No Yes No Yes Yes CEC No Yes No Yes Yes EDID No NVRAM No NVRAM NVRAM HDCP Repeaer Suppor No No Yes No Yes Inerlaced Forma Deecion Pin Package Yes Yes Yes Yes Yes 144-pin TQFP epad 128-pin TQFP epad 144-pin TQFP epad 144-pin TQFP epad 144-pin TQFP epad Noes: 1. Refer o he SiI9223A/SiI9233A/SiI9127A/SiI1127A HDMI Receivers Programmer Reference for a descripion of hese I 2 C regiser addresses. 2. These are reserved I 2 C regiser addresses which are wihin he I 2 C regiser address map of he chip. Do no access hese regisers on he chip and do no use hese addresses for oher devices, in he sysem which use he same I 2 C bus. SiI-DS-1059-D 9

3. Funcional Descripion The SiI9127A/SiI1127A receiver provides a complee soluion for receiving HDMI-complian digial audio and video. Specialized audio and video processing is available wihin he receiver o add HDMI capabiliy o consumer elecronics such as DTVs. Figure 3.1 shows he SiI9127A/SiI1127A receiver incorporaed ino a digial elevision reciever. Figure 3.2 on he nex page shows he funcional blocks of he chip. The receiver suppors wo HDMI inpu pors. Only one por can be acive a any ime. HDMI Por 2 Connecor Sysem Microconroller R1PWR5V TMDS2 INT DDC2 CEC I 2 C HDMI Por 1 Connecor HPD2 R2PWR5V SiI9127A/ SiI1127A 36-bi Video Video Processor TMDS1 DDC1 HPD1 I 2 S Audio Audio DAC Speakers Figure 3.1. Digial Television Receiver Block Diagram TMDS Digial Cores The TMDS digial core is he laes generaion core ha suppors HDMI and he abiliy o carry 10/12-bi color deph. The core can receive TMDS daa a up o 225 MHz. Each core performs 10-o-8 bi TMDS decoding on he video daa and 10-o-4 bi TMDS decoding on he audio daa received from he hree TMDS differenial daa lines along wih a TMDS differenial clock. The TMDS core can sense a sopped clock or sopped video and sofware can pu he receiver ino power-down mode. Acive Por Deecion and Selecion Only one por can be acive a a ime, under conrol of he receiver firmware. Acive TMDS signaling can arrive a boh pors, bu only one has inernal circuiry enabled. The firmware in he display conrols hese saes using regiser seings. Oher conrol signals are associaed wih he TMDS signals on each HDMI por. The receiver can monior he +5 V supply from each aached hos. The firmware can poll regisers o check which pors are conneced. The firmware also conrols funcional connecion o one of he wo E-DDC buses, enabling one while disabling he oher. An aached hos deermines he acive saus of an aached HDMI device by polling he E-DDC bus o he device. Refer o he SiI-PR-1033 Programmer Reference (see Laice Semiconducor Documens on page 74) for a complee descripion of por deecion and selecion. The Programmer s Reference requires an NDA wih Laice Semiconducor. 10 SiI-DS-1059-D

CEC_A CEC CEC_D DSDA1 DSDA2 DSCL1 DSCL2 CSDA CSCL CI2CA Serial Hos Inerface (DDC) Serial Hos Inerface (local) HDCP Regisers SRAM RPI Regisers and Sae Machine EDID NVRAM Configuraion and Saus Regisers HDCP Engine Embedded HDCP Keys Ho Plug Conroller HPD1 HPD2 INT Video Processing R1XC+ R1XC- R1X0+ R1X0- R1X1+ R1X1- R1X2+ R1X2- R2XC+ R2XC- R2X0+ R2X0- R2X1+ R2X1- R2X2+ R2X2- HDMI Receiver Mux SCDT Logic A/V Spli Video HDCP Unmask HDMI Decode Audio HDCP Unmask Deep Color Up/Down Sampling Color Space Converer Auo Video Configuraion Audio Clock Regeneraion APLL Auo Audio Audio Processing Video Oupu Forma Audio Oupu S/PDIF Oupu I 2 S Oupu ODCK Q[35:0] DE HSYNC VSYNC EVNODD SPDIF SCK/DCLK WS SD0 MUTEOUT XTALIN XTALOUT MCLK SCDT R1PWR5V R2PWR5V RESET# Rese Logic Noe: HDCP blocks do no apply o he SiI1127A receiver. Figure 3.2. Funcional Block Diagram HDCP Decrypion Engine/XOR Mask The HDCP decrypion engine conains all he necessary logic o decryp he incoming audio and video daa. The decrypion process is enirely conrolled by he hos-side microconroller/microprocessor hrough a se sequence of regiser reads and wries hrough he DDC channel. Preprogrammed HDCP keys and Key Selecion Vecor (KSV) sored in he on-chip non-volaile memory are used in he decrypion process. A resuling calculaed ue is applied o an XOR mask during each clock cycle o decryp he audio and video daa. SiI-DS-1059-D 11

HDCP Embedded Keys The SiI9127A receiver comes preprogrammed wih a se of producion HDCP keys sored on-chip in non-volaile memory. Sysem manufacurers do no need o purchase key ses from he Digial Conen Proecion LLC. All purchasing, programming, and securiy for he HDCP keys is handled by Laice Semiconducor. The preprogrammed HDCP keys provide he highes level of securiy, as keys canno be read ou of he device afer hey are programmed. Before receiving samples of he receiver, cusomers mus sign he HDCP license agreemen available from Digial Conen Proecion, LLC, or have a special NDA wih Laice Semiconducor. The SiI1127A receiver does no come preprogrammed wih a se of producion HDCP keys sored on-chip in nonvolaile memory. Daa Inpu and Conversion Mode Conrol Logic The mode conrol logic deermines if he decryped daa is video, audio, or auxiliary informaion, and direcs i o he appropriae logic block. Video Daa Conversion and Video Oupu The SiI9127A/SiI1127A receiver can oupu video in many differen formas (see he examples in Table 3.1) and can process he video daa before i is sen, as shown in Figure 3.3. I is possible o bypass each of he processing blocks by seing he appropriae regiser bis. Table 3.1. Digial Video Oupu Formas Color Space Video Forma RGB 4:4:4 YCbCr 4:4:4 4:2:2 Bus Widh HSYNC/ VSYNC Oupu Clock (MHz) 480i/576i 2, 3 480p XGA 720p 1080i SXGA 1080p UXGA 36 Separae 27 27 65 74.25 74.25 108 148.5 162 30 Separae 27 27 65 74.25 74.25 108 148.5 162 24 Separae 27 27 65 74.25 74.25 108 148.5 162 12/15/18 Separae 27 27 65 74.25 74.25 4 36 Separae 27 27 65 74.25 74.25 108 148.5 162 30 Separae 27 27 65 74.25 74.25 108 148.5 162 24 Separae 27 27 65 74.25 74.25 108 148.5 162 12/15/18 Separae 27 27 65 74.25 74.25 4 16/20/24 Separae 27 27 74.25 74.25 148.5 162 16/20/24 Embedded 27 27 74.25 74.25 148.5 162 1 8/10/12 Separae 27 54 148.5 148.5 8/10/12 Embedded 27 54 148.5 148.5 1 Noes: 1. Embedded syncs use SAV/EAV coding. 2. 480i and 576i modes can oupu a 13.25 MHz clock using he inernal clock divider. 3. Oupu clock frequency depends on programming of inernal regisers. Differenial TMDS clock is always 25 MHz or faser. 4. Oupu clock suppors 12/15/18-bi mode by using boh edges. Color Range Scaling The color range depends on he video forma, according o he CEA-861D specificaion. In some applicaions he 8-bi inpu range uses he enire span of 0x00 (0) o 0xFF (255) ues. In oher applicaions he range is scaled narrower. The receiver canno deec he incoming video daa range and here is no required range specificaion in he HDMI AVI packe. The device chooses scaling depending on he deeced video forma. 10 and 12-bi color range scaling are boh handled he same way. Refer o he SiI-PR-1033 Programmer Reference for more deails. When he receiver oupus embedded syncs (SAV/EAV codes), i also limis he YCbCr daa oupu ues o 1 o 254. Noes 12 SiI-DS-1059-D

Up Sample/Down Sample Addiional logic can conver from 4:2:2 o 4:4:4 (8/10/12-bi) or from 4:4:4 (8/10/12-bi) o 4:2:2 YCbCr forma. All processing is done wih 14 bis of accuracy for rue 12-bi daa. Deep Color Suppor The HDMI 1.3 Specificaion inroduces Color Deph modes greaer han 24 bis, known as Deep Color modes, o he HDMI sysem archiecure. The Deep Color modes employ a new pixel packing scheme o enable he exra bis of higher color deph daa o be carried over he exising TMDS daa encoding scheme. Currenly, hree Deep Color modes are defined: 30-bi, 36-bi, and 48-bi. The SiI9127A/SiI1127A receiver suppors wo of hese hree Deep Color modes; 30-bi, and 36-bi modes. In addiion, each Deep Color mode is suppored up o 1080p HD forma. For Deep Color modes, he TMDS clock is run faser han he pixel clock in order o creae exra bandwidh for he addiional bis of he higher color deph daa. The increase in he TMDS clock is by he raio of he pixel size o 24 bis, as follows: 30-bi mode: TMDS clock = 1.25x pixel clock (5:4) 36-bi mode: TMDS clock = 1.5x pixel clock (3:2) Because he receiver suppors 36-bi mode a 1080p, he highes TMDS clock rae i suppors is herefore 225 MHz. When in Deep Color mode, he ransmier periodically sends a General Conrol Packe wih he curren color deph and pixel packing phase informaion o he receiver. The receiver capures he color deph informaion in a regiser, which he firmware can hen use o se he appropriae clock divider o recover he pixel clock and daa. xvycc The SiI9127A/SiI1127A receiver adds suppor for he exended gamu xvycc color space; his exended forma has roughly 1.8 imes more colors han he RGB color space. The use of he xvycc color space is made possible because of he availabiliy of LED and laser based ligh sources for he nex generaion displays. This forma also makes use of he full range of ues 1 o 254 in an 8-bi space insead of 16 o 235 in he RGB forma. The use of xvycc along wih Deep Color helps in reducing color banding and allows display of a larger range of colors han is currenly possible. Color Space Conversion Color space converer (CSC) blocks are provided o conver RGB daa o Sandard-Definiion (ITU.601) or High- Definiion (ITU.709) YCbCr formas, and vice-versa. To suppor he laes exended-gamu xvycc displays, he SiI9127A/SiI1127A receiver implemens color space converer blocks o conver RGB daa o exended-gamu Sandard- Definiion (ITU.601) or High-Definiion (ITU.709) xvycc formas, and vice-versa. RGB o YCbCr The RGB YCbCr color space converer (CSC) can conver from video daa RGB o sandard definiion (ITU.601) or o high definiion (ITU.709) YCbCr formas. The HDMI AVI packe defines he color space of he incoming video. YCbCr o RGB The YCbCr RGB color space converer is available o inerface o MPEG decoders wih RGB-only inpus. The CSC can conver from YCbCr in sandard-definiion (ITU.601) or high-definiion (ITU.709) o RGB. 3D Video Formas The SiI9127A/SiI1127A receiver has suppor for he 3D video modes described in he HDMI 1.4 Specificaion. All modes suppor RGB 4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2 color formas and 8-, 10-, and 12-bi daa widh per color componen. Table 3.2 on he nex page shows only he maximum possible resoluion wih a given frame rae; for example, Side-by- Side (Half) mode is defined for 1080p60, which implies ha 720p60 and 480p60 are also suppored. Furhermore, a frame rae of 24 Hz also means ha a frame rae of 23.98 Hz is suppored and a frame rae of 60 Hz also means a frame rae of 59.94 Hz is suppored. The inpu pixel clock changes accordingly. When using Side-by-Side formas he use of 4:2:2 o 4:4:4 up-sampling and 4:4:4 o 4:2:2 down-sampling should no be enabled as i may resul in visible arifacs. Video processing should be bypassed in he case of L + deph forma. SiI-DS-1059-D 13

Table 3.2. Suppored 3D Video Formas 3D Forma Exended Definiion Resoluion Frame Rae (Hz) Inpu Pixel Clock (MHz) 1080p 24 Frame Packing 720p 50 / 60 inerlaced 1080i 50 / 60 1080p 24 L + deph 148.5 720p 50 / 60 1080p 24 full 720p 50 / 60 Side-by-Side 1080p 50 / 60 half 1080i 50 / 60 74.25 Defaul Video Configuraion Afer hardware rese, he SiI9127A/SiI1127A chip is configured in is defaul mode. This mode is summarized in Table 3.3. For more deails and for a complee regiser lising, refer o he SiI-PR-1033 Programmer Reference. Table 3.3. Defaul Video Processing Video Conrol HDCP Decrypion Color Space Conversion Color Space Selecion Color Range Scaling Upsampling/Downsampling HSYNC & VSYNC Timing Daa Bi Widh Pixel Clock Replicaion Power Down Defaul afer Hardware Rese HDCP decrypion is OFF No color space conversion BT.601 seleced No range scaling No upsampling or downsampling No inversions of HSYNC or VSYNC Uses 8-bi daa No pixel clock replicaion Everyhing is powered down Noes: 1. The receiver assumes DVI mode afer rese, which is RGB 24-bi 4:4:4 video wih a range of 0 255. 2. HDCP decrypion is no suppored on he SiI1127A receiver. TMDS HDCP Widen o 14-Bis bypass RGB o YCbCr YCbCr Range Reduce Down Sample 4:4:4 o 4:2:2 bypass bypass Upsample 4:2:2 o 4:4:4 xvycc/ YCbCr o RGB RGB Range Expand Diher Module Mux 656 Video Timing DE HSYNC bypass bypass bypass VSYNC Noe: HDCP decoding does no apply o he SiI1127A receiver. ODCK Q[35:0] Figure 3.3. Defaul Video Processing Pah 14 SiI-DS-1059-D

Auomaic Video Configuraion The SiI9127A/SiI1127A receiver adds auomaic video configuraion o simplify he firmware ask of updaing he video pah whenever he incoming video changes forma. Bis in he HDMI Auxiliary Video Informaion (AVI) InfoFrame are used o reprogram he regisers in he video pah. Table 3.4. AVI InfoFrame Video Pah Deails AVI Bye 1 Bis [6:5] AVI Bye 2 Bis [7:6] AVI Bye 5 Bis [3:0] Y[1:0] Color Space C[1:0] Colorimeric PR[3:0] Pixel Repeiion 00 RGB 4:4:4 00 No Daa 0000 No repeiion 01 YCbCr 4:2:2 01 ITU 601 0001 Pixel sen 2 imes 10 YCbCr 4:4:4 10 ITU 709 0010 Pixel sen 3 imes 11 Fuure 11 Exended Colorimery Informaion Valid Noes: 1. The Auo Video Configuraion assumes ha he AVI informaion is accurae. If informaion is no available, hen he receiver mus choose he video pah based on measuremen of he incoming resoluion. 2. Refer o EIA/CEA-861D Specificaion for deails. 3. The SiI9127A/SiI1127A device can suppor only pixel replicaion modes 0b0000, 0b0001, and 0b0011. Oher modes are unsuppored and can resul in an unpredicable behavior. 0011 Pixel sen 4 imes 0100 Pixel sen 5 imes 0101 Pixel sen 6 imes 0110 Pixel sen 7 imes 0111 Pixel sen 8 imes 1000 Pixel sen 9 imes 1001 Pixel sen 10 imes The forma of he digial video oupu bus can be auomaically configured o many differen formas by programming he Auo Oupu Forma Regiser. The available formas are lised in Table 3.5. For deailed definiions of how o se his regiser, refer o he SiI-PR-1033 Programmer Reference. Table 3.5. Digial Oupu Formas Configurable hrough Auo Oupu Forma Regiser Digial Oupu Formas Color Widh MUX Sync RGB 4:4:4 N Separae YCbCr 4:4:4 N Separae YCbCr 4:2:2 N Separae YCbCr 4:2:2 Y Separae YCbCr 4:2:2 Y Embedded Audio Daa Oupu Logic The SiI9127A/SiI1127A receiver can send digial audio over S/PDIF and wo-channel I 2 S oupus. S/PDIF The S/PDIF sream can carry 2-channel uncompressed PCM daa (IEC 60958). The audio daa oupu logic forms he audio daa oupu sream from he decoded HDMI audio packes. The S/PDIF oupu suppors audio sampling raes from 32 khz o 192 khz. A separae maser clock oupu (MCLK), coheren wih he S/PDIF oupu, is provided for imesamping purposes. Coheren means ha he MCLK and S/PDIF are creaed from he same clock source. I 2 S The I 2 S bus forma is programmable hrough regisers, o allow inerfacing wih I 2 S audio DACs or audio DSPs wih I 2 S inpus. Refer o he SiI-PR-1033 Programmer Reference for he differen opions on he I 2 S bus. Addiionally, he MCLK (audio maser clock) frequency is selecable o be an ineger muliple of he audio sample rae Fs. MCLK frequencies suppor various audio sample raes as shown in Table 3.6 on he nex page. SiI-DS-1059-D 15

Table 3.6. Suppored MCLK Frequencies Muliple of Fs Audio Sample Rae, Fs: I 2 S and S/PDIF Suppored Raes 32 khz 44.1 khz 48 khz 88.2 khz 96 khz 176.4 khz 192 khz 128 4.096 MHz 5.645 MHz 6.144 MHz 11.290 MHz 12.288 MHz 22.579 MHz 24.576 MHz 192 6.144 MHz 8.467 MHz 9.216 MHz 16.934 MHz 18.432 MHz 33.868 MHz 36.864 MHz 256 8.192 MHz 11.290 MHz 12.288 MHz 22.579 MHz 24.576 MHz 45.158 MHz 49.152 MHz 384 12.288 MHz 16.934 MHz 18.432 MHz 33.864 MHz 36.864 MHz 512 16.384 MHz 22.579 MHz 24.576 MHz 45.158 MHz 49.152 MHz Conrol and Configuraion Regiser/Configuraion Logic The Regiser/Configuraion Logic block incorporaes all he regisers required for configuring and managing he feaures of he SiI9127A/SiI1127A receiver. These regisers are used o perform HDCP auhenicaion; audio, video, or auxiliary forma processing; CEA-861B InfoFrame Packe forma; and power-down conrol. The regisers are accessible from one of he wo serial pors. The firs por is he DDC por, which is conneced hrough he HDMI cable o he HDMI hos. I is used o conrol he receiver from he hos sysem for HDCP operaion. The second por is he local I 2 C por, which is used o conrol he receiver from he display sysem. This is shown in Figure 3.4. The Local Bus accesses he General Regisers and he Common Regisers. The DDC Bus accesses he HDCP Operaion regisers and he Common Regisers. The HDCP Operaion regisers are no applicable o he SiI1127A receiver. Accessible from DDC Bus HDCP Operaion Common Regisers General Regisers Video Processing Audio Processing InfoFrames Accessible from Local I 2 C Bus Repeaer Inerrups I 2 C Serial Pors Figure 3.4. I 2 C Regiser Domains The SiI9127A/SiI1127A receiver provides hree I 2 C serial inerfaces: wo DDC pors o communicae back o he HDMI or DVI hoss, along wih one I 2 C por for iniializaion and conrol by a local microconroller in he display. Each inerface is 5 V oleran. E-DDC Bus Inerface o HDMI Hos The wo DDC inerfaces, DSDA1-2 and DSCL1-2, on he receiver are slave inerfaces ha can run up o 100 khz. Each inerface is conneced o one E-DDC bus and is used for reading he inegraed EDID in addiion o HDCP auhenicaion. 16 SiI-DS-1059-D

The SiI9127A/SiI1127A receiver is accessible on he E-DDC bus a device addresses 0xA0 for he EDID, and 0x74 for HDCP conrol. This feaure complies wih he HDCP Specificaion. EDID FLASH and RAM Block The EDID block consiss of 512 byes of RAM. Each por has a block of 256 byes of RAM for EDID daa. This feaure allows simulaneous reads of boh pors from wo differen source devices ha are conneced o he SiI9127A/SiI1127A device. In addiion o he RAM, he EDID block conains 256 byes of FLASH ha is shared by boh pors. As a resul, he iming informaion mus be idenical beween boh pors if he inernal EDID is used. An addiional area of FLASH conains unique CEC physical address and checksum ues for each of he pors. This feaure allows simulaneous reads of boh pors from wo differen source devices if hey are conneced and aemp an EDID read a he same ime. If independen EDIDs are required on any of he pors, a CPU can exernally load he 256 byes of RAM for ha por, by using he local I 2 C bus. The inernal EDID can be seleced on a per-por basis using regisers on he local I 2 C bus. For example, Por 1 can use he inernal EDID, and Por 2 can use a discree EEPROM for he EDID. CEC Inerface The Consumer Elecronics Conrol (CEC) Inerface block provides CEC elecrically complian signals beween CEC devices and a CEC maser. I allows producs o mee he elecrical specificaions of CEC signaling by ranslaing he LVTTL signals of an exernal microconroller (CEC hos-side or ransmi-side) o CEC signaling levels for CEC devices a he receive side, and vice versa. Addiionally, a CEC conroller compaible wih he Laice Semiconducor CEC Programming Inerface (CPI) is included on-chip. This CEC conroller has a high-level regiser inerface accessible hrough he I 2 C inerface which can be used o send and receive CEC commands. This conroller makes CEC conrol very easy and sraighforward, and removes he burden of having a hos CPU perform hese low-level ransacions on he CEC bus. As a resul, CEC pass-hrough mode is neiher required nor suppored. I 2 C Inerface o Display Conroller The Conroller I 2 C inerface (CSDA, CSCL) on he SiI9127A/SiI1127A receiver is a slave inerface capable of running up o 400 khz. This bus is used o configure he chip by reading or wriing o he appropriae regisers. I is accessible on he local I 2 C bus a wo device addresses. Refer o he SiI-PR-1033 Programmer Reference for more informaion. Sandby and HDMI Por Power Supplies The receiver incorporaes a power island ha coninues o supply power o he EDID memory, he DDC pors, and he CEC bus when power is removed from he VCC pins, as long as power coninues o be provided hrough a leas one conneced HDMI cable or by sysem sandby power. Refer o Figure 3.5 on he nex page. The inernal power muliplexer selecs power from eiher SBVCC5, if i is available, or from one of he RnPWR5V pins. The power island resuls in an exremely low power sandby mode, bu allows he EDID o be readable and he CEC conroller o be funcional. No damage will occur o he device when in his mode. SiI-DS-1059-D 17

HDMI Por Sysem Sandby 5 V Sysem Main 5 V RnRPWR5V SBVCC5 Regulaor +3.3 V +1.2 V Power MUX On-Chip Regulaor +3.3 V DDC I 2 C Logic Power-On Rese EDID RAM CEC Logic Main Chip Logic +3.3 V On-Chip Regulaor +1.2 V NV Memory OTP ROM Power Island Figure 3.5. Power Island 18 SiI-DS-1059-D

4. Elecrical Specificaions Absolue Maximum Condiions Symbol Parameer Min Typ Max Unis Noe IOVCC33 I/O Pin Supply Volage 0.3 4.0 V 1, 2, 3 AVCC12 TMDS Analog Supply Volage 0.3 1.9 V 1, 2 AVCC33 TMDS Analog Supply Volage 0.3 4.0 V 1, 2 APVCC12 Audio PLL Supply Volage 0.3 1.9 V 1, 2 CVCC12 Digial Core Supply Volage 0.3 1.9 V 1, 2 XTALVCC33 ACR PLL Crysal Oscillaor Supply Volage 0.3 4.0 V 1, 2 SBVCC5 Sandby Supply Volage 0.3 5.7 V 1,2 V I Inpu Volage 0.3 IOVCC33 + 0.3 V 1, 2 V 5V-Toleran Inpu Volage on 5 V oleran Pins 0.3 5.5 V 5 T J Juncion Temperaure 125 C T STG Sorage Temperaure 65 150 C Noes: 1. Permanen device damage can occur if absolue maximum condiions are exceeded. 2. Funcional operaion should be resriced o he condiions described in he Normal Operaing Condiions secion on page 20. 3. Volage undershoo or overshoo canno exceed absolue maximum condiions. 4. Refer o he SiI9127A/SiI1127A receiver Qualificaion Repor for informaion on ESD performance. 5. All VCC supplies mus be available o he device. If he device is no powered and 5 V is applied o hese inpus, damage can occur. SiI-DS-1059-D 19

Normal Operaing Condiions Symbol Parameer Min Typ Max Unis Noe IOVCC33 I/O Pin Supply Volage 3.13 3.3 3.47 V 1, 4 AVCC12 TMDS Analog Supply Volage 1.14 1.2 1.26 V 3 AVCC33 TMDS Analog Supply Volage 3.13 3.3 3.47 V 1, 6 APVCC12 Audio PLL Supply Volage 1.14 1.2 1.26 V CVCC12 Digial Core Supply Volage 1.14 1.2 1.26 V 2 XTALVCC33 ACR PLL Crysal Oscillaor Supply Volage 3.13 3.3 3.47 V 4 SBVCC5 Sandby Supply Volage 4.75 5.0 5.25 V 10 RnPWR5V DDC I 2 C I/O Reference Volage 4.7 5.00 5.3 V 11 DIFF33 Difference beween wo 3.3-V Power Pins 1.0 V 4 DIFF12 Difference beween wo 1.2-V Power Pins 1.0 V 4 DIFF3312 Difference beween any 3.3-V and 1.2-V Pin 1.0 2.6 V 4, 5 V CCN Supply Volage Noise 100 mv P-P 7 T A Ambien Temperaure (wih power applied) 0 25 70 C ja Ambien Thermal Resisance (Thea JA) 27 C/W Noes: 1. IOVCC33 and AVCC33 pins should be conrolled from one power source. 2. CVCC12 should be conrolled from one power source. 3. AVCC12 pin should be regulaed. 4. Power supply sequencing mus guaranee ha power pins say wihin hese limis of each oher. See Figure 5.2. 5. No 1.2 V pin can be more han DIFF3312[min] higher han any 3.3 V pin. No 3.3 V pin can be more han DIFF3312[max] higher han any 1.2 V pin. 6. The HDMI Specificaion requires erminaion volage (AVCC33) o be conrolled o 3.3 V±5%. The SiI9127A/SiI1127A receiver oleraes a wider range of ±300 mv. 7. The supply volage noise is measured a es poin VCCTP in Figure 4.1. The ferrie bead provides filering of power supply noise. The figure is represenaive and applies o oher VCC pins as well. 8. Airflow a 0 m/s. 9. The schemaics on page 65 show decoupling and power supply regulaion. 10. SBVCC5V should provide a sable 5 V before any oher VCC is applied o he device; see he Power Supply Sequencing secion on page 28. 11. Maximum curren draw from his source is 50 ma. There is no power-on sequence requiremen for his source. VCCT P 0. 56 0.1 F Parasiic Resisor Ferrie 0. 82 H, 150 ma + 10 F 0.1 F 1 nf AVCC12 SiI9127A/ SiI1127A GND Figure 4.1. Tes Poin VCCTP for VCC Noise Tolerance Specificaion Noes: 1. The Ferrie (0.82 H, 150 ma) aenuaes he PLL power supply noise a 10 khz and above. 2. The opional parasiic resisor minimizes he peaking. The ypical ue used here is 0.56. 1 is he maximum. 20 SiI-DS-1059-D

DC Specificaions Digial I/O Specificaions Symbol Parameer Pin Type 3 Condiions 2 Min Typ Max Unis Noe V IH HIGH-level Inpu Volage LVTTL 2.0 V V IL LOW-level Inpu Volage LVTTL 0.8 V V TH+ V TH- DDC V TH+ DDC V TH- Local I 2 C V TH+ Local I 2 C V TH- LOW o HIGH Threshold RESET # Pin HIGH o LOW Threshold RESET# Pin LOW o HIGH Threshold DSDA0, DSDA1, DSCL0, and DSCL1 pins. HIGH o LOW Threshold DSDA0, DSDA1, DSCL0, and DSCL1 pins. LOW o HIGH Threshold CSCL and CSDA pins HIGH o LOW Threshold CSCL and CSDA pins Schmi 1.46 V 5 Schmi 0.96 V 5 Schmi 3.0 V Schmi 1.5 V Schmi 2.1 V 11, 13 Schmi 0.86 V 11, 13 V OH HIGH-level Oupu Volage LVTTL 2.4 V 10 V OL LOW-level Oupu Volage LVTTL 0.4 V 10 I OL Oupu Leakage Curren High Impedance 10 10 A V ID Differenial Inpu Volage 75 250 780 mv 4 I OD4 4 ma Digial Oupu Drive Oupu I OD8 8 ma Digial Oupu Drive Oupu I OD12 12 ma Digial Oupu Drive Oupu V OUT = 2.4 V 4 ma 1, 6, 7 V OUT = 0.4 V 4 ma 1, 6, 7 V OUT = 2.4 V 8 ma 1, 6, 8 V OUT = 0.4 V 8 ma 1, 6, 8 V OUT = 2.4 V 12 ma 1, 6, 9 V OUT = 0.4 V 12 ma 1, 6, 9 R PD Inernal Pull Down Resisor Oupus IOVCC33 = 3.3 V 25 50 110 kω 1, 12 I OPD Oupu Pull Down Curren Oupus IOVCC33 = 3.6 V 60 90 A 1, 12 I IPD Inpu Pull Down Curren Inpu IOVCC33 = 3.6 V 60 90 A 1 Noes: 1. These limis are guaraneed by design. 2. Under normal operaing condiions unless oherwise specified, including oupu pin loading C L = 10 pf. 3. See he Pin Descripions secion on page 36 for pin ype designaions for all package pins. 4. Differenial inpu volage is a single-ended measuremen, according o DVI Specificaion. 5. Schmi rigger inpu pin hresholds V TH+ and V TH- correspond o V IH and V IL, respecively. 6. Minimum oupu drive specified a ambien = 70 C and IOVCC33 = 3.0 V. Typical oupu drive specified a ambien = 25 C and IOVCC33 = 3.3 V. Maximum oupu drive specified a ambien = 0 C and IOVCC33 = 3.6 V. 7. I OD4 Oupu applies o pins SPDIF, SCK, WS, SD[3:0], DCLK, INT, and CSDA. 8. I OD8 Oupu applies o pins DE, HSYNC, VSYNC, Q[35:0].and MCLK. 9. I OD12 Oupu applies o pin ODCK. 10. Noe ha he S/PDIF oupu drives LVTTL levels, no he low-swing levels defined by IEC958. 11. The SCL and SDA pins are no rue open-drain buffers. When no VCC is applied o he chip, hese pins can coninue o draw a small curren, and preven he maser IC from communicaing wih oher devices on he I 2 C bus. Therefore, do no power-down he SiI9127A/SiI1127A receiver (remove VCC) unless he aached I 2 C bus is compleely idle. 12. The chip includes an inernal pull-down resisor on many of he oupu pins. When in he high-impedance sae, hese pins draw a pull- down curren according o his specificaion when he signal is driven HIGH by anoher source device. 13. Wih 10% IOVCC33 supply, he HIGH-o-LOW hreshold on DDC and I 2 C bus is marginal. A 5% olerance on he IOVCC33 power supply is recommended. SiI-DS-1059-D 21

DC Power Supply Pin Specificaions Toal Power versus Power-Down Modes Symbol Parameer Mode Frequency I PDQ3 I PDS I STBY I UNS I CCTD Complee Power-Down Curren Sleep Powerdown Curren Sandby Curren Unseleced Curren Full Power Digial Ou Curren Typ 3 Max 4 3.3 V 1.2 V SBVCC5 3.3 V 1.2 V SBVCC5 Unis A 65 3 8 ma 1, 6 B C D E 27 MHz 68 15 8 ma 74.25 MHz 85 19 8 ma 150 MHz 74 19 8 ma 225 MHz 74 19 8 ma 27 MHz 0 0 8 ma 74.25 MHz 0 0 8 ma 150 MHz 0 0 8 ma 225 MHz 0 0 8 ma 27 MHz 67 111 8 68 119 8 ma 74.25 MHz 70 173 8 72 180 8 ma 150 MHz 75 291 8 79 299 8 ma 225 MHz 78 313 8 79 315 8 ma 27 MHz 97 112 8 102 121 8 ma 74.25 MHz 158 175 8 167 177 8 ma 150 MHz 259 295 8 280 302 8 ma 225 MHz 335 321 8 366 326 8 ma Noes: 1. Power is no relaed o inpu TMDS clock (RxC) frequency because he seleced TMDS por is powered down. 2. Power is relaed o inpu TMDS clock (RxC) frequency a he seleced TMDS por. Only one por can be seleced. 3. Typical power specificaions measured wih supplies a ypical normal operaing condiions, and a video paern ha combines gray scale, checkerboard and. 4. Maximum power limis measured wih supplies a maximum normal operaing condiions, minimum normal operaing ambien emperaure, and a video paern wih single-pixel verical lines. 5. Regisers are always accessible on local I2C (CSDA/CSCL) wihou acive link clock. 6. Power Down Mode A: Minimum power. Everyhing is powered off. Hos sees no erminaion of TMDS signals on eiher TMDS por. I2C access is sill available. 7. Power Down Mode B: Powers down TMDS core. CKDT remains enabled and sae can be polled in regiser. Hos device can sense TMDS erminaion. 8. Power Down Mode C: Power off o 3.3 V and 1.2 V supplies. Power on o SBVCC5 sandby supply. 9. Power Down Mode D: Monior SCDT on seleced TMDS por wih oupus in he high-impedance sae. HDCP coninues in he seleced por, bu he oupu of he receiver can be conneced o a shared bus. 10. Digial Funcional Mode E: Full operaion on one por wih digial oupus. Noes 2, 7 2, 8 2, 9 2, 10 22 SiI-DS-1059-D

Power Down Mode Definiions A B C D Mode Power Down Sleep Mode Power Sandby Power Unseleced Power 3.3 V Supply 1.2 V Supply SBVCC5 Regiser Bi Saes PDTOT# PD_TMDS# PD_AO# PD_VO# ON ON ON 0 1 1 1 ON ON ON 1 0 1 1 OFF OFF ON 1 1 1 1 ON ON ON 1 1 0 0 E Digial ON ON ON 1 1 1 1 Descripion Minimum power. Everyhing is powered off. Hos sees no erminaion of TMDS signals on eiher TMDS por. I 2 C access is sill available. Powers down TMDS core. CKDT remains enabled and sae can be polled in regiser. Hos device can sense TMDS erminaion. Power off o 3.3 V and 1.2 V supplies. Power on o SBVCC5 sandby supply. Monior SCDT on seleced TMDS por wih oupus in he high-impedance sae. HDCP coninues in he seleced por, bu he oupu of he receiver can be conneced o a shared bus. Full operaion on one por wih digial oupus. Noes: 1. PD Clks include PD_MCLK#, PD_XTAL#, PD_APLL#, and PD_PCLK# all se o zero. 2. PD Ous include PD_AO#, and PD_VO# all se o zero. 3. Refer o he SiI-PR-1033 Programmer Reference for regiser bi descripions. The Programmer s Reference requires an NDA wih Laice Semiconducor. SiI-DS-1059-D 23

AC Specificaions TMDS Inpu Timings Symbol Parameer Condiions Min Typ Max Unis Figure Noes T DPS Inra-Pair Differenial Inpu Skew T BIT ps 2, 4 T CCS Channel o Channel Differenial Inpu Skew T CIP ns Figure 5.1 2, 3 F RXC Differenial Inpu Clock Frequency 25 225 MHz T RXC Differenial Inpu Clock Period 4.44 40 ns T IJIT Differenial Inpu Clock Jier olerance (0.3 Tbi) 74.25 MHz 400 ps 2, 5, 6 Noes: 1. Under normal operaing condiions unless oherwise specified, including oupu pin loading of C L = 10 pf. 2. Guaraneed by design. 3. IDCK Period. Refer o he applicable Laice Semiconducor HDMI Transmier. 4. 1/10 of IDCK Period. Refer o he applicable Laice Semiconducor HDMI Transmier. 5. Jier as defined by he HDMI Specificaion. 6. Jier measured wih Clock Recovery Uni per HDMI Specificaion. Acual jier olerance can be higher depending on he frequency of he jier. Refer o he SiI-PR-1033 Programmer Reference for more deails on conrolling iming modes. Video Oupu Timings 12/15/18-Bi Daa Oupu Timings Symbol Parameer Condiions Min Typ Max Unis Figure Noes D LHT LOW-o-HIGH Rise Time Transiion C L = 10 pf 1.5 ns Figure 5.4 2 D HLT HIGH-o-LOW Fall Time Transiion C L = 10 pf 1.5 ns Figure 5.4 2 R CIP ODCK Cycle Time C L = 10 pf 13 40 ns Figure 5.5 8 F CIP ODCK Frequency C L = 10 pf 25 82.5 MHz 5 T DUTY ODCK Duy Cycle C L = 10 pf 40% 60% R CIP Figure 5.5 3 T CK2OUT ODCK-o-Oupu Delay C L = 10 pf 0.6 3.8 ns Figure 5.5 16/20/24/30/36-Bi Daa Oupu Timings Symbol Parameer Condiions Min Typ Max Unis Figure Noes D LHT LOW-o-HIGH Rise Time Transiion C L = 10 pf 1.5 ns Figure 5.4 2 D HLT HIGH-o-LOW Fall Time Transiion C L = 10 pf 1.5 ns Figure 5.4 2 R CIP ODCK Cycle Time C L = 10 pf 40 ns Figure 5.5 5, 8 F CIP ODCK Frequency C L = 10 pf 165 MHz Figure 5.5 5 T DUTY ODCK Duy Cycle C L = 10 pf 40% 60% R CIP Figure 5.5 3 T CK2OUT ODCK-o-Oupu Delay C L = 10 pf 0.4 2.5 ns Figure 5.5 Noes: 1. Under normal operaing condiions unless oherwise specified, including oupu pin loading of C L = 10 pf. 2. Rise ime and fall ime specificaions apply o HSYNC, VSYNC, DE, ODCK, EVNODD and Q[35:0]. 3. Oupu clock duy cycle is independen of he differenial inpu clock duy cycle. Duy cycle is a componen of oupu seup and hold imes. 4. See Table 5.2 on page 33 for calculaion of wors case oupu seup and hold imes. 5. All oupu imings are defined a he maximum operaing ODCK frequency, F CIP, unless oherwise specified. 6. F CIP can be he same as F RXC or one-half of F RXC, depending on OCLKDIV seing. F CIP can also be F RXC /1.25 or F RXC /1.5 if Deep Color mode is being ransmied. 7. R CIP is he inverse of F CIP and is no a conrolling specificaion. 8. Oupu skew specified when ODCK is programmed o divide-by-wo mode. 24 SiI-DS-1059-D

Audio Oupu Timings I 2 S Oupu Por Timings Symbol Parameer Condiions Min Typ Max Unis Figure Noes T r SCK Clock Period (TX) C L = 10 pf 1.00 T r T HC SCK Clock HIGH Time C L = 10 pf 0.35 T r 1 T LC SCK Clock LOW Time C L = 10 pf 0.35 T r 1 T SU Seup Time, SCK o SD/WS C L = 10 pf 0.4T TR 5 ns Figure 5.6 1 T HD Hold Time, SCK o SD/WS C L = 10 pf 0.4T TR 5 ns 1 T SCKDUTY SCK Duy Cycle C L = 10 pf 40% 60% T r 1 T SCK2SD SCK o SD or WS Delay C L = 10 pf 5 +5 ns 2 T AUDDLY Audio Pipeline Delay 40 80 µs Noes: 1. Refer o Figure 5.6. Mees imings in Philips I 2 S Specificaion. 2. Applies also o SDC-o-WS delay. S/PDIF Oupu Por Timings Symbol Parameer Condiions Min Typ Max Unis Figure Noes T SPCYC S/PDIF Cycle Time C L = 10 pf 1.0 UI F SPDIF S/PDIF Frequency 4 24 MHz Figure 5.7 3 T SPDUTY S/PDIF Duy Cycle C L = 10 pf 90% 110% UI 2, 5 T MCLKCYC MCLK Cycle Time C L = 10 pf 20 250 ns F MCLK MCLK Frequency C L = 10 pf 4 50 MHz Figure 5.8 1, 2, 4 T MCLKDUTY MCLK Duy Cycle C L = 10 pf 40% 60% T MCLKCYC 2, 4 T AUDDLY Audio Pipeline Delay 40 80 µs Noes: 1. Guaraneed by design. 2. Proporional o uni ime (UI), according o sample rae. 3. S/PDIF is no a rue clock, bu is generaed from he inernal 128Fs clock, for Fs from 128 o 512 khz. 4. MCLK refers o MCLKOUT. 5. Inrinsic jier on S/PDIF oupu can limi is use as an S/PDIF ransmier. The S/PDIF inrinsic jier is approximaely 0.1 UI. Audio Crysal Timings Symbol Parameer Condiions Min Typ Max Unis Figure F XTAL Exernal Crysal Freq. 26 27 28.5 MHz Figure 4.2 1 1, 2 1, 2, 4 3.3 V 3 XTALVCC 5 XTALIN 18 pf 27 MHz 1 M 4 XTALOUT SiI9127A/ SiI1127A 18 pf Figure 4.2. Audio Crysal Schemaic SiI-DS-1059-D 25

Miscellaneous Timings Symbol Parameer Condiions Min Typ Max Unis Figure Noes T I2CDVD SDA Daa Valid delay from SCL falling edge C L = 400 pf 700 ns F DDC Speed on TMDS DDC Pors C L = 400 pf 100 khz 2 F I 2 C Speed on Local I 2 C Por C L = 400 pf 400 khz 3 T RESET RESET# Signal LOW Time for id rese 50 µs Figure 5.3 T STARTUP Sarup ime from power supplies id 100 ms 5 T BKSVINIT HDCP BKSV Load Time 2.2 ms 4 Noes: 1. Under normal operaing condiions unless oherwise specified, including oupu pin loading of C L = 10 pf. 2. DDC pors are limied o 100 khz by he HDMI Specificaion, and mee I 2 C sandard mode imings. 3. Local I 2 C por (CSCL/CSDA) mees sandard mode I 2 C iming requiremens o 400 khz. 4. The ime required o load he KSV ues inernal o he receiver afer a RESET# and he sar of an acive TMDS clock. An aached HDCP hos device should no aemp o read he receiver BKSV ues unil afer his ime. The T BKSVINIT Min and Max ues are based on he maximum and minimum allowable XCLK frequencies. The loading of he BKSV ues requires a id XCLK and TMDS clock. 5. T STARTUP is he sarup ime required for he device o be operaional once power is sable. This sarup ime is due o he onboard volage regulaor for he EDID and CEC and a power-on rese circui. Inerrup Timings Inerrup Oupu Pin Timings Symbol Parameer Condiions Min Typ Max Unis Figure Noes T FSC Link disabled (DE inacive) o SCDT LOW 0.15 40 ms Figure 4.3 1, 2, 3, 8 T HSC Link enabled (DE acive) o SCDT HIGH 4 DE Figure 4.3 1, 2, 4, 8 T CICD RXC inacive o CKDT LOW 100 µs Figure 4.3 1, 2, 8 T CACD RXC acive o CKDT HIGH 10 µs Figure 4.3 1, 2, 8 T INT Response Time for INT from Inpu Change 100 µs 1, 5, 8 T CIOD RXC inacive o ODCK inacive 100 ns 1, 8 T CAOD RXC acive o ODCK acive and sable 10 ms 1, 6, 8 T SRRF Delay from SCDT rising edge o Sofware Rese falling edge 100 ms Figure 5.3 7 Noes: 1. Guaraneed by design. 2. SCDT and CKDT are regiser bis in his device. 3. SCDT changes o LOW afer DE is HIGH for approximaely 4096 pixel clock cycles, or afer DE is LOW for approximaely 1,000,000 clock cycles. A 27 MHz pixel clock, his delay for DE HIGH is approximaely 150 µs, and he delay for DE LOW is approximaely 40 ms. 4. SCDT changes o HIGH when clock is acive (T CACD) and a leas 4 DE edges have been recognized. A 720p, he DE period is 22 µs, so SCDT responds approximaely 50 µs afer T CACD. 5. The INT pin changes sae afer a change in inpu condiion when he corresponding inerrup is enabled. 6. Oupu clock (ODCK) becomes acive before i becomes sable. Use he SCDT signal as an indicaor of sable video oupu imings, as his depends on decoding of DE signals wih acive RXC (see T FSC). 7. Sofware rese mus be assered and hen de-assered wihin he specified maximum ime afer rising edge of Sync Deec (SCDT). Access o boh SWRST and SCDT can be limied by he speed of he I 2 C connecion. 8. SCDT is HIGH only when CKDT is also HIGH. When he receiver is in a powered-down mode, he INT oupu pin indicaes he curren sae of SCDT. Thus, a powered-down receiver signals a microconroller conneced o he INT pin whenever SCDT changes from LOW o HIGH or HIGH o LOW. 26 SiI-DS-1059-D

RXC link clock acive link clock inacive link clock acive CKDT T CICD T CACD DE Do no Care T FSC T HSC SCDT Figure 4.3. SCDT and CKDT Timing from DE or RXC Inacive/Acive Noes: 1. The SCDT shown in Figure 4.3 is a regiser bi. SCDT remains HIGH if DE is suck in LOW while RXC remains acive, bu SCDT changes o LOW if DE is suck HIGH while RXC remains acive. 2. The CKDT shown in Figure 4.3 is a regiser bi. CKDT changes o LOW whenever RXC sops, and changes o HIGH when RXC sars. SCDT changes o LOW when CKDT changes o LOW. 3. SCDT changes o LOW when CKDT changes o LOW. SCDT changes o HIGH a T HSC afer CKDT changes o HIGH. 4. The INT oupu pin changes sae afer he SCDT or CKDT regiser bi is se or cleared if hose inerrups are enabled. Refer o he SiI-PR-1033 Programmer Reference for more deails on conrolling iming modes. The Programmer s Reference requires an NDA wih Laice Semiconducor. SiI-DS-1059-D 27

5. Timing Diagrams TMDS Inpu Timing Diagrams RX0 RX1 RX2 T CCS V DIFF = 0V Figure 5.1. TMDS Channel-o-Channel Skew Timing Power Supply Conrol Timings Power Supply Sequencing Power On Sequence Power Off Sequence IOVCC33 AVCC33 XTALVCC33 maximum 3.3 V excursion minimum 3.3 V excursion DIFF33 max DIFF3312 max IOVCC33 AVCC33 XTALVCC33 minimum 3.3 V excursion maximum 3.3 V excursion DIFF33 max AVCC12 CVCC12 AVPCC12 maximum 1.2 V excursion minimum 1.2 V excursion DIFF12 max AVCC12 CVCC12 AVPCC12 To ensure proper power-on rese, 5 V should be provided o he SBVCC5 pin before he power-on sequence shown here begins. minimum 1.2 V excursion Figure 5.2. Power Supply Sequencing maximum 1.2 V excursion DIFF3312 max DIFF12 max 28 SiI-DS-1059-D

Rese Timings VCC max VCC min RESET# TRESET VCC RESET# TRESET Noe ha VCC mus be sable beween is limis for Normal Operaing Condiions for TRESET before RESET# is HIGH. RESET# mus be pulled LOW for TRESET before accessing regisers. This can be done by holding RESET# LOW unil TRESET afer sable power (a lef), or by pulling RESET# LOW from a HIGH sae (a righ) for a leas TRESET. Figure 5.3. RESET# Minimum Timings Digial Video Oupu Timing Diagrams Oupu Transiion Times 2.0 V 2.0 V 0.8 V 0.8 V D LHT D HLT Figure 5.4. Video Digial Oupu Transiion Times SiI-DS-1059-D 29

Oupu Clock o Oupu Daa Delay T CYC T H T L OCLKINV = 0 ODCK OCLKINV = 1 ODCK T CKO(max) T CKO(min) Q[35:0] T CKO(max) T CKO(min) DE HSYNC VSYNC Figure 5.5. Receiver Clock-o-Oupu Delay and Duy Cycle Limis Digial Audio Oupu Timings T TR T SCKDUTY SCK T SCK2SD_MAX T SU T HD T SCK2SD_MIN WS SD Daa Valid Daa Valid Daa Valid Figure 5.6. I 2 S Oupu Timings 30 SiI-DS-1059-D

T SPCYC T SPDUTY 50% SPDIF Figure 5.7. S/PDIF Oupu Timings T MCLKCYC MCLK 50% 50% T MCLKDUTY Figure 5.8. MCLK Timings SiI-DS-1059-D 31

Calculaing Seup and Hold Times for Video Bus 24/30/36-Bi Mode Oupu daa is clocked ou on one rising or falling edge of ODCK, and is hen capured downsream using he same polariy ODCK edge one clock period laer. The seup ime of daa o ODCK and hold ime of ODCK o daa are herefore a funcion of he wors case ODCK o oupu delay, as shown in Figure 5.9. The acive rising ODCK edge is shown wih an arrowhead. For OCK_INV = 1, reverse he logic. T CK2OUT {max} T SU T HD T CK2OUT {min} ODCK Longes Clk-o-Ou Shores Clk-o-Ou Q DE VSYNC HSYNC Daa Valid Daa Valid Figure 5.9. 24/30/36-Bi Mode Receiver Oupu Seup and Hold Times Table 5.1 shows minimum calculaed seup and hold imes for commonly used ODCK frequencies. The seup and hold imes apply o DE, VSYNC, HSYNC, and Daa oupu pins, wih an oupu load of 10 pf. These are approximaions. Hold ime is no relaed o ODCK frequency. Table 5.1. Calculaion of 24/30/36-Bi Oupu Seup and Hold Times Mode Symbol Parameer T ODCK Min 24/30/36- Bi Mode T SU Seup Time o ODCK = T ODCK T CK2OUT{max} 27 MHz 37.0 ns 34.5 ns 74.25 MHz 13.5 ns 11.0 ns T HD Hold Time from ODCK = T CK2OUT{min} 27 MHz 37.0 ns 0.4 ns 32 SiI-DS-1059-D

12/15/18-Bi Dual-Edge Mode Oupu daa is clocked ou on boh he rising and falling edges of ODCK, and is hen capured downsream using he opposie ODCK edge. This is shown in Figure 5.10. The seup ime of daa o ODCK is a funcion of he shores duy cycle and he longes ODCK o oupu delay. The hold ime does no depend on duy cycle since every edge is used, and is a funcion only of he shores ODCK o oupu delay. T SU T HD ODCK T DUTY {min} T CK2OUT {max} T CK2OUT {min} Q DE VSYNC HSYNC Daa Valid Daa Valid Figure 5.10. 12/15/18-Bi Mode Receiver Oupu Seup and Hold Times Table 5.2 shows minimum calculaed seup and hold imes for commonly used ODCK frequencies, up o he maximum allowed for 12/15/18-bi mode. The seup and hold imes apply o DE, VSYNC, HSYNC, and Daa oupu pins, wih oupu load of 10 pf. These are approximaions. Hold ime is no relaed o ODCK frequency. Table 5.2. Calculaion of 12/15/18-Bi Oupu Seup and Hold Times Mode Symbol Parameer T ODCK Min 12/15/18- Bi Mode T SU Seup Time o ODCK = T ODCK T DUTY{min} T CK2OUT{max} 27 MHz 37.0 ns 11 ns 74.25 MHz 13.5 ns 1.6 ns T HD Hold Time from ODCK = T CK2OUT{min} 27 MHz 37.0 ns 0.4 ns SiI-DS-1059-D 33

Calculaing Seup and Hold Times for I 2 S Audio Bus Valid serial daa is available a Tsck2sd afer he falling edge of he firs SCK cycle, and hen capured downsream using he acive rising edge of SCK one clock period laer. The seup ime of daa o SCK (TSU) and hold ime of SCK o daa (THD) are herefore a funcion of he wors case SCK-o-oupu daa delay (Tsck2sd). Figure 5.6 illusraes his iming relaionship. The acive SCK edge (rising edge) is shown wih an arrowhead. For a falling edge sampling clock, he logic is reversed. Table 5.3 shows he seup and hold ime calculaion examples for various audio sample frequencies. The formula used in hese examples also applies when calculaing he seup and hold imes for oher audio sampling frequencies. Table 5.3. I 2 S Seup and Hold Time Calculaions Symbol Parameer FWS (khz) FSCLK (MHz) Tr Min T SU T HD Seup Time, SCK o SD/WS = T TR ( T SCKDUTY_WORST + T SCK2SD_MAX ) = T TR (0.6T TR + 5 ns ) = 0.4T TR 5 ns Hold Time, SCK o SD/WS = ( T SCKDUTY_WORST T SCK2SD_MIN ) = 0.4T TR 5 ns Noe: The sample calculaions shown are based on WS = 64 SCLK rising edges. 32 khz 2.048 488 ns 190 ns 44.1 khz 2.822 354 ns 136 ns 48 khz 3.072 326 ns 125 ns 96 khz 6.144 163 ns 60 ns 192 khz 12.288 81 ns 27 ns 32 khz 2.048 488 ns 190 ns 44.1 khz 2.822 354 ns 136 ns 48 khz 3.072 326 ns 125 ns 96 khz 6.144 163 ns 60 ns 192 khz 12.288 81 ns 27 ns 34 SiI-DS-1059-D

6. Pin Diagram and Descripions Pin Diagram Figure 6.1 shows he pin connecions for he SiI9127A/SiI1127A receiver in he 128-pin TQFP package. Individual pin funcions are described in he Pin Descripions secion on he nex page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SiI9127A/SiI1127A (Top View) 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 GPIO3/MUTEOUT SPDIF MCLK RSVDNC RSVDNC RSVDNC SD0 SCK WS IOVCC33 CVCC12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 IOVCC33 CVCC12 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 ODCK 33 34 35 36 37 38 39 40 41 42 43 44 53 54 55 56 57 58 59 60 61 62 63 64 RSVDNC AVCC33 NC NC NC NC NC AVCC12 R2X2+ R2X1+ R2X0+ R2XC+ AVCC33 R1X2+ R1X1+ R1X0+ R1XC+ R2X2- R2X1- R2X0- R2XC- R1X2- R1X1- R1X0- R1XC- AVCC12 NC NC NC NC NC AVCC33 APVCC12 XTALVCC33 XTALOUT XTALIN XTALGND IOVCC33 CVCC12 RSVDNC RSVDL RSVDL GPIO0/XCLKOUT GPIO1/SCDT GPIO2/EVNODD GPIO4 GPIO5 GPIO6 GPIO7 RSVDNC RSVDNC RSVDNC RESET# INT CSCL CSDA C12CA CEC_A CEC_D SBVCC5 R1PWR5V HPD1 DSCL1 DSDA1 R2PWR5V HPD2 DSCL2 DSDA2 RSVDNC RSVDNC GND Q35 Q34 Q33 Q32 Q31 Q30 Q29 Q28 Q27 CVCC12 IOVCC33 Q26 Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 DE VSYNC HSYNC CVCC12 IOVCC33 45 46 47 48 49 50 51 52 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 Figure 6.1. Pin Diagram SiI-DS-1059-D 35

Pin Descripions Digial Video Oupu Daa Pins Pin Name Pin Type Dir Descripion Q0 85 LVTTL Q1 84 2 ma o 14 ma Q2 83 Q3 82 Q4 81 Q5 80 Q6 79 Q7 78 Q8 77 Q9 74 Q10 73 Q11 72 Q12 71 Q13 70 Q14 69 Q15 68 Q16 67 Q17 66 Q18 59 Q19 58 Q20 57 Q21 56 Q22 55 Q23 54 Q24 53 Q25 52 Q26 51 Q27 48 Q28 47 Q29 46 Q30 45 Q31 44 Q32 43 Q33 42 Q34 41 Q35 40 Oupu 36-Bi Oupu Pixel Daa Bus. Q[35:0] is highly configurable using he various video configuraion regisers. I suppors a wide array of oupu formas, including muliple RGB and YCbCr bus formas. Using he appropriae bis in he PD_SYS2 regiser, he oupu drivers can be pu ino a high impedance sae. Noes: 1. When ransporing video daa ha uses fewer han 36 bis, he unused bis on he Q[] bus can sill carry swiching pixel daa signals. Unused Q[35:0] bus pins should be unconneced, masked, or ignored by downsream devices. For example, carrying YCbCr 4:2:2 daa wih 16-bi widh (see page 47), he bis Q[0] hrough Q[7] oupu swiching signals. 2. The oupu daa bus, Q[35:0], can be wire-ored o anoher device so one device is always in high impedance sae. However, hese pins do no have inernal pull-up or pull-down resisors, and so canno pull he bus HIGH or LOW when all conneced devices are in he high-impedance sae. 3. The drive srengh of Q[0:35] can be programmed in 2 ma seps beween 2 ma and 14 ma. 36 SiI-DS-1059-D

Digial Video Oupu Conrol Pins Pin Name Pin Type Dir Descripion DE 60 HSYNC 62 VSYNC 61 GPIO2/ EVNODD GPIO2/ EVNODD 13 ODCK 65 LVTTL 2 ma o 14 ma LVTTL 2 ma o 14 ma LVTTL 2 ma o 14 ma LVTTL 8 ma LVTTL 2 ma o 14 ma Oupu Oupu Oupu Inpu Oupu Oupu Oupu Daa Enable. Horizonal Sync Oupu. Verical Sync Oupu. Programmable GPIO2. Indicaes Even or Odd Field for Inerlaced Formas. Oupu Daa Clock. Noes: 1. HSYNC and VSYNC oupus carry sync signals for boh embedded and separae sync configuraions. 2. The drive srengh of DE, HSYNC, VSYNC, and ODCK can be programmed in 2 ma seps beween 2 ma and 14 ma. Digial Audio Oupu Pins Pin Name Pin Type Dir Descripion XTALIN 4 XTALOUT 3 GPIO0/ XCLKOUT GPIO0/ XCLKOUT 11 MCLK 94 SCK 89 WS 88 SD0 90 SPDIF 95 GPIO3/ MUTEOUT GPIO3/ MUTEOUT 96 5 V oleran LVTTL LVTTL 4 ma LVTTL 4 ma LVTTL 8 ma LVTTL 4 ma LVTTL 4 ma LVTTL 4 ma LVTTL 4 ma LVTTL 4 ma Inpu Oupu Inpu Oupu Oupu Oupu Oupu Oupu Oupu Oupu Inpu Oupu Oupu Crysal Clock Inpu. Also allows LVTTL inpu. Frequency required: 26 28.5 MHz. Crysal Clock Oupu. Programmable GPIO0. Addiional Clock Oupu from crysal oscillaor circui. Audio Maser Clock Oupu. I 2 S Serial Clock Oupu. I 2 S Word Selec Oupu. I 2 S Serial Daa Oupu. S/PDIF Audio Oupu. Programmable GPIO3. Mue Audio Oupu. Signal o he exernal downsream audio device, audio DAC, ec. o mue audio oupu. Noe: The XTALIN pin can eiher be driven a LVTTL levels by a clock (leaving XTALOUT unconneced), or conneced hrough a crysal o XTALOUT. Refer o he schemaic on page 68. SiI-DS-1059-D 37

Configuraion/Programming Pins Pin Name Pin Type Dir Descripion INT 22 RESET# 21 CSCL 23 CSDA 24 CI2CA 25 GPIO1/SCDT GPIO1/SCDT 13 GPIO4 14 GPIO5 15 GPIO6 16 GPIO7 17 LVTTL 4 ma Schmi 5 V oleran Schmi 5 V oleran Schmi 5 V oleran 3 ma LVTTL 5 V oleran LVTTL 4 ma LVTTL 4 ma LVTTL 4 ma LVTTL 4 ma LVTTL 4 ma Oupu Inpu Inpu Inpu Oupu Inpu Oupu Inpu Oupu Inpu Oupu Inpu Oupu Inpu Oupu Inerrup Oupu. Configurable polariy and push-pull oupu. Muliple sources of inerrup can be enabled hrough he INT_EN regiser. See noe below. Rese Pin. Acive LOW. Configuraion/Saus I 2 C Clock. Chip configuraion/saus, CEA-861 suppor and downsream HDCP regisers are accessed via his I 2 C por. True open drain, so does no pull o GND if power is no applied. Configuraion/Saus I 2 C Daa. Chip configuraion/saus, CEA-861 suppor and downsream HDCP regisers are accessed via his I 2 C por. True open drain, so does no pull o GND if power is no applied. Local I 2 C Address Selec. LOW = Addresses 0x60/0x68 HIGH = Addresses 0x62/0x6A Programmable GPIO1. Sync Deecion Indicaor. Indicaes Acive Video a HDMI Inpu Por. Programmable GPIO4. Programmable GPIO5. Programmable GPIO6. Programmable GPIO7. Noe: The INT pin can be programmed o be eiher a push-pull LVTTL oupu or an open-drain oupu. HDMI Conrol Signal Pins Pin Name Pin Type Dir Descripion DSCL1 DSCL2 DSDA1 DSDA2 HPD1 HPD2 R1PWR5V R2PWR5V 31 35 32 36 30 34 29 33 CEC_A 26 CEC_D 27 Schmi Open drain 5 V oleran Schmi Open drain 5 V oleran 3 ma LVTTL 4 ma LVTTL 5 V oleran CEC complian 5 V oleran Schmi 5 V oleran Inpu Inpu Oupu Oupu Inpu Inpu Oupu Inpu Oupu DDC I 2 C Clock for respecive por. HDCP KSV, An and Ri ues are exchanged over an I 2 C por during auhenicaion. True open drain, so does no pull o GND if power is no applied. DDC I 2 C Daa for respecive por. HDCP KSV, An and Ri ues are exchanged over an I 2 C por during auhenicaion. True open drain, so does no pull o GND if power is no applied. Ho plug oupu signal o HDMI connecor for respecive por. Indicaes EDID is readable. 5 V power and por deecion inpu for respecive por. Used o power inernal EDID when device is no powered. These pins require a 10 F capacior o ground. HDMI complian CEC I/O used o inerface o CEC devices. This pin connecs o he CEC signal of all HDMI connecors in he sysem. This pin has an inernal pull-up resisor. CEC inerface o local sysem. True open-drain. An exernal pull-up is required. This pin ypically connecs o he local CPU. 38 SiI-DS-1059-D

TMDS Differenial Signal Pins Pin Name Pin Type Dir Descripion R1X0+ R1X0 R1X1+ R1X1 R1X2+ R1X2 R1XC+ R1XC R2X0+ R2X0 R2X1+ R2X1 R2X2+ R2X2 R2XC+ R2XC 107 106 109 108 111 110 105 104 116 115 118 117 120 119 114 113 TMDS analog Inpu Por 1 TMDS inpu daa pairs. TMDS analog Inpu Por 1 TMDS inpu clock pair. TMDS analog Inpu Por 2 TMDS inpu daa pairs. TMDS analog Inpu Por 2 TMDS inpu clock pair. Power and Ground Pins Pin Name Pin Type Descripion Supply CVCC12 7, 49, 63, 75, 86 Power Digial Logic VCC. 1.2 V IOVCC33 6, 50, 64, 76, 87 Power Inpu/Oupu Pin VCC. 3.3 V AVCC33 97, 112, 127 Power TMDS Analog VCC 3.3 V. 3.3 V AVCC12 103, 121 Power TMDS Analog VCC 1.2 V. 1.2 V APVCC12 1 Power XTALVCC33 2 Power Audio Clock Regeneraion PLL Analog VCC. Mus be conneced o 1.2 V. Audio Clock Regeneraion PLL crysal oscillaor power. Mus be conneced o 3.3 V. XTALGND 5 Ground Audio Clock Regeneraion ground. Ground SBVCC5 28 Power Sandby power supply. All oher supplies can be off wih SBVCC5 on. This pin requires a 10 F capacior o ground. GND 39, epad (boom of package) Ground Ground. The epad mus be soldered o ground. Ground 1.2 V 3.3 V 5 V Reserved and No Conneced Pins Pin Name Pin Type Descripion Supply RSVDNC 8, 18 20, 37, 38, 91, 92, 93, 128 Reserved Reserved, mus be lef unconneced. No connecion RSVDL 9, 10 Reserved Reserved, mus be ied o ground. Ground NC 98 102, 122 126 No conneced Mus be lef unconneced. No connecion SiI-DS-1059-D 39

7. Video Pah The SiI9127A/SiI1127A receiver acceps all id HDMI inpu formas and can ransform ha video in a variey of ways o produce he proper video oupu forma. The following pages describe how o conrol he video pah formaing and how o assign oupu pins for each video oupu forma. The processing blocks in Figure 7.1 correspond o hose shown in Figure 7.2 hrough Figure 7.4. MCLK SPDIF Audio Processing I2S Oupus SCK TMDS HDCP WS Widen o 14-Bis InfoFrame Packe Processing SD[3:0] DSD Oupus DCLK RGB o YCbCr YCbCr Range Reduce Down Sample 4:4:4 o 4:2:2 Noe: DSD oupus are shared wih SPDIF and I2S signals DR[3:0] DL[3:0] bypass bypass bypass Upsample 4:2:2 o 4:4:4 xvycc/ycbcr o RGB RGB Range Expand Diher Module Mux 656 Video Timing DE HSYNC bypass bypass bypass VSYNC ODCK Noe: HDCP decoding does no apply o he SiI1127A receiver. Q[35:0] Figure 7.1. Receiver Video and Audio Daa Processing Pahs 40 SiI-DS-1059-D

HDMI Inpu Modes o SiI9127A/SiI1127A Oupu Modes The HDMI link suppors ranspor of video in any of he hree modes; RGB 4:4:4, YCbCr/xvYCC 4:4:4, or YCbCr/xvYCC 4:2:2. The flexible video pah in he SiI9127A/SiI1127A receiver allows reformaing of video daa o a se of oupu modes. Table 7.1 liss he suppored ransformaions and poins o he figure for each. In every case, he HDMI link iself carries separae syncs. Table 7.1. Translaing HDMI Formas o Oupu Formas HDMI Inpu Mode RGB 4:4:4 Separae Sync YCbCr 4:4:4 Separae Sync YCbCr 4:2:2 Separae Sync Digial Oupu Forma YCbCr 4:2:2 Embedded Sync YC Mux Separae Sync YC Mux Embedded Sync RGB 4:4:4 Figure 7.2A Figure 7.2B Figure 7.2C Figure 7.2D Figure 7.2E Figure 7.2F YCbCr/xvYCC 4:4:4 Figure 7.3A Figure 7.3B Figure 7.3C Figure 7.3D Figure 7.3E Figure 7.3F YCbCr/xvYCC 4:2:2 Figure 7.4A Figure 7.4B Figure 7.4C Figure 7.4D Figure 7.4E Figure 7.4F HDMI RGB 4:4:4 Inpu Processing RGB 4:4:4 TMDS and HDCP Decoding RGB 4:4:4 Digial Ou A RGB 4:4:4 TMDS and HDCP Decoding RGBoYCbCr Color Range Scaling YCbCr 4:4:4 Separae Syncs Digial Ou B RGB 4:4:4 TMDS and HDCP Decoding RGBoYCbCr Color Range Scaling DownSampling YCbCr 4:2:2 Separae Syncs Digial Ou C RGB 4:4:4 TMDS and HDCP Decoding RGBoYCbCr Color Range Scaling DownSampling Embedded Syncs YCbCr 4:2:2 Emb. Syncs Digial Ou D RGB 4:4:4 TMDS and HDCP Decoding RGBoYCbCr Color Range Scaling MUX YC 4:2:2 Separae Syncs Digial Ou DownSampling MUX YC E RGB 4:4:4 TMDS and HDCP Decoding RGBoYCbCr Color Range Scaling Down Sampling Embedded Syncs MUX YC MUX YC 4:2:2 Emb. Syncs Digial Ou F Noe: HDCP decoding does no apply o he SiI1127A receiver. Figure 7.2. HDMI RGB 4:4:4 Inpu o Video Oupu Transformaions SiI-DS-1059-D 41

HDMI YCbCr/xvYCC 4:4:4 Inpu Processing YCbCr/xvYCC 4:4:4 TMDS and HDCP Decoding YCbCr/xvYCC o RGB RGB 4:4:4 Digial Ou A YCbCr/xvYCC 4:4:4 TMDS and HDCP Decoding YCbCr 4:4:4 Digial Ou B YCbCr/xvYCC 4:4:4 TMDS and HDCP Decoding DownSampling YCbCr 4:2:2 Digial Ou C YCbCr/xvYCC 4:4:4 TMDS and HDCP Decoding YCbCr 4:2:2 Emb. Syncs Digial Ou Embedded DownSampling Syncs D YCbCr/xvYCC 4:4:4 TMDS and HDCP Decoding DownSampling MUX YC 4:2:2 Digial Ou MUX YC E YCbCr/xvYCC 4:4:4 TMDS and HDCP Decoding Embedded DownSampling MUX YC Syncs F MUX YC 4:2:2 Emb. Syncs Digial Ou Noe: HDCP decoding does no apply o he SiI1127A receiver. Figure 7.3. HDMI YCbCr/xvYCC 4:4:4 Inpu o Video Oupu Transformaions 42 SiI-DS-1059-D

HDMI YCbCr/xvYCC 4:2:2 Inpu Processing YCbCr/xvYCC 4:2:2 TMDS and HDCP Decoding YCbCr/xvYCC Upsampling o RGB A RGB 4:4:4 Digial Ou YCbCr/xvYCC 4:2:2 TMDS and HDCP Decoding UpSampling YCbCr 4:4:4 Digial Ou B YCbCr/xvYCC 4:2:2 TMDS and HDCP Decoding YCbCr 4:2:2 Digial Ou C YCbCr/xvYCC 4:2:2 TMDS and HDCP Decoding Embedded Syncs YCbCr 4:2:2 Emb. Syncs Digial Ou D YCbCr/xvYCC 4:2:2 TMDS and HDCP Decoding MUX YC 4:2:2 Digial Ou MUX YC E YCbCr/xvYCC 4:2:2 TMDS and HDCP Decoding Embedded Syncs MUX YC 4:2:2 Emb. Syncs Digial Ou MUX YC F Noe: HDCP decoding does no apply o he SiI1127A receiver. Figure 7.4. HDMI YCbCr/xvYCC 4:2:2 Inpu o Video Oupu Transformaions SiI-DS-1059-D 43

SiI9127A/SiI1127A Oupu Mode Configuraion The SiI9127A/SiI1127A receiver suppors muliple oupu daa mappings. Some have separae conrol signals while ohers have embedded conrol signals. The selecion of daa mapping mode should be consisen a boh he pins and in he corresponding regiser seings. Refer o he SiI-PR-1033 Programmer Reference for more deails. Table 7.2. Oupu Video Formas Oupu Mode Daa Widhs Pixel Replicaion Syncs Page Noes RGB 4:4:4 24, 30, 36 1x Separae 45 3, 7 YCbCr 4:4:4 24, 30, 36 1x Separae 45 1, 3, 7 YC 4:2:2 Sep. Syncs 16, 20, 24 1x Separae 47 2, 3 YC 4:2:2 Sep. Syncs 16, 20, 24 2x Separae 47 2, 3, 8 YC 4:2:2 Emb. Syncs 16, 20, 24 1x Embedded 50 2, 5 YC MUX 4:2:2 8, 10, 12 2x Separae 53 2, 4, 8, 9 YC MUX 4:2:2 Emb. Syncs 8, 10, 12 2x Embedded 55 2, 5, 6, 8, 9 Noes: 1. YC 4:4:4 daa conains one Cr, one Cb and one Y ue for every pixel. 2. YC 4:2:2 daa conains one Cr and one Cb ue for every wo pixels; and one Y ue for every pixel. 3. These formas can be carried across he HDMI link. Refer o he HDMI Specificaion, Secion 6.2.3. The link clock mus be wihin he specified range of he receiver. 4. In YC MUX mode daa is sen o one or wo 8/10/12-bi channels. 5. YC MUX wih embedded SAV/EAV signal. 6. Syncs are embedded using SAV/EAV codes. 7. A 2x clock can also be sen wih 4:4:4 daa. 8. When sending a 2x clock he HDMI source mus also send AVI InfoFrames wih an accurae pixel replicaion field. Refer o he HDMI Specificaion, Secion 6.4. 9. 2x clocking does no suppor YC 4:2:2 MUX imings for resoluions greaer han 720p or 1080i, because he oupu clock frequency would exceed he range allowed for he receiver. The SiI9127A/SiI1127A receiver can oupu video in various formas on is parallel digial oupu bus. Some ransformaion of he daa received over HDMI is necessary in some modes. Digial oupu is used wih eiher 4:4:4 or 4:2:2 daa. The diagrams do no show separaion of he audio and InfoFrame packes from he HDMI sream, which occurs immediaely afer he TMDS and opional HDCP decoding. The HDMI link always carries separae HSYNC and VSYNC and DE. Therefore he SAV/EAV sync encoder mus be used whenever he oupu mode includes embedded sync. The iming diagrams in Figure 7.5 hrough Figure 7.9 show only a represenaion of he DE, HSYNC, and VSYNC imings. These imings are specific o he video resoluion, as defined by EIA/CEA-861B and oher specs. The number of pixels shown per DE HIGH ime is represenaive, o show he daa formaing. 44 SiI-DS-1059-D

RGB and YCbCr 4:4:4 Formas wih Separae Syncs The pixel clock runs a he pixel rae, and a complee definiion of each pixel is oupu on each clock. Figure 7.5 shows RGB daa. The same iming forma is used for YCbCr 4:4:4 as lised in Table 7.3. Figure 7.5 shows imings wih OCLKDIV = 0 and OCKINV = 1. Table 7.3. 4:4:4 Mappings Pin Name 36-bi 30-bi 24-bi RGB YCbCr RGB YCbCr RGB YCbCr Q0 B0 Cb0 NC NC NC NC Q1 B1 Cb1 NC NC NC NC Q2 B2 Cb2 B0 Cb0 NC NC Q3 B3 Cb3 B1 Cb1 NC NC Q4 B4 Cb4 B2 Cb2 B0 Cb0 Q5 B5 Cb5 B3 Cb3 B1 Cb1 Q6 B6 Cb6 B4 Cb4 B2 Cb2 Q7 B7 Cb7 B5 Cb5 B3 Cb3 Q8 B8 Cb8 B6 Cb6 B4 Cb4 Q9 B9 Cb9 B7 Cb7 B5 Cb5 Q10 B10 Cb10 B8 Cb8 B6 Cb6 Q11 B11 Cb11 B9 Cb9 B7 Cb7 Q12 G0 Y0 NC NC NC NC Q13 G1 Y1 NC NC NC NC Q14 G2 Y2 G0 Y0 NC NC Q15 G3 Y3 G1 Y1 NC NC Q16 G4 Y4 G2 Y2 G0 Y0 Q17 G5 Y5 G3 Y3 G1 Y1 Q18 G6 Y6 G4 Y4 G2 Y2 Q19 G7 Y7 G5 Y5 G3 Y3 Q20 G8 Y8 G6 Y6 G4 Y4 Q21 G9 Y9 G7 Y7 G5 Y5 Q22 G10 Y10 G8 Y8 G6 Y6 Q23 G11 Y11 G9 Y9 G7 Y7 Q24 R0 Cr0 NC NC NC NC Q25 R1 Cr1 NC NC NC NC Q26 R2 Cr2 R0 Cr0 NC NC Q27 R3 Cr3 R1 Cr1 NC NC Q28 R4 Cr4 R2 Cr2 R0 Cr0 Q29 R5 Cr5 R3 Cr3 R1 Cr1 Q30 R6 Cr6 R4 Cr4 R2 Cr2 Q31 R7 Cr7 R5 Cr5 R3 Cr3 Q32 R8 Cr8 R6 Cr6 R4 Cr4 Q33 R9 Cr9 R7 Cr7 R5 Cr5 Q34 R10 Cr10 R8 Cr8 R6 Cr6 Q35 R11 Cr11 R9 Cr9 R7 Cr7 HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC DE DE DE DE DE DE DE SiI-DS-1059-D 45

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel n blank blank blank Q[35:24] R0 R1 R2 R3 R4 Rn Q[23:12] G0 G1 G2 G3 G4 Gn Q[11:0] B0 B1 B2 B3 B4 Bn ODCK DE HSYNC, VSYNC Figure 7.5. 4:4:4 Timing Diagram Noe: The daa is defined in various specificaions o specific ues. These ues are conrolled by seing he appropriae SiI9127A/SiI1127A regisers, because no pixel daa is carried on HDMI during blanking. 46 SiI-DS-1059-D

YC 4:2:2 Formas wih Separae Syncs The YC 4:2:2 formas oupu one pixel for every pixel clock period. A luminance (Y) ue is sen for every pixel, bu he chrominance ues Cb and Cr are sen over wo pixels. Pixel daa can be 24-bi, 20-bi or 16-bi. HSYNC and VSYNC are oupu separaely on heir own pins. The DE HIGH ime mus conain an even number of pixel clocks. Figure 7.6 shows imings wih OCLKDIV = 0 and OCKINV = 1. Table 7.4. YC 4:2:2 Separae Sync Pin Mappings Pin Name 16-bi YC 20-bi YC 24-bi YC Pixel #0 Pixel #1 Pixel #0 Pixel #1 Pixel #0 Pixel #1 Q0 NC NC NC NC NC NC Q1 NC NC NC NC NC NC Q2 NC NC NC NC NC NC Q3 NC NC NC NC NC NC Q4 NC NC NC NC NC NC Q5 NC NC NC NC NC NC Q6 NC NC NC NC NC NC Q7 NC NC NC NC NC NC Q8 NC NC NC NC NC NC Q9 NC NC NC NC NC NC Q10 NC NC NC NC NC NC Q11 NC NC NC NC NC NC Q12 NC NC NC NC Y0 Y0 Q13 NC NC NC NC Y1 Y1 Q14 NC NC Y0 Y0 Y2 Y2 Q15 NC NC Y1 Y1 Y3 Y3 Q16 Y0 Y0 Y2 Y2 Y4 Y4 Q17 Y1 Y1 Y3 Y3 Y5 Y5 Q18 Y2 Y2 Y4 Y4 Y6 Y6 Q19 Y3 Y3 Y5 Y5 Y7 Y7 Q20 Y4 Y4 Y6 Y6 Y8 Y8 Q21 Y5 Y5 Y7 Y7 Y9 Y9 Q22 Y6 Y6 Y8 Y8 Y10 Y10 Q23 Y7 Y7 Y9 Y9 Y11 Y11 Q24 NC NC NC NC Cb0 Cr0 Q25 NC NC NC NC Cb1 Cr1 Q26 NC NC Cb0 Cr0 Cb2 Cr2 Q27 NC NC Cb1 Cr1 Cb3 Cr3 Q28 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Q29 Cb1 Cr1 Cb3 Cr3 Cb5 Cr5 Q30 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Q31 Cb3 Cr3 Cb5 Cr5 Cb7 Cr7 Q32 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8 Q33 Cb5 Cr5 Cb7 Cr7 Cb9 Cr9 Q34 Cb6 Cr6 Cb8 Cr8 Cb10 Cr10 Q35 Cb7 Cr7 Cb9 Cr9 Cb11 Cr11 HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC DE DE DE DE DE DE DE SiI-DS-1059-D 47

Table 7.5. YC 4:2:2 (Pass Through Only) Separae Sync Pin Mapping Pin Name 16-bi YC 20-bi YC 24-bi YC Pixel #0 Pixel #1 Pixel #0 Pixel #1 Pixel #0 Pixel #1 Q0 NC NC NC NC NC NC Q1 NC NC NC NC NC NC Q2 NC NC NC NC NC NC Q3 NC NC NC NC NC NC Q4 NC NC NC NC Y0 Y0 Q5 NC NC NC NC Y1 Y1 Q6 NC NC Y0 Y0 Y2 Y2 Q7 NC NC Y1 Y1 Y3 Y3 Q8 NC NC NC NC Cb0 Cr0 Q9 NC NC NC NC Cb1 Cr1 Q10 NC NC Cb0 Cr0 Cb2 Cr2 Q11 NC NC Cb1 Cr1 Cb3 Cr3 Q12 NC NC NC NC NC NC Q13 NC NC NC NC NC NC Q14 NC NC NC NC NC NC Q15 NC NC NC NC NC NC Q16 Y0 Y0 Y2 Y2 Y4 Y4 Q17 Y1 Y1 Y3 Y3 Y5 Y5 Q18 Y2 Y2 Y4 Y4 Y6 Y6 Q19 Y3 Y3 Y5 Y5 Y7 Y7 Q20 Y4 Y4 Y6 Y6 Y8 Y8 Q21 Y5 Y5 Y7 Y7 Y9 Y9 Q22 Y6 Y6 Y8 Y8 Y10 Y10 Q23 Y7 Y7 Y9 Y9 Y11 Y11 Q24 NC NC NC NC NC NC Q25 NC NC NC NC NC NC Q26 NC NC NC NC NC NC Q27 NC NC NC NC NC NC Q28 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Q29 Cb1 Cr1 Cb3 Cr3 Cb5 Cr5 Q30 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Q31 Cb3 Cr3 Cb5 Cr5 Cb7 Cr7 Q32 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8 Q33 Cb5 Cr5 Cb7 Cr7 Cb9 Cr9 Q34 Cb6 Cr6 Cb8 Cr8 Cb10 Cr10 Q35 Cb7 Cr7 Cb9 Cr9 Cb11 Cr11 HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC DE DE DE DE DE DE DE Noe: This pin mapping is only id when he inpu video forma is YC 4:2:2 and he oupu video forma is YC 4:2:2 also. No video processing blocks should be enabled when his pin mapping is used. 48 SiI-DS-1059-D

blank Pixel0 Pixel1 Pixel2 Pixel3 Pixeln-1 Pixeln Q[35:28] Cb0[11:4] Cr0[11:4] Cb2[11:4] Cr2[11:4] Cbn-1[11:4] Crn-1[11:4] Q[23:16] Y0[11:4] Y1[11:4] Y2[11:4] Y3[11:4] Yn-1[11:4] Yn[11:4] Q[27:24] Cb0[3:0] Cr0[3:0] Cb2[3:0] Cr2[3:0] Cbn-1[3:0] Crn-1 [3:0] Q[15:12] Y0[3:0] Y1[3:0] Y2[3:0] Y3[3:0] Yn-1[3:0] Yn[3:0] ODCK DE HSYNC, VSYNC Figure 7.6. YC Timing Diagram Noe: The daa is defined in various specificaions o specific ues. These ues are conrolled by seing he appropriae SiI9127A/SiI1127A receiver regisers, because no pixel daa is carried on HDMI during blanking. SiI-DS-1059-D 49

YC 4:2:2 Formas wih Embedded Syncs The YC 4:2:2 embedded sync forma is idenical o he previous forma (YC 4:2:2), excep ha he syncs are embedded and no separae. Pixel daa can be 24-bi, 20-bi or 16-bi. DE is always oupu. Figure 7.7 shows he Sar of Acive Video (SAV) preamble, he End of Acive Video (EAV) suffix, and shows imings wih OCLKDIV = 0 and OCKINV = 1. Table 7.6. YC 4:2:2 Embedded Sync Pin Mappings Pin Name 16-bi YC 20-bi YC 24-bi YC Pixel #0 Pixel #1 Pixel #0 Pixel #1 Pixel #0 Pixel #1 Q0 NC NC NC NC NC NC Q1 NC NC NC NC NC NC Q2 NC NC NC NC NC NC Q3 NC NC NC NC NC NC Q4 NC NC NC NC NC NC Q5 NC NC NC NC NC NC Q6 NC NC NC NC NC NC Q7 NC NC NC NC NC NC Q8 NC NC NC NC NC NC Q9 NC NC NC NC NC NC Q10 NC NC NC NC NC NC Q11 NC NC NC NC NC NC Q12 NC NC NC NC Y0 Y0 Q13 NC NC NC NC Y1 Y1 Q14 NC NC Y0 Y0 Y2 Y2 Q15 NC NC Y1 Y1 Y3 Y3 Q16 Y0 Y0 Y2 Y2 Y4 Y4 Q17 Y1 Y1 Y3 Y3 Y5 Y5 Q18 Y2 Y2 Y4 Y4 Y6 Y6 Q19 Y3 Y3 Y5 Y5 Y7 Y7 Q20 Y4 Y4 Y6 Y6 Y8 Y8 Q21 Y5 Y5 Y7 Y7 Y9 Y9 Q22 Y6 Y6 Y8 Y8 Y10 Y10 Q23 Y7 Y7 Y9 Y9 Y11 Y11 Q24 NC NC NC NC Cb0 Cr0 Q25 NC NC NC NC Cb1 Cr1 Q26 NC NC Cb0 Cr0 Cb2 Cr2 Q27 NC NC Cb1 Cr1 Cb3 Cr3 Q28 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Q29 Cb1 Cr1 Cb3 Cr3 Cb5 Cr5 Q30 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Q31 Cb3 Cr3 Cb5 Cr5 Cb7 Cr7 Q32 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8 Q33 Cb5 Cr5 Cb7 Cr7 Cb9 Cr9 Q34 Cb6 Cr6 Cb8 Cr8 Cb10 Cr10 Q35 Cb7 Cr7 Cb9 Cr9 Cb11 Cr11 HSYNC Embedded Embedded Embedded Embedded Embedded Embedded VSYNC Embedded Embedded Embedded Embedded Embedded Embedded DE Embedded Embedded Embedded Embedded Embedded Embedded 50 SiI-DS-1059-D

Table 7.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping Pin Name 16-bi YC 20-bi YC 24-bi YC Pixel #0 Pixel #1 Pixel #0 Pixel #1 Pixel #0 Pixel #1 Q0 NC NC NC NC NC NC Q1 NC NC NC NC NC NC Q2 NC NC NC NC NC NC Q3 NC NC NC NC NC NC Q4 NC NC NC NC Y0 Y0 Q5 NC NC NC NC Y1 Y1 Q6 NC NC Y0 Y0 Y2 Y2 Q7 NC NC Y1 Y1 Y3 Y3 Q8 NC NC NC NC Cb0 Cr0 Q9 NC NC NC NC Cb1 Cr1 Q10 NC NC Cb0 Cr0 Cb2 Cr2 Q11 NC NC Cb1 Cr1 Cb3 Cr3 Q12 NC NC NC NC NC NC Q13 NC NC NC NC NC NC Q14 NC NC NC NC NC NC Q15 NC NC NC NC NC NC Q16 Y0 Y0 Y2 Y2 Y4 Y4 Q17 Y1 Y1 Y3 Y3 Y5 Y5 Q18 Y2 Y2 Y4 Y4 Y6 Y6 Q19 Y3 Y3 Y5 Y5 Y7 Y7 Q20 Y4 Y4 Y6 Y6 Y8 Y8 Q21 Y5 Y5 Y7 Y7 Y9 Y9 Q22 Y6 Y6 Y8 Y8 Y10 Y10 Q23 Y7 Y7 Y9 Y9 Y11 Y11 Q24 NC NC NC NC NC NC Q25 NC NC NC NC NC NC Q26 NC NC NC NC NC NC Q27 NC NC NC NC NC NC Q28 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Q29 Cb1 Cr1 Cb3 Cr3 Cb5 Cr5 Q30 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Q31 Cb3 Cr3 Cb5 Cr5 Cb7 Cr7 Q32 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8 Q33 Cb5 Cr5 Cb7 Cr7 Cb9 Cr9 Q34 Cb6 Cr6 Cb8 Cr8 Cb10 Cr10 Q35 Cb7 Cr7 Cb9 Cr9 Cb11 Cr11 HSYNC Embedded Embedded Embedded Embedded Embedded Embedded VSYNC Embedded Embedded Embedded Embedded Embedded Embedded DE Embedded Embedded Embedded Embedded Embedded Embedded Noe: This pin mapping is only id when he inpu video forma is YC 4:2:2 and he oupu video forma is YC 4:2:2 also. No video processing blocks should be enabled when his pin mapping is used. SiI-DS-1059-D 51

SAV Pixel0 Pixel1 Pixel2 Pixel3 Pixel n-1 Pixel n EAV Q[35:28] FF 00 00 XY Cb0[11:4] Cr0[11:4] Cb2[11:4] Cr2[11:4] Cbn-1[11:4] Crn-1[11:4] FF 00 00 XY Q[23:16] FF 00 00 XY Y0[11:4] Y1[11:4] Y2[11:4] Y3[11:4] Yn-1[11:4] Yn[11:4] FF 00 00 XY Q[27:24] X X X X Cb0[3:0] Cr0[3:0] Cb2[3:0] Cr2[3:0] Cbn-1[3:0] Crn-1[3:0] X X X X Q[15:12] X X X X Y0[3:0] Y1[3:0] Y2[3:0] Y3[3:0] Yn-1[3:0] Yn[3:0] X X X X ODCK Acive Video Figure 7.7. YC 4:2:2 Embedded Sync Timing Diagram Noe: The daa is defined in various specificaions o specific ues. These ues are conrolled by seing he appropriae SiI9127A/SiI1127A regisers, because no pixel daa is carried on HDMI during blanking. SAV/EAV codes appear as an 8-bi field on boh Q[35:28] (per SMPTE) and Q[23:16]. 52 SiI-DS-1059-D

YC Mux (4:2:2) Formas wih Separae Syncs The video daa is muliplexed ono fewer pins han he mapping in Table 7.8, bu complee luminance (Y) and chrominance (Cb and Cr) daa is sill provided for each pixel because he oupu pixel clock runs a wice he pixel rae. Figure 7.8 on he nex page shows he 24-bi mode. The 16-bi and 20-bi mappings use fewer oupu pins for he pixel daa. The separae syncs. Figure 7.8 shows imings wih OCLKDIV = 0 and OCKINV = 1. Table 7.8. YC Mux 4:2:2 Mappings Pin Name 8-bi YCbCr 10-bi YCbCr 12-bi YCbCr Q0 NC NC NC Q1 NC NC NC Q2 NC NC NC Q3 NC NC NC Q4 NC NC NC Q5 NC NC NC Q6 NC NC NC Q7 NC NC NC Q8 NC NC NC Q9 NC NC NC Q10 NC NC NC Q11 NC NC NC Q12 NC NC D0 Q13 NC NC D1 Q14 NC D0 D2 Q15 NC D1 D3 Q16 D0 D2 D4 Q17 D1 D3 D5 Q18 D2 D4 D6 Q19 D3 D5 D7 Q20 D4 D6 D8 Q21 D5 D7 D9 Q22 D6 D8 D10 Q23 D7 D9 D11 Q24 NC NC NC Q25 NC NC NC Q26 NC NC NC Q27 NC NC NC Q28 NC NC NC Q29 NC NC NC Q30 NC NC NC Q31 NC NC NC Q32 NC NC NC Q33 NC NC NC Q34 NC NC NC Q35 NC NC NC HSYNC HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC VSYNC DE DE DE DE SiI-DS-1059-D 53

Q[35:24] Q[11:0] X X X X Pixel 0 Pixel 1 Pixel 2 Pixel 3 X X X X X X X X X Q[23:16] Cb0[11:4] Y0[11:4] Cr0[11:4] Y1[11:4] Cb2[11:4] Y2[11:4] Cr2[11:4] Y3[11:4] Q[15:12] Cb0[3:0] Y0[3:0] Cr0[3:0] Y1[3:0] Cb2[3:0] Y2[3:0] Cr2[3:0] Y3[3:0] ODCK DE HSYNC VSYNC Figure 7.8. YC Mux 4:2:2 Timing Diagram Noe: The daa is defined in various specificaions o specific ues. These ues are conrolled by seing he appropriae SiI9127A/SiI1127A regisers, because no pixel daa is carried on HDMI during blanking. 54 SiI-DS-1059-D

YC Mux 4:2:2 Formas wih Embedded Syncs This mode is similar o ha on page 53, bu wih embedded syncs. I is similar o YC 4:2:2 wih embedded syncs, bu also muliplexes he luminance (Y) and chrominance (Cb and Cr) ono he same pins on alernaing pixel clock cycles. Normally his mode is used only for 480i, 480p, 576i and 576p modes. Oupu clock rae is half he pixel clock rae on he link. SAV code is shown before rise of DE. EAV follows he falling edge of DE. See he ITU-R BT.656 Specificaion for more informaion. 480p 54 MHz oupu can be achieved if he inpu differenial clock is 54 MHz. Figure 7.9 on he nex page shows OCLKDIV = 0 and OCKINV = 1. Table 7.9. YC Mux 4:2:2 Embedded Sync Pin Mapping Pin Name 8-bi YCbCr 10-bi YCbCr 12-bi YCbCr Q0 NC NC NC Q1 NC NC NC Q2 NC NC NC Q3 NC NC NC Q4 NC NC NC Q5 NC NC NC Q6 NC NC NC Q7 NC NC NC Q8 NC NC NC Q9 NC NC NC Q10 NC NC NC Q11 NC NC NC Q12 NC NC D0 Q13 NC NC D1 Q14 NC D0 D2 Q15 NC D1 D3 Q16 D0 D2 D4 Q17 D1 D3 D5 Q18 D2 D4 D6 Q19 D3 D5 D7 Q20 D4 D6 D8 Q21 D5 D7 D9 Q22 D6 D8 D10 Q23 D7 D9 D11 Q24 NC NC NC Q25 NC NC NC Q26 NC NC NC Q27 NC NC NC Q28 NC NC NC Q29 NC NC NC Q30 NC NC NC Q31 NC NC NC Q32 NC NC NC Q33 NC NC NC Q34 NC NC NC Q35 NC NC NC HSYNC Embedded Embedded Embedded VSYNC Embedded Embedded Embedded DE Embedded Embedded Embedded SiI-DS-1059-D 55

Q[35:24] Q[11:0] X X SAV X Pixel 0 Pixel 1 Pixel 2 Pixel 3 X X X X X X X X X Q[23:16] FF 00 00 XY Cb0[11:4] Y0[11:4] Cr0[11:4] Y1[11:4] Cb2[11:4] Y2[11:4] Cr2[11:4] Y3[11:4] Q[15:12] X X X X Cb0[3:0] Y0[3:0] Cr0[3:0] Y1[3:0] Cb2[3:0] Y2[3:0] Cr2[3:0] Y3[3:0] ODCK Acive Video Figure 7.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram Noe: The daa is defined in various specificaions o specific ues. These ues are conrolled by seing he appropriae SiI9127A/SiI1127A regisers, because no pixel daa is carried on HDMI during blanking. Refer o he SiI-PR-1033 Programmer Reference for deails. The Programmer s Reference requires an NDA wih Laice Semiconducor. 56 SiI-DS-1059-D

12/15/18-Bi RGB and YCbCr 4:4:4 Formas wih Separae Syncs The An oupu clock runs a he pixel rae, and a complee definiion of each pixel is oupu on each clock. One clock edge drives ou half he pixel daa on 12/15/18 pins. The opposie clock edge drives ou he remaining half of he pixel daa on he same 12/15/18 pins. Figure 7.10 shows RGB daa. The same iming forma is used for YCbCr 4:4:4 as lised in he columns of Table 7.10. Conrol signals (DE, HSYNC, and VSYNC) change sae wih respec o he firs edge of ODCK. Table 7.10. 12/15/18-Bi Oupu 4:4:4 Mappings Pin Name Firs Edge 24-bi 30-bi 36-bi RGB YCbCr RGB YCbCr RGB YCbCr Second Edge Firs Edge Second Edge Firs Edge Second Edge Firs Edge Second Edge Firs Edge Second Edge Q0 NC NC NC NC NC NC NC NC B0 G6 Cb0 Y6 Q1 NC NC NC NC NC NC NC NC B1 G7 Cb1 Y7 Q2 NC NC NC NC NC NC NC NC B2 G8 Cb2 Y8 Q3 NC NC NC NC B0 G5 Cb0 Y5 B3 G9 Cb3 Y9 Q4 NC NC NC NC B1 G6 Cb1 Y6 B4 G10 Cb4 Y10 Q5 NC NC NC NC B2 G7 Cb2 Y7 B5 G11 Cb5 Y11 Q6 B0 G4 Cb0 Y4 B3 G8 Cb3 Y8 B6 R0 Cb6 Cr0 Q7 B1 G5 Cb1 Y5 B4 G9 Cb4 Y9 B7 R1 Cb7 Cr1 Q8 B2 G6 Cb2 Y6 B5 R0 Cb5 Cr0 B8 R2 Cb8 Cr2 Q9 B3 G7 Cb3 Y7 B6 R1 Cb6 Cr1 B9 R3 Cb9 Cr3 Q10 B4 R0 Cb4 Cr0 B7 R2 Cb7 Cr2 B10 R4 Cb10 Cr4 Q11 B5 R1 Cb5 Cr1 B8 R3 Cb8 Cr3 B11 R5 Cb11 Cr5 Q12 B6 R2 Cb6 Cr2 B9 R4 Cb9 Cr4 G0 R6 Y0 Cr6 Q13 B7 R3 Cb7 Cr3 G0 R5 Y0 Cr5 G1 R7 Y1 Cr7 Q14 G0 R4 Y0 Cr4 G1 R6 Y1 Cr6 G2 R8 Y2 Cr8 Q15 G1 R5 Y1 Cr5 G2 R7 Y2 Cr7 G3 R9 Y3 Cr9 Q16 G2 R6 Y2 Cr6 G3 R8 Y3 Cr8 G4 R10 Y4 Cr10 Q17 G3 R7 Y3 Cr7 G4 R9 Y4 Cr9 G5 R11 Y5 Cr11 Firs Edge Second Edge HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC DE DE DE DE DE DE DE DE DE DE DE DE DE blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 blank blank blank Q[17:12] G0[5:0] R0[11:6] G1[5:0] R1[11:6] G2[5:0] R2[11:6] G3[5:0] R3[11:6] Q[11:6] B0[11:6] R0[5:0] B1[11:6] R1[5:0] B2[11:6] R2[5:0] B3[11:6] R3[5:0] Q[5:0] B0[5:0] G0[11:6] B1[5:0] G1[11:6] B2[5:0] G2[11:6] B3[5:0] G3[11:6] ODCK DE HSYNC, VSYNC Figure 7.10. 18-Bi Oupu 4:4:4 Timing Diagram SiI-DS-1059-D 57

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 blank blank blank Q[17:13] G0[4:0] R0[9:5] G1[4:0] R1[9:5] G2[4:0] R2[9:5] G3[4:0] R3[9:5] Q[12:8] B0[9:5] R0[4:0] B1[9:5] R1[4:0] B2[9:5] R2[4:0] B3[9:5] R3[4:0] Q[7:3] B0[4:0] G0[9:5] B1[4:0] G1[9:5] B2[4:0] G2[9:5] B3[4:0] G3[9:5] ODCK DE HSYNC, VSYNC Figure 7.11. 15-Bi Oupu 4:4:4 Timing Diagram blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 blank blank blank Q[17:14] G0[3:0] R0[7:4] G1[3:0] R1[7:4] G2[3:0] R2[7:4] G3[3:0] R3[7:4] Q[13:10] B0[7:4] R0[3:0] B1[7:4] R1[3:0] B2[7:4] R2[3:0] B3[7:4] R3[3:0] Q[9:6] B0[3:0] G0[7:4] B1[3:0] G1[7:4] B2[3:0] G2[7:4] B3[3:0] G3[7:4] ODCK DE HSYNC, VSYNC Figure 7.12. 12-Bi Oupu 4:4:4 Timing Diagram 58 SiI-DS-1059-D

8. I 2 C Inerfaces HDCP E-DDC / I 2 C Inerface For he SiI9127A device, he HDCP proocol requires ues o be exchanged beween he video ransmier and he video receiver. These ues are exchanged over he DDC channel of he DVI inerface. The E-DDC channel follows he I 2 C serial proocol. The SiI9127A/SiI1127A device is he video receiver in a sysem design using he SiI9127A/SiI1127A receiver and i has a connecion o he E-DDC bus wih a slave address of 0x74. The I 2 C read operaion is shown in Figure 8.1, and he wrie operaion is shown in Figure 8.2. Bus Aciviy : Maser Sar Slave Address Regiser Address Slave Address Sar Sop DSDA Line S S P A C K A C K A C K Daa No A C K Figure 8.1. I 2 C Bye Read Bus Aciviy : Maser Sar Slave Address Regiser Address Daa Sop DSDA Line S P A C K Figure 8.2. I 2 C Bye Wrie A C K A C K Muliple byes can be ransferred in each ransacion, regardless of wheher hey are reads or wries. The operaions are similar o hose in Figure 8.1 and Figure 8.2 excep ha here is more han one daa phase. An ACK follows each bye excep he las bye in a read operaion. Bye addresses incremen, wih he leas significan bye ransferred firs, and he mos significan bye las. See he I 2 C specificaion for more informaion. There is also a Shor Read forma, designed o improve he efficiency of Ri regiser reads, which mus be done every wo seconds while encrypion is enabled. This ransacion is shown in Figure 8.3. Wih his forma, here is only he slave address phase, and no regiser address phase, because he regiser address is rese o 0x08 (Ri) afer a hardware or sofware rese, and afer he STOP condiion on any preceding I 2 C ransacion. Bus Aciviy: Maser Sar Slave Address Ri Lsb Ri Msb Sop DSDA Line S P A C K A C K No A C K Figure 8.3. Shor Read Sequence SiI-DS-1059-D 59

Local I 2 C Inerface The SiI9127A/SiI1127A receiver has a second I 2 C por accessible only o he conroller in he display device. I is separae from he E-DDC bus. The receiver is a slave device ha responds o he six binary I 2 C device addresses of seven bis each. This I 2 C inerface only suppors he read operaion shown in Figure 8.1, and he wrie operaion shown in Figure 8.2. I does no suppor he shor read operaion shown in Figure 8.3. The I 2 C daa pin for he local I 2 C bus is CSDA, insead of he DSDA pin shown in hese figures. The local I 2 C inerface on he receiver (pins CSCL and CSDA) is a slave inerface ha can run up o 400 khz. This bus is used o configure and conrol he SiI9127A/SiI1127A device by reading or wriing o necessary regisers. The local I 2 C inerface consiss of 5 separae I 2 C slave addresses. Therefore, i appears as 5 separae devices on he I 2 C local bus. The firs wo of hese addresses, used for HDMI Conrol and general low level regiser conrol, are fixed and can only be se o one of wo ues by using he CI2CA pin. Table 8.1 shows he address seleced for each sae of he CI2CA pin a rese. The oher 3 addresses, used for CEC, EDID and xvycc, have an I 2 C regiser-programmable address mapped ino he HDMI Conrol regiser space, so he defaul ue can be changed if here is a bus conflic wih anoher device. Table 8.1. Conrol of he Defaul I 2 C Addresses wih he CI2CA Pin Regiser Group CI2CA = LOW CI2CA = HIGH HDMI Conrol and low level regisers (fixed) 0x60 & 0x68 0x62 & 0x6A The HDMI Conrol and low level regisers are fixed afer a rese based on CI2CA pin and canno be changed. The I 2 C slave address for he xvycc regisers, EDID Conrol regisers, and he CEC Conrol regisers each have a regiser associaed wih hem ha allows he address o be changed. Refer o he SiI-PR-1033 Programmer Reference for more informaion. Video Requiremen for I 2 C Access The SiI9127A/SiI1127A receiver does no require an acive video clock o access is regisers from eiher he E-DDC por or he local I 2 C por. Read-Wrie regisers can be wrien and hen read back. Read-only regisers ha provide ues for an acive video or audio sream reurn indeerminae ues if here is no video clock and no acive syncs. Use he SCDT and CKDT regiser bis o deermine when acive video is being received by he chip. I 2 C Regisers The regiser ues ha are exchanged over he HDMI DDC I 2 C serial inerface wih he receiver for HDCP are described in he HDCP Specificaion in Secion 2.6 HDCP Por. Refer o he SiI-PR-1033 Programmer Reference for deails on hese and all oher SiI9127A/SiI1127A regisers. 60 SiI-DS-1059-D

9. Design Recommendaions The following informaion is provided as recommendaions ha are based on he experience of Laice Semiconducor engineers and cusomers. If you choose o deviae from hese recommendaions for a paricular applicaion, Laice Semiconducor srongly suggess ha you conac one of is echnical represenaives for an euaion of he change. Power Conrol The low-power sandby sae feaure of he SiI9127A/SiI1127A receiver provides a design opion of leaving he chip always powered, as opposed o powering i on and off. Leaving he chip powered and using he PD# regiser bi o pu i in a lower power sae can resul in faser sysem response ime, depending on he sysem Vcc supply ramp-up delay. Power-on Sequencing Due o iming consideraions wih he power-on rese circuis wihin he chip, Laice Semiconducor recommends ha 5 V power is available o he device before he 3.3 V and 1.2 V VCC supplies are enabled. If he 3.3 V and 1.2 V supplies reach heir operaing levels before he 5 V power supply o he power island, he chip may no rese properly. Power Pin Curren Demands The limis shown in Table 9.1 indicae he curren demanded by each group of power pins on he device. These limis were characerized a maximum VCC, 0 C ambien emperaure and for fas-fas silicon. Acual applicaion curren demands can be lower han hese figures and vary wih video resoluion and audio clock frequency. Table 9.1. Maximum Power Domain Currens versus Video Mode Mode ODCK (MHz) 3.3 V Power Domain Currens (ma) IOVCC33 AVCC33 XTALVCC33 480p 27.0 39 62 2 1080i 74.25 104 62 2 1080p 148.5 217 62 2 1080p@12-bi 1 225 302 62 2 Mode ODCK (MHz) 1.2 V Power Domain Currens (ma) AVCC12 CVCC12 APVCC12 480p 27.0 79 40 3 1080i 74.25 86 88 3 1080p 148.5 118 158 3 1080p@12-bi 1 225 95 191 3 Noes: 1. Measured wih 12 bis/pixel video daa. 2. Measured wih 192 khz, 8-channel audio, excep for 480p mode which used 48 khz, 8-channel audio. 3. Measured wih RGB inpu, verical black-whie/1-pixel sripe (Moire2) paern, convering o YCbCr oupu (digial for IOVCC33). 4. Only one core can be seleced a a ime. The TMDSxSEL regiser bi urns off he unseleced core, excep for he erminaion o AVCC33. AVCC33 curren includes 40 ma for he unseleced TMDS core. Only 5 ma of his curren is dissipaed as power in he receiver; he remainder is dissipaed in he HDMI ransmier. The AVCC33 curren on he unseleced core can be reduced o 5 ma by assering he corresponding PD_TERMx# regiser bi. SiI-DS-1059-D 61

HDMI Receiver DDC Bus Proecion The VESA DDC Specificaion (see Sandards Groups on page 74) defines he DDC I 2 C inerconnec bus o be a 5 V signaling pah. The I 2 C pins on he SiI9127A/SiI1127A chip are 5 V oleran and are rue open-drain I/O. The pull-up resisors on he DDC bus should be pulled up using he 5 V supply from he HDMI connecor. See Figure 9.9 on page 70. Decoupling Capaciors Designers should include decoupling and bypass capaciors a each power pin in he layou. These are shown schemaically in Figure 9.4 on page 65. Place hese componens as close as possible o he SiI9127A/SiI1127A pins and avoid rouing hrough vias. Figure 9.1 shows various ypes of power pins on he receiver. VCC C1 C2 L1 VCC Ferrie GND C3 Via o GND Figure 9.1. Decoupling and Bypass Capacior Placemen ESD Proecion The SiI9127A/SiI1127A chip is designed o wihsand an elecrosaic discharge up o 2 kv. In applicaions where higher proecion levels are required, ESD limiing componens can be placed on he differenial lines coming ino he chip. These componens ypically have a capaciive effec, reducing he signal qualiy a higher clock frequencies on he link. Use of he lowes capaciance devices is suggesed; he capaciance ue should no exceed 5 pf in any case. Series resisors can be included on he TMDS lines (see Figure 9.9 on page 70) o counerac he impedance effecs of ESD proecion diodes. The diodes ypically lower he impedance because of heir capaciance. The resisors raise he impedance o say wihin he HDMI Specificaion, cenered on a 100 Ω differenial. 62 SiI-DS-1059-D

HDMI Receiver Layou The SiI9127A/SiI1127A chip should be placed as close as possible o he inpu connecors ha carry he TMDS signals. For a sysem using indusry-sandard HDMI connecors (see Sandards Groups on page 74), he differenial lines should be roued as direcly as possible from he connecor o he receiver. Laice Semiconducor receivers are oleran of skews beween differenial pairs, so spiral skew compensaion for pah lengh differences is no required. Each differenial pair should be roued ogeher, minimizing he number of vias hrough which he signal lines are roued. The disance separaing he wo races of he differenial pair should be kep o a minimum. In order o achieve opimal inpu TMDS signal qualiy, follow he layou guidelines below: Lay ou all differenial pairs wih a conrolled differenial impedance of 100. Cu ou all ground and power copper planes ha are less han 45 mils underneah he TMDS races near he receiver wih he dimensions shown in Figure 9.2. If ESD suppression devices or common mode chokes are used, place hem near he HDMI connecor, away from he SiI9127A/SiI1127A package. Do no place hem over he ground and power plane cuou near he receiver. 0.3 inch > 0.1 inch HDMI Receiver HDMI Connecors > 0.1 inch Ground and Power plane cu-ou for copper planes <45 mil separaion from TMDS races Figure 9.2. Cu-ou Reference Plane Dimensions SiI-DS-1059-D 63

In Figure 9.3, which is a represenaion of a PCB conaining HDMI connecors and he receiver, he sixeen TMDS races are conneced direcly from he HDMI connecors (shown on he lef in he figure) o he pins on he SiI9127A/SiI1127A receiver (shown on he righ). Trace differenial impedance should be 100 for each pair and 50 single-ended if possible. Trace widh and pich depends on he PCB consrucion. No all connecions are shown; he drawing demonsraes rouing of TMDS lines wihou crossovers, vias, or ESD proecion. Refer also o Figure 9.9. +5V DDC#0 DDC#1 PIN 19 R1PWR5V PIN 1 HDMI Por #0 Connecor HDMI Por #1 Connecor PIN 19 10 19 +5V 10 DDC#1 R0PWR5V SiI9127A/ SiI1127A PIN 1 19 Drawing is no o exac. scale. Refer o HDMI connecor specificaion for. exac dimensions EMI Consideraions Figure 9.3. HDMI o Receiver Rouing Top View Elecromagneic inerference is a funcion of he board layou, shielding, receiver componen operaing volage, and frequency of operaion, among oher facors. When aemping o conrol emissions, do no place any passive componens on he differenial signal lines oher han he essenial ESD proecion described earlier. The differenial signaling used in HDMI is inherenly low in EMI as long as he rouing recommendaions noed in he Receiver Layou secion are followed. The PCB ground plane should exend unbroken under as much of he SiI9127A/SiI1127A chip and associaed circuiry as possible, wih all ground pins of he chip using a common ground. 64 SiI-DS-1059-D

Typical Circui Represenaive circuis for applicaion of he SiI9127A/SiI1127A receiver chip are shown in Figure 9.4 hrough Figure 9.8. For a deailed review of your inended circui implemenaion, conac your Laice Semiconducor represenaive. Power Supply Decoupling AVCC_3.3V Ferrie 220 @100MHz AVCC33 0.1 F 10 F 0.1 F 0.1 F 0.1 F 1 nf 1 nf 1 nf +3.3 V Place ceramic capaciors close o VCC pins. GND IOVCC33 10 F 10 F 0.1 F 0.1 F 0.1 F 0.1 F 1 nf 1 nf 1 nf 1 nf 1 nf 1 nf 1 nf +1.2 V Place ceramic capaciors close o VCC pins. GND CVCC 12 10 F 10 F 0.1 F 0.1 F 0.1 F 0.1 F 1 nf 1 nf 1 nf 1 nf 1 nf 1 nf 1 nf +1.2 V 0.56 1% Ferrie 0.82 H, 150 ma GND AVCC12 SiI9127A/ SiI1127A 10 F 0.1 F 0.1 F 0.1 F 1 nf 1 nf 1 nf +1.2 V +3.3 V Ferrie 220@100 MHz Ferrie 220@100 MHz AGND APVCC12 XTALVCC33 +5 V SBVCC 5 Figure 9.4. Power Supply Decoupling and PLL Filering Schemaic The ferrie on AVCC33 aenuaes noise above 10 khz. A parasiic resisor helps o minimize he peaking. An example of a surface moun device is he MLF2012 Series SMD inducors from TDK. SiI-DS-1059-D 65

HDMI Por Connecions RX2+ n RX2- n RX1+ n RX1- n RnX1+ RX0+ n RX0- n RnX0+ RXC+ n RXC- n RnXC+ RnX0- RnX2+ RnX2- RnX1- RnXC- HDMI Connecor Por n CEC n CEC_A SiI9127A/SiI1127A HPD n HPDn +5V n 47 k 47 k SCL n DSCLn SDA n DSDAn Figure 9.5. HDMI Por Connecions Schemaic Noe: Repea he schemaic for each HDMI inpu por on he receiver. 66 SiI-DS-1059-D

Digial Video Oupu Connecions SiI9127A/SiI1127A INT 22 Microconroller 60 DE HSYNC 62 61 VSYNC 65 ODCK 85 Q0 84 Q1 83 Q2 82 Q3 81 Q4 80 Q5 79 Q6 78 Q7 77 Q8 74 Q9 73 Q10 72 Q11 33 33 33 33 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 71 70 69 68 67 66 59 58 57 56 55 54 33 33 33 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 53 52 51 48 47 46 45 44 43 42 41 40 33 33 33 Figure 9.6. Digial Display Schemaic The 3.3 V o he level-shifers and pull-up resisors should be powered-down whenever he 3.3 V is powered-down on he receiver iself. The receiver INT oupu can be conneced as an inerrup o he microconroller, or he microconroller can poll regiser 0x70 (INTR_STATE) o deermine if any of he enabled inerrups have occurred. Refer o he SiI-PR-1033 Programmer Reference for deails. The receiver VSYNC oupu can be conneced o he microconroller if i is necessary o monior he verical refresh rae of he incoming video. SiI-DS-1059-D 67

Digial Audio Oupu Connecions +3.3 V Ferrie SiI9127A/SiI1127A XTALVCC SCK WS 0.1 F 0.01 F SD0 SPDIF DCLK DR[2:0] DL[2:0] 18 pf XTALIN MCLKOUT MUTEOUT 33 1 M 27.00 MHz 18 pf XTALOUT Place crysal circui as closely o package as possible. Figure 9.7. Audio Oupu Schemaic 68 SiI-DS-1059-D

Conrol Signal Connecions +3.3 V SiI9127A/ Si1127A CSDA 4.7 k 4.7 k CSDA CSCL CSCL EVEN/ODD Field EVNODD RSVDL Microconroller 4.7 k GPIO SCDT and INT oupus o micro are opional. Sync saus and inerrup bis may be polled hrough CSDA/ CSCL I 2 C por. RESET# GPIO SCDT GPIO INT GPIO Firmware moniors Ho Plug Deec signal o rigger EDID re- read and inhibi HDCP auhenicaion aemps. HPD HDMI Connecor Figure 9.8. Conroller Connecions Schemaic SiI-DS-1059-D 69

Layou Figure 9.9 shows an example of rouing TMDS lines beween he SiI9127A/SiI1127A device and he HDMI connecor. TMDS Inpu Por Connecions DDC SCL DDC SDA Ho Plug Deec Connecor Shell +5V Power DDC Ground Reserved NC CEC TMDS Clock- TMDS Clock Shield TMDS Clock+ Figure 9.9. TMDS Inpu Signal Assignmens TMDS Daa 2+ TMDS Daa 2- TMDS Daa 1+ TMDS Daa 1- TMDS Daa 0+ TMDS Daa 0- TMDS Daa Shield TMDS Daa Shield TMDS Daa Shield 70 SiI-DS-1059-D

10. Package Informaion epad Requiremens The SiI9127A/SiI1127A receiver is packaged in a 128-pin, 14 mm x 14 mm TQFP package wih an epad ha is used for he elecrical ground of he device and for improved hermal ransfer characerisics. The epad dimensions are 4.445 mm x 4.0604 mm ±0.15 mm. Soldering he epad o he ground plane of he PCB is required o mee package power dissipaion requiremens a full speed operaion, and o correcly connec he chip circuiry o elecrical ground. A clearance of a leas 0.25 mm should be designed on he PCB beween he edge of he epad and he inner edges of he lead pads o avoid he possibiliy of elecrical shors. The hermal land area on he PCB may use hermal vias o improve hea remo from he package. These hermal vias also double as he ground connecions of he chip and mus aach inernally in he PCB o he ground plane. An array of vias should be designed ino he PCB beneah he package. For opimum hermal performance, he via diameer should be 12 mils o 13 mils (0.30 mm o 0.33 mm) and he via barrel should be plaed wih 1-ounce copper o plug he via. This design helps o avoid any solder wicking inside he via during he soldering process, which may resul in voids in solder beween he pad and he hermal land. If he copper plaing does no plug he vias, he hermal vias can be ened wih solder mask on he op surface of he PCB o avoid solder wicking inside he via during assembly. The solder mask diameer should be a leas 4 mils (0.1 mm) larger han he via diameer. Package sand-off when mouning he device also needs o be considered. For a nominal sand-off of approximaely 0.1 mm he sencil hickness of 5 mils o 8 mils should provide a good solder join beween he epad and he hermal land. Figure 10.1 on he nex page shows he package dimensions of he SiI9127A/SiI1127A receiver. PCB Layou Guidelines Refer o Laice Semiconducor applicaion noe PCB Layou Guidelines: Designing wih Exposed Pads (see Laice Semiconducor Documens on page 74) for basic PCB design guidelines when designing wih hermally enhanced packages using he exposed pad. This applicaion noe is inended for use by PCB layou designers. SiI-DS-1059-D 71

Package Dimensions Figure 10.1 shows he layou and dimensions of he 128-pin TQFP package. Package drawings are no o scale. 96 D D1 D2 4.064 ± 0.15 65 97 64 R 1 R 2 A A GAGE PLANE.25 S A B 4.445 ± 0.15 E2 E1 E L 1 L SECTION A-A 128 33 Pin 1 Idenifier 1 e b 32 0.07 M C A B S D S 0.20 C A B D 0.20 H A B D TOP VIEW 0.05 S A A 2 A 1 L1 0.08 c C Seaing Plane C SIDE VIEW JEDEC Package Code MS-026-AFB Iem Descripion Typ Max Iem Descripion Typ Max A Thickness 1.10 1.20 b Lead widh 0.16 0.23 A1 Sand-off 0.10 0.15 c Lead hickness 0.20 A2 Body hickness 1.00 1.05 e Lead pich 0.40 D Fooprin 16.00 L Lead foo lengh 0.60 0.75 E Fooprin 16.00 L1 Lead lengh 1.00 D1 Body size 14.00 E1 Body size 14.00 D2 Lead Row Widh 12.40 E2 Lead Row Widh 12.40 Dimensions are in millimeers. Overall hickness A = A1 + A2. Figure 10.1. 128-Pin TQFP Package Diagram 72 SiI-DS-1059-D

Marking Specificaion Figure 10.2 shows he markings of he SiI9127A package. This drawing is no o scale. Refer o he specifics in Figure 10.1 on he previous page. Figure 10.3 shows he alernae marking diagram for SiI9127A/SiI1127A. Logo Produc Line SiI9127ACTU LLLLLL.LL-L YYWW TTTTTTmmmr Par Number Lo # (= Job#) Dae code Trace code Pin 1 locaion Figure 10.2. Marking Diagram of SiI9127A SiI9127ACTU SiI1127ACTU DATECODE DATECODE Region/Counry of Origin @ Region/Counry of Origin @ Pin 1 Indicaor Pin 1 Indicaor Figure 10.3. Alernae Marking Diagram Ordering Informaion Producion Par Numbers: TMDS Inpu Clock Range Par Number The universal package may be used in lead-free and ordinary process lines. 25 MHz 225 MHz SiI9127ACTU 25 MHz 225 MHz SiI1127ACTU SiI-DS-1059-D 73

References Sandards Documens This is a lis of sandards abbreviaions appearing in his documen, and references o heir respecive specificaions documens. Abbreviaion Sandards publicaion, organizaion, and dae HDMI High-Definiion Mulimedia Inerface, Revision 1.4b, HDMI Consorium; Ocober 2011 High-Definiion Mulimedia Inerface, Revision 1.4a, HDMI Consorium; March 2010 High Definiion Mulimedia Inerface, Revision 1.3, HDMI Consorium; June 2006 HCTS HDMI Compliance Tes Specificaion, Revision 1.2a, HDMI Consorium; December 2005 HDCP High-bandwidh Digial Conen Proecion, Revision 1.3, Digial Conen Proecion, LLC; December 2006 E-EDID Enhanced Exended Display Idenificaion Daa Sandard, Release A Revision 1, VESA; Feb. 2000 E-DID IG VESA EDID Implemenaion Guide, VESA; June 2001 CEA-861 A DTV Profile for Uncompressed High Speed Digial Inerfaces, EIA/CEA; January 2001 CEA-861-B A DTV Profile for Uncompressed High Speed Digial Inerfaces, Draf 020328, EIA/CEA; March 2002 CEA-861-D A DTV Profile for Uncompressed High Speed Digial Inerfaces, EIA/CEA; July 2006 EDDC Enhanced Display Daa Channel Sandard, Version 1.1, VESA; March 2004 Sandards Groups For informaion on he specificaions ha apply o his documen, conac he responsible sandards groups appearing on his lis. Sandards Group Web URL ANSI/EIA/CEA VESA DVI HDCP HDMI hp://global.ihs.com hp://www.vesa.org hp://www.ddwg.org hp://www.digial-cp.com hp://www.hdmi.org Laice Semiconducor Documens This is a lis of he relaed documens ha are available from your Laice Semiconducor sales represenaive. The Programmer s Reference requires an NDA wih Laice Semiconducor. Documen Tile SiI-PR-1033 SiI-PR-0041 SiI-AN-0129 SiI9127A/SiI1127A HDMI Receiver wih Deep Color Oupus Programmer Reference CEC Programming Inerface (CPI) Programmer Reference PCB Layou Guidelines: Designing wih Exposed Pads Applicaion Noe Technical Suppor For assisance, submi a echnical suppor case a www.laicesemi.com/echsuppor. 74 SiI-DS-1059-D

Revision Hisory Revision D, May 2017 Figure 10.3. Alernae Marking Diagram added per PCN13A16. Revision C, February 2016 Added SiI1127A receiver suppor. Updaed o laes emplae. Revision B, December 2012 Added local I 2 C device addresses and 3D video forma suppor. Revision A03, Sepember 2010 Removed Paen informaion from DB, rolled he revision for DS. Revision A02, May 2010 Rewrie page 1; minor conen correcions; ligh copyedi; updae package drawing; prepare Daa Brief. Revision A01, April 2009 Removed audio downsampling, oupu delay conrol, video oupu pull-down informaion; updaed specificaions and layou. Revision A, Ocober 2008 Firs producion release. SiI-DS-1059-D 75

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