MIMO Development Efforts at Virginia Tech

MIMO Development Efforts at Virginia Tech S. Ellingson 1, R. Mostafa 2 & J. Reed 2 {ellingson,ramostaf,jhreed}@vt.edu 1 Virginia Tech Antenna Group (VTAG) 2 Mobile & Portable Radio Research Group (MPRG) Bradley Dept. of Electrical & Computer Engineering Virginia Polytechnic Institute & State University 340 Whittemore Hall, Blacksburg VA 24061 September 19, 2004 Slide 1

MIMO at Virginia Tech Virginia Tech is interested in all aspects of MIMO: MIMO channel physics MIMO communication theory Practical implementation (HW, SW, Systems, & Networks) This talk: Evolution of a serial-bus based data aggregation scheme for array receivers Full presentation (including more details on other efforts) available: http:// http://www.mprg.org www.mprg.org/ Slide 2

Array Receiver Architectures A MIMO communications link or channel measurement system consists of An array transmitter An array receiver Array transmitters are easy Array receivers are hard Data Aggregation (interconnects) Processing Throughput (logic density) Slide 3

SHF Array Experimental (SAX) 16-Channel Digital Receiver (PC with A/D cards) Classical Polled Bus Data Aggregation MIMO Channel Measurement Project (1999-2000) SHF Rack (24xx 435 MHz) UHF Rack (435 7.5 MHz) A/D Conditioning, Power, and Cal Rear View of Rack Slide 4

SAX: On-the the-fly Data Display Slide 5

SAX: Field Eval of MIMO Capacity Ideal N T =2 Ideal N T =8 Measured N T =8 Measured N T =2 Measured N T =1 (LOS) (Behind Building) Slide 6

SAX: Lessons Learned Limitations of Polled Bus Architecture Data Aggregation Processing Throughput MIMO Field Studies Easy to be overrun by complexity, yet: Traditional architectures are too slow -> > Time IS money Near real time monitoring is GOOD (less wasted effort when things s go wrong!) More info: S.W. Ellingson, "Effects of Angle Spread in a Complex Outdoor Environment At 2.4 GHz", 2003 IEEE Antennas & Propagation Soc. Int'l Symposium,, Columbus, OH, June 2003 (3:264( :264-7). S.W. Ellingson, "Vector Channel Coherence in a Complex Outdoor Environment E At 2.4 GHz", 2003 IEEE Antennas & Propagation Soc. Int'l Symposium, Columbus, OH, June 2003 (4:208( :208-11). People involved: S. Ellingson, I. Gupta (OSU), J. Hetrick (TRW), K. Ayotte (OSU), G. Whipps (OSU) Slide 7

Argus Astrophysical transient search instrument N = 36 element array, 24 instrumented 1200-1700 1700 MHz tuning T sys ~ 215 K per element Digitizes 20 MSPS complex (14 MHz BW); processed to 78.125 ksps complex & aggregated into a single 80-Mb/s serial data stream Data stream broadcast using UDP/IP over Ethernet to PC cluster for all subsequent processing Pulse sensitivity ~ 24 kjy at zenith in 0.2 s Slide 8

Argus Narrowband Processor Solves the corner turning problem using serial bus architecture implemented using LVDS Control goes out, time-ordered data and status comes back Same architecture simplifies additional processing & interfaces to other systems Slide 9

Argus: Lessons Learned LVDS serial bus technology is an effective replacement for polled bus architectures, especially for large-n, low- BW systems More info: S.W. Ellingson and G.A. Hampson, "Argus: An L-Band Array for Detection of Astronomical Transients," 2003 IEEE Int'l Ant. and Prop. Sym., Columbus, OH, June 2003 (3:256-9). S.W. Ellingson and G.A. Hampson, "Detection and Localization of L-Band Satellites Using an Antenna Array", 2004 IEEE Antennas & Propagation Soc. Int'l Symposium, Monterey, CA, June 2004. Project web site: http://www.ece.vt.edu/~swe/argus Key involved: S. Ellingson, G. Hampson (CSIRO), many others Slide 10

Matrix Channel Measurement System (MCMS) TAS Application & frequency specific Vector / Matrix Channel Under Test RAS Application & frequency specific 4 Key 16 Signal Flow Control/Status Cal MCT - 4 Channels Arbitrary, coherent waveforms 250 MHz - 6 GHz 40 MHz BW MCR - 16 Channels Continuous capture & On-the-fly analysis Portable (2-man lift) Battery Powered; 1-hr 1 minimum Slide 11

MCMS: Downconverter / Digitizer Up/Down/Down + Down/Down Superhet 250 MHz - 6 GHz tuning 40 MHz BW IF input (78 MHz center) Dual RJ45 Connector For 1.248 Gb/s LVDS output 12 bit A/D 104MHz clock Slide 12

MCMS: Digital IF Board DB37 Backplane Connector 3.3V, 1.5V, GND Daisy Chain Clock, Reset DDC Sync signals Analog Devices AD6620 Digital Downconverter (DDC) For narrowband signal processing Memory board located On rear of PCB LVDS Receivers for odd and even A/D data LVDS Transceiver for daisy chain serial bus Wideband signal processing on Altera Stratix FPGA 1.248 Gb/s Data from A/D Slide 13

MCMS: DIF Board Capabilities F S /4 Conversion Stage 104 MSPS real @ 78 MHz 52 MSPS complex @ baseband Programmable 63 tap FIR with 12-bit coefficients Decimation by 2 Outputs 26 MSPS complex @ baseband (16 bits) Can be bypassed (unless AD6620 DDC is to be used) Programmable 46 tap FIR with 12-bit coefficients Digital Downcoverter (DDC) AD6620 input/output/control through FPGA Very large decimations & fine tunings possible User programmable through software interfaces Slide 14

MCMS: Serial Bus Test PC Interface Data path; also controls corner turner & digital IF boards 1.248 Gb/s LVDS data from each ADC Corner Turner Aggregates data across channels and reorders samples Digital IF Processor 16-Channel Digital Backplane Four LVDS loops, each servicing 4 channels. Each loop is 320 Mb/s. Slide 15

MCMS Validation: Raw A/D Output LabWindows CVI Interface Time Domain 104 MSPS real (AD9432 is 12-bit so full scale is +/-2048) 27 MHz IF input Frequency Domain Blue: 1 Yellow: 100, average Observed SNR is >65dB (Specification is 67dB) Slide 16

MCMS Validation: After F S /4, 2 Time Domain 52 MSPS complex Output of Fs/4 Downconversion is 16-bits (+/-32K) Filter Specs: 63-tap FIR, 12-bit coeff., 12-bit in, 16-bit out, 20 MHz LP -F S /4 Spectral Shift (104 / 4 = 26 MHz) +27 MHz shifts to +1MHz Frequency Domain Blue: 1 Yellow: 100, average Slide 17

MCMS Validation: Second 2 Time Domain 26 MSPS complex Filter Specs: 31-tap FIR, 12-bit coeff. 12-bit in 16-bit out 10 MHz LP Output BW is now 40/2=20MHz Frequency Domain Blue: 1 Yellow: 100, average Slide 18

MCMS Validation: DDC Output Time Domain 130 ksps DDC Filter: Dec by 200 128-tap FIR 16-bit in 16-bit out 50 khz LPF Frequency Domain Blue: 1 Yellow: 100, average Slide 19

MCMS Validation : Digital Upconverter GUI-based Control Software Running in C using LabWindows/CVI Measured Output I/F board in Circulate Mode I/Q symbols (noise) @ 12.5 Mbaud AD9857 in Quadrature Mode Interpolation by 4 x 4, to 200 MSPS NCOM upconversion to 50 MHz Observing D/A output Slide 20

MCMS: Data Acquisition and DSP Dedicated Windows PCs in cpci chassis Bittware Hammerhead quad ADSP-21160 DSP board for on- the-fly processing Connected to corner turner through 4 100-MB/s link port cables Slide 21

MCMS Summary Project Status: Mass build of subsystems & final assembly underway at industry partner s facility Delivery expected November 2004 Long & extensive commissioning process to follow Planned First Uses: 2.4 GHz x 40 MHz indoor channel meas. campaign 2.4 GHz 4 x 16 MIMO/OFDM simplex testbed Project Web Site: http:// Key people: S. Ellingson, G. Hampson (now at CSIRO), B. Reynolds (Aeroflex( Aeroflex), P. Bohley (Aeroflex), S. Fisher (Aeroflex), Slide 22

MCMS Summary Project Status: Mass build of subsystems & final assembly underway at industry partner s facility Delivery expected October 2004 Long & extensive commissioning process to follow Planned First Uses: 2.4 GHz x 40 MHz indoor channel meas. campaign 2.4 GHz 4 x 16 MIMO/OFDM simplex testbed Anybody else want one? Project Web Site: http:// Key people: S. Ellingson, G. Hampson (now at CSIRO), B. Reynolds (Aeroflex( Aeroflex), P. Bohley (Aeroflex), S. Fisher (Aeroflex), Slide 23

Virginia Tech Summary Current MIMO Testbed Initiatives at VT: MCMS VT-STAR SDR-3000 The testbeds have strong potential for research contribution in MIMO area: MIMO measurements and validation of performance improvement Demonstration of existing air interfaces with MIMO technology These testbeds impart significant value and greater outreach to education: Used by students to support wireless course projects Different smart antenna algorithms have been demonstrated by students Emphasis on programmable, software-defined hardware Slide 24