Modeling and Implementing Software-Defined Radio Communication Systems on FPGAs Puneet Kumar Senior Team Lead - SPC 2012 The MathWorks, Inc. 1
Agenda Integrated Model-Based Design to Implement SDR on FPGA s, highlighting: Rapidly develop and verify a baseline transmitter and receiver using library blocks Automatically generate HDL code and integrate the code with target hardware Verify the design using HDL cosimulation and FPGA-in-the-loop on an FPGA Evaluation Kit Q&A 2
Software Defined Radio - Demo 3
Beacon Frame Receiver SDR Demo 4
Software Defined Radio 5
Software Defined Radio Software or Programmable Logic 6
Software Defined Radio 7
Some SDR systems (various vendors) 8
Implementing a Wireless Receiver on an FPGA Build a Baseline QPSK Model o Create Simulink executable model to explore design choices and determine baseline performance o Use model to generate wireless test signal Elaborate and Prototype the Design o Designing the carrier and timing recovery loops for a QPSK receiver o Verify the design with the wireless test signal Implement on Target Hardware o Convert the QPSK design to an implementation level model o Generate HDL code and integrate with target hardware 9
Implementing a Wireless Receiver on an FPGA Build a Baseline QPSK Model o Create Simulink executable model to explore design choices and determine baseline performance o Use model to generate wireless test signal Elaborate and Prototype the Design o Designing the carrier and timing recovery loops for a QPSK receiver o Verify the design with the wireless test signal Implement on Target Hardware o Convert the QPSK design to an implementation level model o Generate HDL code and integrate with target hardware 10
Build a Baseline QPSK Model Steps to follow 1. Get the Design Specification 2. Build the Executable Testbench 3. Verify the Model 11
Design Specifications Modulation: Symbol Rate: QPSK 195 kilo-sym/sec RRCOS Filter Stopband Attenuation: 30 db Rolloff: 0.25; Interp/Decim Factor: 8 Carrier Frequency: 432 MHz 12
Communications System Toolbox The Communications System Toolbox extends Simulink to design and simulate the physical layer of communication systems and components. Modulation AM, PM, FM, CPM, TCM Hard Decision, Log Likelihood Forward Error Correction Reed Solomon, Convolutional RF Impairments Synchronization, Equalization 13
Build the Executable Test Bench Simulink Executable Model Simulink Library Browser Visualization 14
Verify the Model with AWGN Channel and BER Analysis Establish Baseline Simulated Results vs Theory BERTool 15
Verify the Model Generate Wireless Test Signal using MATLAB/Simulink SDR Interface E100 Communications Model Gigabit Ethernet N210 USRP2 MAT file Spectrum Analyzer 16
Implementing a Wireless Receiver on an FPGA Build a Baseline QPSK Model o Create Simulink executable model to explore design choices and determine baseline performance o Use model to generate wireless test signal Elaborate and Prototype the Design o Designing the carrier and timing recovery loops for a QPSK receiver o Verify the design with the wireless test signal Implement on Target Hardware o Convert the QPSK design to an implementation level model o Generate HDL code and integrate with target hardware 17
Elaborate and Prototype the Design Steps to follow 1. Add more realistic impairments to the Basic QPSK Model 2. Design mitigation algorithms 3. Test design with real captured data 18
Wireless Channel Impairments Additive thermal noise Multipath fading Not a concern here due to close-range line-of-sight communication Synchronization Carrier phase/frequency offset Symbol timing offset Frame boundaries 19
Effect of Carrier Frequency Offset 20
Effect of Carrier Frequency Offset 21
Effect of Carrier Frequency Offset 22
Carrier Synchronization Loop Filter e j( ω 0n θ) Phase Error Detector arg(.) K1 K2 Z -1 NCO e j( ω 0n θ) e j(.) Z -1 Rice, M. (2008). Digital Communications: A Discrete-Time Approach, Prentice Hall. 23
Implementing a Wireless Receiver on an FPGA Build a Baseline QPSK Model o Create Simulink executable model to explore design choices and determine baseline performance o Use model to generate wireless test signal Elaborate and Prototype the Design o Designing the carrier and timing recovery loops for a QPSK receiver o Verify the design with the wireless test signal Implement on Target Hardware o Convert the QPSK design to an implementation level model o Generate HDL code and integrate with target hardware 24
Algorithm Development Process Requirements Research & Design Explore and discover Design Gain insight into problem Evaluate options, trade-offs Implementation Elaborate Test Test & Verification Desktop.dll.exe.c, C,.cpp C++ Embedded C, C++ VHDL / Verilog Structured Text Design Elaborate Test 25
Solution: C and HDL Code Generation Design, execute, and verify algorithms in MATLAB MATLAB Algorithm Design Automatically generate C or HDL code Deploy generated code on hardware MATLAB Coder CGenerate HDL Coder Generate VHDL/Verilog FPGA MCU ASIC DSP FPGA ASIC 26
Targeting HDL with an SDR Platform Workflow Demo 27
Model-Based Design flow using Simulink from Algorithm to FPGA Implementation MATLAB and Simulink Algorithm and System Design DESIGN HDL Coder RTL Creation HDL Verifier HDL Co-Simulation Algorithm Development MATLAB Simulink Stateflow RTL Back Annotation Implement Design Verification Synthesis Functional Simulation Map Static Timing Analysis Place & Route Timing Simulation HDL Verifier FPGA in the Loop 28
Thank You! 29