AN898: Achieving Optimal Jitter Performance Using ClockBuilder Pro s Clock Placement Wizard When high-frequency clock signals are in close proximity to each other, there is a high likelihood of crosstalk impacting the jitter performance of each output. Refer to AN862 at https:// www.silabs.com/support%20documents/technicaldocs/ AN862.pdf to learn how to manually order and place output clock pins on the Si538x/4x clocks to achieve the best possible jitter and crosstalk performance. This application note provides an overview of ClockBuilder Pro s Clock Placement Wizard and how to use it to achieve the best possible jitter and crosstalk performance for your frequency plan and device configuration. The Clock Builder Pro software includes various design tips and utilities to quickly configure high-performance clocks. One of the embedded utilities is the Clock Placement Wizard, which is designed to algorithmically optimize the physical pin ordering of the Si534x/8x devices output clocks to enable the best jitter performance and lowest cross talk. KEY POINTS Use the Clock Placement Wizard in ClockBuilder Pro Use differential output formats wherever possible Avoid placing clocks beside each other if they are within the integration bandwidth (e.g., 12 khz to 20 MHz) Consider reducing the output swings and I/O voltages Contact Silicon Labs if you need more information silabs.com Smart. Connected. Energy-friendly. Rev. 0.1
Design Guidelines for Lowest Jitter and Crosstalk 1. Design Guidelines for Lowest Jitter and Crosstalk Before describing how the Clock Placement Wizard works and how to use it to achieve the lowest jitter and crosstalk for a specific Si538x/4x frequency plan, let s consider the following output clock pin configuration guidelines. 1.1 Use Differential Formats Whenever Possible For best performance, differential output formats, such as LVDS, LVPECL, CML or HCSL, are strongly recommended. While the clock placement wizard will not force the user to select differential formats, differential outputs are recommended since these lower swing signaling formats are inherently balanced and, therefore, minimize common-mode noise generation. Common-mode noise is often a key contributor to degraded jitter performance and crosstalk. In contrast, CMOS output buffers are single-ended, swing rail-to rail, and have sub-picosecond edge rates. Because of these factors, CMOS output drivers can create significant single-ended current surges at all of the clock edges and, therefore, can produce significant crosstalk. For these reasons, CMOS outputs should be avoided whenever possible when seeking low-jitter performance. If a CMOS output must be used in the frequency plan, then it is best to place this output as far away from the other clocks as possible, with unused outputs in between. Output formats can easily be chosen or changed in the Clock Builder Pro Configuration Wizard. 1.2 Place Clock Pins Carefully The Clock Placement Wizard will analyze all the clock outputs and arrange them to avoid placing clocks that will cause jitter within the integration bandwidth next to each other. A commonly used integration bandwidth is 12 khz to 20 MHz, which comes from the SONET OC-48 specification. The Clock Placement wizard uses this bandwidth in its algorithm. If two clock outputs are closer to 20 MHz apart in output frequency, this can cause crosstalk issues. For example, if Clock 2 is 155.52 MHz and Clock 3 is 156.25 MHz, then 156.25 MHz 155.52 MHz = 730 khz. Since 730 khz is within the 12 khz to 20 MHz integration bandwidth, the CPW s auto placement algorithm tries to find a way to avoid placing these two clocks beside each other, assuming there are better options. These two output signals will create spurs at 730 khz and multiples of 730 khz that will be in the 12 khz to 20 MHz integration band if placed beside each other. These spurs will contribute to higher jitter. If there are unused clock outputs, it would be best to have an unused clock output between Clock 2 and Clock 3 in this example. Additionally, Clock 2 and Clock 3 should be placed further away with other, higher frequencies between them that are much higher and out of the integration band. Note that the integration bandwidth proximity placement algorithm does not apply to clocks that are simple integer multiples of one another. For example a 20 MHz clock and a 10 MHz clock could be placed beside each other, even though 10 MHz x 2 = 20 MHz and 20 MHz 10 MHz = 10 MHz, both of which reside within the integration band. The reason that simple integer relationships are not an issue is because the edges of one clock do not move with respect to the edges of the other clock. The Clock Placement Wizard takes all of this into account. 1.3 Consider Reducing Output Swings and I/O Voltages If optimal performance is not achieved using the Clock Placement Wizard and the details of AN862 for manual pin placement are included in your design, it is possible that jitter performance can still be improved by using a lower I/O voltage (2.5 or 1.8 V) for CMOS and/or a custom, lower-swing, differential output signal setting. Refer to the Si538x/4x Family Reference Manuals or contact Silicon Labs customer support at https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx. silabs.com Smart. Connected. Energy-friendly. Rev. 0.1 1
2. The Clock Placement Wizard is accessed on the Define Output Frequencies menu step as shown below. Notice that there are currently warning symbols beside some of the outputs for this example frequency plan. These warnings indicate that the output placement is not yet optimized for jitter and crosstalk. Figure 2.1. Defined Output Frequencies, Access to the Clock Placement Wizard Click on the Clock Placement Wizard button, and two options appear: 1. Automatically optimize the output clock placement to run the auto-placement algorithm. 2. Manually optimize the output clock placement, allowing quick rearrangement of the output ordering. silabs.com Smart. Connected. Energy-friendly. Rev. 0.1 2
Figure 2.2. Selecting the Optimization Mode for Clock Placement After choosing the Automatic setting, if the output placement is fully optimized, then there will be a green checkmark icon beside each output as shown below. Click Finish to make the changes take effect. Figure 2.3. Review the Updated Pin Placements After clicking Finish, the outputs have been rearranged, and there is a green checkmark beside each one. This indicates that the algorithm in ClockBuilder Pro has identified the outputs to be in an optimal physical position. silabs.com Smart. Connected. Energy-friendly. Rev. 0.1 3
Figure 2.4. Output Frequencies with Optimized Placement By selecting the Manual Mode for optimization, the output pin placement can be quickly changed by dragging and dropping the outputs into a new arrangement. Figure 2.5. Manual Optimization As shown below, manual optimization can be done by clicking on the output, holding the left mouse button down, and dragging the mouse up or down to reorganize output locations. The output numbering will automatically update. silabs.com Smart. Connected. Energy-friendly. Rev. 0.1 4
Figure 2.6. Moving Output 8 up to the Output 2 Location Figure 2.7. Result from Moving Output 8 to Output 2 Click Next to update the final output arrangement; then click Finish to update the defined outputs back on the main screen as shown below. silabs.com Smart. Connected. Energy-friendly. Rev. 0.1 5
Figure 2.8. Updated Main Screen with Manually-Optimized Output Placement silabs.com Smart. Connected. Energy-friendly. Rev. 0.1 6
Conclusion 3. Conclusion By following the guidelines described in this application note and by using the Clock Placement Wizard, optimal jitter and crosstalk performance can be quickly and easily achieved for the Si534x/8x family of jitter attenuators and clock generators. silabs.com Smart. Connected. Energy-friendly. Rev. 0.1 7
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