A7108 RF Chip Sub 1GHz Transceiver
RF Feature Frequency bands: 315, 433, 470, 868 and 915MHz @ FSK & GFSK Datarate: : 50K, 100K, 150K & 250Kbps (and below by divided) RF TX output power: up to 20dBm (315MHz) 10bps@sensitivity : -114dBm (433MHz) 100bps@sensitivity: -107dBm (433MHz) ADC function: RSSI, battery detector,external voltage and carrier detect Supply voltage 2.0 ~ 3.6V 64bytes separated s physical TX/RX FIFO buffer, FIFO extension function with up to 256 bytes FIFO Optional Manchester Data / FEC / CRC / data whitening (encryption) n) AFC (Auto Frequency Compensation) function, more crystal tolerance Data filtering function (CRC & carrier detect) WOR function No need external capacitor and inductor.
A7108 QFN Top View
RF Interface
3-wire Serial Interface Timing Chart
4-wire Serial Interface Timing Chart
SPI Format (1/3) Bit 7: R/W Bit[15:0]: Data bytes [0]: write data to control register [1]: read data from control register Bit[6:4]: Conmmand bits [000]: read/write control register [01x]: read/write ID code [10x]: read/write FIFO [110]: reset Tx/Rx FIFO pointer [111]: RF chip reset Bit[3:0]: Address of Control register
SPI Format (2/3) Bit[7:4] (A7~A4): state strobe command [0001]: strobe command to set IC operation state Bit[3:0] (A3~A0): State bits
SPI Format (3/3)
Packet Format Preamble ID code Payload (CRC) 1/2/3/4 bytes 2/4/6/8 bytes Data whitening(optional) FEC encoded/decoded(optional) CRC -16 calculation(optional) Max. 256 bytes 2 bytes
Control Register Access Type SCS Read/Write register ADDR reg DataWord ADDR reg DataWord ADDR reg DataWord Read/Write RF FIFO ADDR FIFO DataByte 0 DataByte 1 DataByte 2 DataByte 3 DataByte n Read/Write ID register ADDR ID DataByte 0 DataByte 1 DataByte 2 DataByte 3 DataByte 0 DataByte 1 DataByte 2 DataByte 3 Sleep Mode Idle Mode STBY Mode PLL Mode RX Mode Strobe Command Sleep Mode Strobe Command Idle Mode Strobe Command STBY Mode Strobe Command PLL Mode Strobe Command RX Mode TX Mode FIFO Write Reset FIFO Read Reset Strobe Command TX Mode Strobe Command FIFO Write Reset Strobe Command FIFO Read Reset
Operation modes (I) Mode Register retention Regulator Xtal OSC. VCO L RX TX Strobe Command Register Power down No N/A N/A Deep Sleep(Tristate) No (0001-1100)b N/A Deep Sleep(pullhigh) No (0001-1111)b N/A Sleep Yes (0001-0000)b CER=0,PLL=0 XS=0 Idle Yes ON (0001-0010)b CER=1,PLL=0 XS=0 Standby Yes ON ON (0001-0100)b CER=1, PLLE=0 XS=1 PLL Yes ON ON ON ON (0001-0110)b CER=1, PLLE=1 XS=1 TX Yes ON ON ON ON ON (0001-1000)b TRSR, TRER RX Yes ON ON ON ON ON (0001-1010)b TRSR, TRER SW RST N/A N/A N/A N/A N/A N/A N/A (x111-xxxx)b N/A
Operation modes (II) 3.0V, Power consumption on each mode MODE PLL STANDBY IDLE SLEEP DEEP SLEEP A7108 #A 8.57mA 1.128mA 244uA 0.987uA 0.102uA A7108 #B 8.53mA 1.128mA 252uA 0.951uA 0.087uA
Operation modes (III) IC reset (POR, RST-CMD) FIFO mode Standby 1.2mA PLL PLL AK Auto CAL. STB: reset STB (1ms) Sleep SLEEP 1.5uA Sleep STB (1ms) STB Deep Sleep Auto R-FIFO Standby 1.2mA W-FIFO Deep SLEEP 0.1uA TX / RX Strobe PLL 8.5mA Auto ( RX FIFO Full *) RX settling RX 15.5mA WPLL 8.5mA Auto PDL TDL TX Auto ( TX FIFO Empty * ) SYMBOL EXPLAIN PLL 8.5mA ST (1ms) 1ms State State current Strobe CMD MCU delay time RF auto delay Auto Auto RSSI Measure (ARSSI=1) ST : apply Strobe command AK : enable control register Auto : auto entry
Operation modes (IV) IC reset (POR, RST-CMD) Direct mode Standby 1.2mA PLL PLL AK Auto CAL. STB: reset STB (1ms) Sleep SLEEP 1.5uA Standby 1.2mA Sleep STB (1ms) STB Deep Sleep Auto Deep SLEEP 0.1uA TX / RX Strobe PLL 8.5mA STB RX settling RX 15.5mA WPLL 8.5mA Auto PDL TDL TX STB SYMBOL EXPLAIN PLL 8.5mA ST (1ms) 1ms State State current Strobe CMD MCU delay time RF auto delay MCU decodes Raw RXD Via GIO1/GIO2 MCU generates Raw TXD Via GIO1/GIO2 ST : apply Strobe command AK : enable control register Auto : auto entry
System Block Diagram 20 19 18 17 16 BP_RSSI 1 ADC Battery Detect Regulator Radio Control 15 GIO1 RFI 2 AFC CRC Filtering 14 SDIO AGC RFO 3 LNA 13 SCK GND 4 PA VCO Fractional-N PLL 12 SCS VDD_VCO 5 Gaussian Filter Sigma-Delta Modulator XOSC CLK GEN 11 VDD_D 6 7 8 9 10
Crystal Oscillator 1. External crystal or external clock needs to generate internal clock. 2. Built-in capacitance for the crystal. 3. Crystal (clock) is suggested to be within ± 30 ppm, above 1V peak-to-peak. 1. INXTC = 1 2. XCL[4:0] =22
VCO Block Diagram Ex: 16MHz crystal, 433.001MHz At PFD: 16MHz/(0+1)=433.001MHz*4/x, RRC=0 x=108.25025 IP=108, FP=0.25025*(2^16)=16400, RRC=0
System Clock Block Diagram (I) How to obtain correct setting of A7108 clock domain?
System Clock Block Diagram (II) CSC[2:0] (64) (or 32) IF Freq. (100KHz) (200KHz) (300KHz) (500KHz) IF Filter BW (50KHz) (100KHz) (150KHz) (250KHz) DMOS IFBW[1:0] Fmsck (CSC+1) System Clk SDR[6:0] (SDR+1) (128) (or 64) Data rate clk Output to CKO (RCK/DCK) TRX Baseband How to obtain correct setting of A7108 clock domain? Ex: 433.001MHz, 250Kbps 1. Let DMOS= 0, SDR= 0, CSC= 0, IFBW[1:0]= 3 2. System clock = 128*(SDR+1)*(Datarate)=128*1*0.25=32(MHz) 3. Fmsck= System clock * (CSC+1)= 32MHz
System Clock Block Diagram (III) CGS GRC[4:0] GRS (GRC+1) FCGRF FCGRF x (48 or 32) CGS XS PLL Clk Gen 1 Fmsck XI XE Buffer Xtal Freq 0 XO How to obtain correct setting of A7108 clock domain? Ex: 433.001MHz, 250Kbps 4. Fmsck= 32MHz!= XI(16MHz), so we choose CGS= 1 to enable clock generator 5. 32MHz=16MHz/(GRC+1)*GRS => let GRC=15, GRS=1(x32)
System Clock Block Diagram (IV) How to obtain correct setting of A7108 clock domain? Ex: 433.001MHz, 250Kbps 6. SWT =1 to enable WCK path. 7. Fmsck= 32MHz, and PF8M should be 8MHz when 250Kbps =>MCNT= 1 (/2) and MCNTR= 0 (/2)
System Clock Block Diagram (V) Ex: 433.001MHz, 250Kbps 1. System clock = 128*(SDR+1)*(Datarate)=128*1*0.25=32(MHz) 2. CSC=0 => Fmsck=32MHz 3. CGS=1 to select clock gen. path. 4. 32MHz=16MHz/(GRC+1)*GRS => let GRC=15, GRS=1(x32) 5. 250Kbps => PF8M should be 8MHz 6. 8MHz = 32MHz/MCNT/MCNTR => MCNTR = 0 (/2), MCNT= 1 (/2) Ex: 433.001MHz, 150Kbps 1. System clock = 128*(SDR+1)*(Datarate)=128*1*0.15=19.2(MHz) 2. CSC=1 => Fmsck=38.4MHz 3. CGS=1 to select clock gen. path. 4. 38.4MHz=12.8MHz/(GRC+1)*GRS => let GRC=15, GRS=0(x48) 5. 150Kbps => PF8M should be 6.4MHz 6. 6.4MHz = 38.4MHz/MCNT/MCNTR => MCNTR = 0 (/2), MCNT= 2 (/3)
System Clock Block Diagram (VI) Ex: 433.001MHz, 100Kbps 1. System clock = 128*(SDR+1)*(Datarate)=128*1*0.1=12.8(MHz) 2. CSC=2 => Fmsck=38.4MHz 3. CGS=1 to select clock gen. path. 4. 38.4MHz=12.8MHz/(GRC+1)*GRS => let GRC=15, GRS=0(x48) 5. 100Kbps => PF8M should be 6.4MHz 6. 6.4MHz = 38.4MHz/MCNT/MCNTR => MCNTR = 0 (/2), MCNT= 2 (/3) Ex: 433.001MHz, 100Kbps (another) 1. System clock = 128*(SDR+1)*(Datarate)=128*1*0.1=12.8(MHz) 2. CSC=0 => Fmsck=12.8MHz 3. CGS=0 to select crystal direct path. 4. Neglect GRC, GRS 5. 100Kbps => PF8M should be 6.4MHz 6. 6.4MHz = 12.8MHz/MCNT/MCNTR => MCNTR = 0 (/2), MCNT= 0 (/1)
System Clock Block Diagram (VII) About WRCKS bit: 1. Determine the WOR/TWWS base clock. 4.096KHz by HWCKS bit = 0 (recommend) 2.048KHz by HWCKS bit =1 2. WRCKS bit should be set to: 0: when PF8M clock = 6.4MHz (50/100/150KHz bps) 1: when PF8M clock = 8MHz (250K bps)
System Clock Block Diagram (VIII) How to make sure if the setting is correct for A7108 clock domain? Answer: Obtain the CKO pin: 1. DCK/RCK: the corresponding datarate. (50/100/150/250Kbps) 2. PF8M: 6.4MHz (50/100/150Kbps) or 8MHz (250Kbps) 3. WCK: ~4KHz (or 2KHz) after WOR calibration.
FIFO Transmit Format (I) Preamble ID code Payload (CRC) 1/2/3/4 bytes 2/4/6/8 bytes Data whitening(optional) FEC encoded/decoded(optional) CRC -16 calculation(optional) Max. 256 bytes Packet Format of FIFO mode 2 bytes
FIFO Transmit Format (II) Packet process function: Bit stream process: 1. Error detection: CRC 2. Error correction: FEC - (7,4) Hamming code 3. Encryption: Data whitening - XOR 7-bits Pseudo Random Sequence 4. Linking budget improvement: Manchester coding Packet filtering: MSCRC: 1: When CRC error occurs, A7108 will keep in Rx state when one packet is received. AFC (Auto Frequency Compensation) will also inactive during this packet.
FIFO Transmit Format (III) T (transit time)= 1) [ L preamble + L ID + L payload ] * 1/Datarate 2) [L preamble + L ID + L payload + CRC ] * 1/Datarate 3) [L preamble + L ID + (L payload ) * 7/4 ] * 1/Datarate 4) [L preamble + L ID + (L payload + CRC) * 7/4 ]* 1/Datarate
FIFO Function (I) TRX FIFO W/R pointer set to 0, when: 1. RF reset reset T/RX FIFO pointer 2. Set reset T/RX FIFO pointer command 3. Equal FIFO end point (FEP)
FIFO Function (II) FEP: payload length
FIFO Function (III)
Function: AFC (I) AFC (Auto Freq. Compensation) function: Benefits: 1. Simple way to get frequency drift 2. No need using high accuracy crystal. (5ppm tolerance acceptable)
Function: AFC (II) AFC PRS Description (MC[14:0]) 0 0 (W) RF PLL fractional part, manual compensation 1 0 (R) frequency offset value, no compensation (measurement) 1 1 (R) frequency offset value, w. compensation 0 1 N/A
Function: AFC (III) Frequency drift measurement: 1. Enter Rx mode. 2. Make sure FSYNC = 1 (WTR = 1). 3. AFC = 1, PRS = 0 4. Read MC[14:0] (PLL3) 5. AFC = 0, PRS = 0 6. Leave Rx mode.
Function: ADC (I) Pin BP_RSSI XADS 1 MUX 0 ADC circuit ADC value ADCK- 3.2/4MHz (PF8M/2) 8-bit ADC: ADC converting time= 20 * ADC clock * average time 4-type application 1. Temp. measurement 2. Applied voltage convertion, range: 0~1.2V 3. RSSI measurement (received signal strength indicator) 4. Carrier detection RADC - average times AVSEL[1:0]: 1, 2, 4 & 8 MVSEL[1:0]: 8, 16, 32 & 64
Function: ADC (II) A D C 350 300 250 200 150 100 50 0 RSSI (AGC on) #1 (06h page5, IRTL=0x04 and IRTH=0x07) #2 (06h page5, IRTL=0x04 and IRTH=0x07) #3 (06h page5, IRTL=0x04 and IRTH=0x07) -130-120 -110-100 -90-80 -70-60 -50-40 -30-20 -10 0 10 Input power(dbm) RSSI: ARSSI: Auto RSSI function (ARSSI=1) ERSSM: 0: RSSI value frozen before leaving RX. (packet RSSI) 1: RSSI value frozen when valid frame sync (ID and header check ok) (env. RSSI) AGCE: 1: Auto gain control function extends the usable RSSI value range from 150 (ADC[7:0]) to 270 (ADCO[8:0]).
Function: ADC (III) CD (Carrier Detect) function: Power strength judgement: RTH[7:0]: Threshold value of Carrier Detect (Active in RX mode only). CD (GIOx) =1 when RSSI RTH. CD (GIOx) =0 when RSSI < RTH. Data Filter function: DFCD: The received packet is filtered if the input power level is below RTH[7:0] (compare to ADC[7:0]), and A7108 stays in Rx mode.
Function: BD BD (Battery Detect) function: Supplied voltage detection: BVT[2:0]: Threshold value of Battery Detect 8-levels, 2.0V~2.7V CD (GIOx) =0 when RSSI < RTH. VBD: indicates if supplied voltage is below threshold value. 0: below the threshold value. 1: above the threshold value.
Tools (I) Useful tools: Amiccom offers 4 tools for customers: EK-G1: Evaluation kit for detailed register control and setting. EK-G2: Simply set the operation type,monitor the operation result and obtain the related register configuration. DK: Development kit let user for basic data transferring and Tx/Rx performance evaluating. RCG: Reference code generator let user to generate simply C code for compiling and building whole Tx/Rx system.
Tools (II) EK board 2 RF module Connector, for A06 Board RF module Connector, for A01 Board RF module Connector, for F01/F02 Board 3 Jumper, J10,J15 4 I/O pin Connector, J3 5 Jumper, J8 1 USB connector, J1 6 Jumper, J7 7 Power Supply, J6
Tools (III) EK7108-G1
Tools (IV) EK7108-G2 (1/2)
Tools (V) EK7108-G2 (2/2)
Tools (VI) DK7108 Board
Tools (VII) A7108 Module
Tools (VIII) RCG_7108
Channel Group Calibration (I)
Channel Group Calibration (II)
Channel Group Calibration (III) Integer of N counter
Channel Group Calibration (IV) First 4 bit of PLL II register
Channel Group Calibration (V) b[7:0]: Integer of N counter b[11:8]: First 4 bit of PLL II register
Channel Group Calibration (VI)
Channel Group Calibration (VII) Integer of N counter
Channel Group Calibration (VIII) First 4 bit of PLL II register
Channel Group Calibration (IX) b[7:0]: Integer of N counter b[11:8]: First 4 bit of PLL II register
The end Thank you!!