SOC Single Channel H264 + Audio Encoder module Integration Manual Revision 1.1 06/16/2016 2016 SOC Technologies Inc.
SOC is disclosing this user manual (the "Documentation") to you solely for use in the development of designs to operate with SOC hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of SOC. SOC expressly disclaims any liability arising out of your use of the Documentation. SOC reserves the right, at its sole discretion, to change the Documentation without notice at any time. SOC assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. SOC expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. SOC MAKES NO OTHER WARRANTIES, WHETHER EXPRESSED, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL SOC BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. 2008-2016 SOC, Inc. All rights reserved. SOC, the SOC logo, the Brand Window, and other designated brands included herein are trademarks of SOC, Inc. Revision History Date (MM/DD/YYYY) Version Notes Author 04/20/2016 1.0 Initial Draft 06/16/2016 1.1 Added Author column in this table. Deleted Transport Stream Start Code Added Figure 1 TS stream waveform Blake Acronyms N/A Not Applicable CC Clock Cycle I/O Input/Output GPIO General Purpose Input Output Page 2 of 7
General Description The SOC Single Channel H264 + Audio Encoder module is responsible for encoding raw video/audio frames into a compressed H264+Audio stream or MPEG Transport Stream. In addition to the encoding process a Transport Stream Encoder block is present. The Transport Stream encoder allows for the ability to timestamp the compressed video frame as well as formats the compressed data for transmission over a link. The final output stream is an MPEG Transport Stream(TS). The H264 Encoder core is capable of encoding a single 1080p60 video. In addition to the H264 Encoder, an Audio interface for encoding audio data is provided. The FPGA will communicate with the DSP audio encoder provided by SOC Technologies. The result is a compressed audio stream which will also be packaged into the MPEG Transport Stream. The interface of the module can be grouped into the following interface categories. UART for API Interface Video Input Audio Input Transport Stream Output This document is supposed to be used with the regarding SOC Encoder Modules Pin Assignment Sheet. Page 3 of 7
UART API Interface The API interface is a parallel interface capable of writing and reading registers in the IP Core. Uart_tx 1 O N/A UART serial data output Uart_rx 1 I N/A UART serial data input Table 1 UART API Interface The UART API pins are used to control the module and inquire info/status from the module through access of API registers. The UART configuration is with baud rate 115200, 8-bit data, no parity, and 1 stop bit. For the detail of API registers, please refer to the corresponding API manuals. Uart_tx: UART serial data output from the module. Uart_rx: UART serial data input to the module. Video Input Interface The Video Input interface follows both BT1120 for embedded sync codes 1 as well as SMPTE HDTV HS/VS/DE. The input video format is a 20bit parallel data bus, with 10bits used for Luma and Chroma pixel buses respectively. The input color format is 4:2:2. Video Clock 1 I N/A Clock Video Display Enable 1 I Video Clock Display enable/active pixels Video Vertical Sync 1 I Video Clock Vertical Sync Video Horizontal Sync 1 I Video Clock Horizontal Sync Video Data Luma 10 I Video Clock Luma pixel Data Bus Video Data Chroma 10 I Video Clock Chroma pixel Data Bus Table 2 Video Input Ports Page 4 of 7
Video Clock: The frequency of the video clock must match the specification for the desired video resolution. For example 720p60=74.25, 1080p60=148.5. Video Display Enable(DE): Display Enable. When external sync codes are used all must be present (vs,hs,de). These codes must follow the HDTV modeline standards. Display enable signifies the active pixels in a line/frame. Video Vertical Sync(VS): Vertical Sync. When external sync codes are used all must be present (vs,hs,de). These codes must follow the HDTV modeline standards. Vertical sync signifies the start of a frame/field. Video Horizontal Sync(HS): Horizontal Sync. When external sync codes are used all must be present (vs,hs,de). These codes must follow the HDTV modeline standards. Horizontal sync signifies the start of a line. Video Data Luma: 10 bit Luma pixel data. When sync signals(vs/hs/de) not present, the embedded sync code is carried on Luma bus. Video Data Chroma: 10 bit Chroma pixel data. Audio Input Interface The Audio interface is a single spdif interface. Up to two audio channels Left and Right can be sent to the IP core using the spdif interface. spdif 1 I N/A SPDIF Audio Data Table 3 Audio Interface Transport Stream Output Interface The output interface is a parallel 8bit MPEG Transport Stream. Transport Stream Clock 1 O N/A Transport stream data Page 5 of 7
(ts_clk) Transport Stream Data(ts_data) Transport Stream Data Valid(ts_dv) Transport Stream Buffer Ready (ts_rdy) 8 O ts_clk Transport stream data 1 O ts_clk Data valid 1 I ts_clk Table 4 Stream Ports Transport Stream read/output buffer ready Transport Stream Clock (ts_clk): The clock output for TS stream signals with typical frequency 27MHz. Transport Stream Buffer Ready(ts_rdy): Allows external control to the output rate of the serial transport stream. This allows the user to apply backpressure if their logic is not ready. Note if too much backpressure is applied (ts_rdy is low for too many cycles) the encoder will begin to drop frames. If this signal is not required tie it to logic 1. Transport Stream Data Valid(ts_dv): Stream data valid. Indicates that for the current clock cycle the ts_data is to be considered valid data. The ts_dv goes high at least one cycle after rising edge of ts_rdy and goes low maximum 1 cycle after falling edge of ts_rdy. Transport Stream Data (ts_data): Parallel stream data. The stream data is a MPEG Transport Stream. The ts_data is valid only when ts_dv is high. The TS stream waveform is shown in Figure 1. The numbers in such as number. are cycle Figure 1 TS stream waveform Page 6 of 7
References 1. BT1120 Embedded Sync http://www.itu.int/rec/r-rec-bt.1120/en 2. SOC Encoder Modules Pin Assignment Sheet Page 7 of 7