EE 200: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Chapter 3 Unit Combinational 5 Registers Logic and Design Counters Part Implementation Technology and Logic Design Charles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Unit 5: Registers and Counters Useful MSI blocks made of Flip-Flops Chapter 6: Registers and Counters. Registers with parallel load 2. Shift Registers 3. Counters - Asynchronous (Ripple) - Synchronous Chapter 3 - Part 2
Registers Register a set of binary storage elements Used to perform simple operations on data such as storage, movement, and processing Examples: load, shift, rotate, increment, etc. A processor processes data by performing operations on registers, e.g. ADD A, B where A and B are say 32-bit registers Chapter 3 - Part 3 Examples: - 4-bit Register, with Clear - Selective Parallel Load by gating the clock Q Reset (Cleared) Asynchronously with A 0 pulse on the (normally High) Clear input Loaded with Data at the inputs (D Q) at every clock edge D3-D0 4-bit Data to be loaded What is the problem With this? Encapsulate As a Register Function Block Clock input to FFs We need controlled loading, e.g. only when input data is valid and a Load Signal arrives - (not on every clock pulse!) One Solution: Gate the clock to the flip flops so that clock pulses reach the FFs only when Load = Chapter 3 - Part 4 2
Better Approach Avoid clock gating. Apply Load control at D input Avoid clock gating if you can! Why? It causes clock skew clock pulses may arrive to various registers in the system at different times So such flip flops will change state at different times No good- could lead to erroneous state transitions or data transfers! EN = for Load EN = 0 for no change External Data to be loaded But we now control what Clock pulses do using The EN control on D Clock pulses go all the time Unobstructed To all FFs 2-to- MUX Load now does not gate the clock, I3-I0 But controls what goes into the D input Data to be loaded Load = EN =, D = Ext. input data will be loaded on the next clock edge Load = 0 EN = 0, D = present Q, so no change I 3 on the next clock edge I Register with Parallel Load & no clock skew I 0 I I 2 Chapter 3 - Part 5 Shift Registers Shift Register Serial Loading A Shift Registers moves data laterally ( ) within the register FFs toward the MSB or LSB position In its simplest form, the shift register is a set of D flip-flops having a common clock & connected in a row like this: Serial Serial In A B C DOut DQ DQ DQ DQ Performs Shift Right CP Shift Right Data input, In, is the serial input (the shift right input). Data output, Out, is the serial output (=D). The vector (ABCD) is called the parallel output of the register. Chapter 3 - Part 6 3
Shift Registers: Serial Loading Behavior of the 4- stage serial shift register Initial register state just before the first clock pulse arrives Assume Register was cleared to 0000 initially, e.g. by S-R T: State after the first pulse and before the second Complete the last two rows of the table Feedback In Clock CP Applications: Delay, Serial to Parallel conversion Gates.. DQ A B C Out DQ DQ DQ CP In A B C D: Serial Out 0 0 0 0 0 After 4 T 0 0 0 0 Clock Pulses: T2 0 0 0 T3 0 0 0 2. Serial I/P Starts to T4 0 0 appear T5 Serially at O/P T6 (after 4T delay) T7 0. 4-bit Serial I/P Appears in parallel In register after 4 clock pulses (serial loading of the register) Some Applications of n-stage Shift Register Delay: T Serial input sequence starts to appear at output after n-clock cycles (i.e. is delayed by nt ns) Parallel to Serial and Serial to Parallel conversion: Load Clock TX Arithmetic: n n bit Shift Register Parallel Load 0000 Serial Link or a network Serial In Clock Parallel Read n bit Shift Register Shifting place to the right (feeding in 0s) = dividing by? Shifting place to the left (feeding in 0s) = multiplying by? RX n Chapter 3 - Part 8 4
Shift Registers with Feedback Rotate Right Shift Right Each of A, B is a 4-bit Right-Shift register Clock gating Clock gating is not a good practice Allow only 4 clock pulses to both registers As it leads to Clock skew Regardless of initial Contents in B (flushed out) X X X X After 4 clock pulses: Initial 4-bit value restored in A and serially loaded into B Universal (Multi-purpose) Shift Register with 4 Functions: - Parallel Load - Shift left - Shift Right - No Change 4-to- MUX MSB Add other Functions? e.g. increment, decrement Mode Select LSB Info Inputs Select Inputs 4-to- MUX Y Parallel Data I/P (Down) (Up) LSB Right = LSB Left = MSB Shift Right (Down) LSB Shift Left (Up) 4-to- MUX (Right) (Left)) LSB Chapter 3 - Part 0 5
Serial (bit-by-bit) adder. Using shift registers, Full Adder, and FF X X+Y Sum gets stored bit by bit in Reg. A, replacing augend Initially: A has X, B has Y A new number Z Sneaking in! Initially Y Z Ai Bi Ci -bit Si C i+ Compare with the Parallel adder in Unit 3 New Old Initial C0 =0 Ripple adder & CLA adder were parallel adders using FA for each bit Clock gating To control the FF clocking Accumulates in reg. A the sum of the number initially in A and a set of numbers, entered sequentially into reg. B Chapter 3 - Part Serial Adder (bit-by-bit addition) 2. Using shift regs. and a sequential circuit External O/P = sum 2 External I/Ps CL CL JK FF Q State = Carry Initial Ci =0 Sequential Circuit Chapter 3 - Part 2 6
Serial Adder (bit-by-bit addition) Using shift regs. and a sequential circuit 3 K-maps CL on previous slide Carry Out Sum Carry IN JK Excitation Chapter 3 - Part 3 Counters A counter is a register that has its parallel outputs go through a specific count sequence as clock pulses arrive Counting sequences can be binary, BCD, etc. Counting can be up, down A modulo-n counter has n different counting states, e.g. it goes through counts 0,,2,, (n-),0,, e.g. a modulo-0 up counter may count: 0,,..,9,0,,.. Modulo n counter divides the clock frequency by n (show waveforms) Some Applications of counters: Counting events Timers Frequency division Repeated counting cycle # of clock pulses sent =? # of pulses at MSB (A) =? This is a modulo-? Up/Down? Counter ABC (LSB) 000 00 00 0 00 0 Successive Clock Pulses 000 Chapter 3 - Part 4 00 7
Implementing Counters Two Basic Approaches:. Async (Ripple) & 2. Sync.. Asynchronous (Ripple) Counters The external clock is connected only to the clock input of the LSB bit flip-flop (first counter stage) Then the output of a stage provides the clock I/P to the next stage i.e. circuit is not synchronous - (since no common clock to all stages) Advantage: - Simple circuit Disadvantages: - Output changes are delayed further for each stage toward the LSB (Ripple Effect) - This ripple propagation delay limits the maximum clock frequency that can be used (same factor that limited speed of the ripple adder) Chapter 3 - Part 5 Ripple (asynchronous) Counters Modulo-6 binary counter (n = 4) using D FFs fc Q In-stage Toggling link Inter-stage Clocking links Every Stage is wired to always Toggle with clock & we connect the suitable clock signal to it! Up Down Down Counter 6 clk cycles Toggle at - ive edge on Q0 Connect Q to next C of a +ive Edge FF Toggle at + ive edge on Q0 Connect Q to next C of a +ive Edge FF Repeat Cycle fc/6 fc/8 How to make an Up/Down ripple counter by adding MUXs? fc/4 fc/2 fc = Clock Frequency Frequency Division Properties 6 8
With T FFs- Toggling obtained with T = (no need to externally connect Q to D for each FF) Q Binary Up Counter 0000 (6 Counts) T FF Advantage: No need for an external Q to D connection for each FF to toggle But for Up counting, Clock is taken from Previous Q not Q - Why? Chapter 3 - Part 7 BCD UP (Decade) Ripple Counter Counts 0,, 8, 9, 0 (modulo 0) 4-bits 4 FFs Only 0 used states 6 unused states Identical to 4-bit binary counter up to here 6 unused states Chapter 3 - Part 8 9
** BCD (Decade) UP Ripple Counter with JK FF edge triggered FFs at Q, Q8= Q2 to 0* * at Q:** - (Q4 Q2)=: Toggle - Else: reset to 0 ** Next pulse at end count 0 JK Characteristic Toggles on at Q2 (As usual) Toggles on at Q if Q8 = 0, otherwise Reset Toggles Always 9 Chapter 3 - Part 9 Cascading Ripple Counters 3-Decade Ripple Up Counter (000-999) 00s 0s s Starting with stages Cleared to all 0s 0 On000th clock pulse 0 On 00th clock pulse 0 On 0 th clock pulse (clock) Divide-by-000 Counter Clock Rippling at 2 levels: - Within each decade stage - and also between the stages Each stage is a BCD up Decade Counter (last slide) 0
2. Synchronous Counters The same System clock is connected directly to the clock inputs of ALL flip-flop stages( truly synchronous) No fiddling with clock- instead, we control operation of individual FFs through data or control inputs e.g. D, JK, T Any counter can be systematically designed as a sequential cct see Unit 4 - A combinational logic circuit is used to implement the desired state sequencing through inputs to the Ds of the flip-flop stages But simpler ad hoc approaches can be used for regular counting patterns e.g. binary up or down Chapter 3 - Part 2 Synchronous Binary Counter- Up Q Q2 Toggles at the next Clock pulse if Q0 Q= Q Toggles at the next Clock pulse if Q0 = =Count 0= Stop Counting (all JKs = 00 (No Change) Q Always Toggles Clock is Common, always reaching all stages Terminal Count (=) To Enable of Next Block Q0 Toggles at every Clock pulse
Synchronous Binary Counter- Down =Count Q Clock is Common To all stages Terminal Count (=0000) To Enable of Next Block Q0 Toggles at every Clock pulse Down 0 Synchronous Binary Counter- Up/Down With T Flip Flop Up 0 Always toggles with every clock pulse (for up or down) Chapter 3 - Part 24 2
For a binary counter: Irregular counting pattern here BCD UP Counter: 8 9 0 with T FFs Additional O/P with pulse of clock period duration every counting cycle (divide by 0) A more systematic approach to Design, compared to slide 9 (Async) Toggles when Q= & Q8 = 0 Toggles Always From T K-maps (use Xs) Chapter 3 - Part 25 Binary UP Counter I with Parallel Load (Functional Block) Count Enable () Synchronous Load Enable () S R A Select between Load/Count Conditions LSB (async) Note: JK FF is more cumbersome than D For loading data! External Data to be loaded in Count cond. for the FF Direct Clear (asynchronous) Active Low ( for normal operation) at terminal count () to enable Next 4-bit stage (for cascading) Chapter 3 - Part 26 3
Designing Larger Counters by cascading smaller ones Using the Cout (Terminal Count) to EN of next stage Given two 2-bit (modulo-4) counter, how to design a 4-bit (modulo-6) counter? MS Part LS Part A B C D (LSB) Cout= Cout= Enabled Always (LSB) LS Part LSB MS Part D C B A Enabled to count only once per counting cycle of the LS part MSB To next Stages LS Part generates a single Cout pulse (lasting for clk Cycle only) every time it finishes its counting cycle Cout= Cout= MS Part is enabled to increment only once when it receives this pulse at its EN I/P Example: Design a 6-bit (0-255) binary counter using two of the 4-bit (0-5) universal binary counters on the previous slide Chapter 3 - Part 27 Using this count/load/clr functional block to implement a modulo-n Counter End Count Desired Two Approaches for a BCD (0 to 9) Counter 0 0 (End Count +) 0 0 Not Recommended Loading occurs at next clock Up Counter Start Count Desired or any other Data In for Load starting # < Ending # (synchronous) 9 exists for a full clock cycle and then gets 0000 loaded at the next clock pulse 0000 0 000 000 2 00 3 000 4 00 5 00 6 0 7 000 8 00 9 (Direct- Async) Forces Start Count (0) Next Clock Pulse Up Counter No loading momentarily 00 9 00 0 0000 CLR 0 Asynchronous (direct) Clear 0 is immediately cleared to 0 Through the direct clear. May cause a small brief glitch (spike) at A Chapter 3 - Part 28 4
Modulo 6 Counter with Arbitrary Counting Sequence: Investigate Effect of Unused States on performance Unused State 0 X X X Unused State X X X ABC Two Unused states: Determine transitions from circuit or eqns and ensure safe return to normal counting seq. Modulo? At O/P A, Divide by? Count Sequence? Number of FFs Needed? Used states? Unused states? Three 3-variable K-maps for CL Optimization, with Xs Chapter 3 - Part 29 Generating a sequence of non-overlapping timing signals:. Ring counter (Shift-Right with Rotate - D-type FFs) T0 2 3 0 0 0 Initially loaded by direct S/R 0 0 0 Pulse 0 0 0 Pulse 2 4 different 0 0 0 states 0 0 0 0 0 0 Q 0 0 0 0 D input 0 T T = clock period n intervals Need n FFs 4 non-overlapping Timing signals 000 Inserted directly with Set/Reset Shift right register with 4 D-type FFs (i.e. Q to next RHS D), + Rotate Feedback: Q 3 D 0 0 Initially loaded through directly Set-Rest of the D FFs Chapter 3 - Part 30 5
Generating a sequence of timing signals: 2. Counter-Decoder Implementation Count Sequence 0 0 0 4 non-overlapping Timing signals 0 Chapter 3 - Part 3 Johnson Counter: 8 non-overlapping signals from 4-bit shift register with rotate - but E instead of E! n intervals Need only n/2 FFs - More efficient cct! 8 non-overlapping timing signals are produced by the 8 AND gates shown In the table opposite 8 additional 2-input ANDs 8 non-overlapping Timing signals 8 different states not 4 as on normal ring counter! Chapter 3 - Part 32 6