樹德科技大學資訊工程系 hapter 9: Shift Registers Shi-Huang hen Fall 2010 1 Outline Basic Shift Register Functions Serial In/Serial Out Shift Registers Serial In/Parallel Out Shift Registers Parallel In/Serial Out Shift Registers Parallel In/Parallel Out Shift Registers Bi-directional Shift Registers Shift Register ounters Shift Register Applications 2 1
Basic Shift Register Functions Data Storage Data Movement D flip-flops are use to store and move data The flip-flop as a storage element 3 Basic Shift Register Functions Basic data movement in shift registers. (Four bits are used for illustration. The bits move in the direction of the arrows.) Data in Data in Data out Data out Data in Data out Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out Data in Data in Data out Data out Serial in/parallel out Parallel in/parallel out Rotate right Rotate left 4 2
Serial In/Serial Out Shift Registers Shift registers are available in I form or can be constructed from discrete flip-flops as is shown here with a five-bit serial-in serial-out register. Each clock pulse will move an input bit to the next flip-flop. For example, a 1 is shown as it moves across. Serial data input D D D D FF0 FF1 FF2 FF3 FF4 Q 0 Q 1 Q 2 D 3 Q 3 Q 4 data Serial 0 1 2 4 output 1 1 1 1 1 1 LK 5 Serial In/Serial Out Shift Registers Four bits (1010) being entered serially into the register (1). 6 3
Serial In/Serial Out Shift Registers Four bits (1010) being entered serially into the register (2). 7 Serial In/Serial Out Shift Registers Four bits (1010) being entered serially into the register (3). 8 4
Serial In/Serial Out Shift Registers Four bits (1010) being serially shifted out of the register and replaced by all zeros (1) 9 Serial In/Serial Out Shift Registers Four bits (1010) being serially shifted out of the register and replaced by all zeros (2) 10 5
Serial In/Serial Out Shift Registers Four bits (1010) being serially shifted out of the register and replaced by all zeros (3) 11 Serial In/Serial Out Shift Registers Logic symbol for an 8-bit serial in/serial out shift register. 12 6
Serial In/Parallel Out Shift Registers An application of shift registers is conversion of serial data to parallel form. For example, assume the binary number 1011 is loaded sequentially, one bit at each clock pulse. After 4 clock pulses, the data is available at the parallel output. Serial data input FF0 FF1 FF2 D 0 Q 0 D 1 Q 1 D 2 Q 2 D 3 Q 3 FF3 X 0 1 0 1 10 1 0 1 LK 13 Serial In/Parallel Out Shift Registers The register contains 0110 after four clock pulses. 14 7
Serial In/Parallel Out Shift Registers The 74H164 8-bit serial in/parallel out shift register (9) LR (8) LK (1) Serial A (2) inputs B R R R R R R R R S S S S S S S S (3) (4) (5) (6) (10) (11) (12) (13) Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 15 Parallel In/ Serial Out Shift Register Shift registers can be used to convert parallel data to serial form. A logic diagram for this type of register is shown: SHIFT/LOAD D 0 D 1 D 2 D 3 G 1 G 5 G 2 G 6 G 3 G 7 G 4 D Serial D D D Q 0 Q 1 Q 2 Q 3 data out LK FF0 FF1 FF2 FF3 16 8
Parallel In/ Serial Out Shift Register 17 Parallel In/ Serial Out Shift Register The 74H165 8-bit parallel load shift register. 18 9
Parallel In/ Parallel Out Shift Register 19 Parallel In/ Parallel Out Shift Register The 74H195 4-bit parallel access shift register. 20 10
Bidirectional Shift Registers Data can be shifted left Data can be shifted right A parallel load maybe possible 74H194 is an bidirectional universal shift register 21 Bidirectional Shift Registers Four-bit bidirectional shift register (1) 22 11
Bidirectional Shift Registers Four-bit bidirectional shift register (2) 23 Bidirectional Shift Registers The 74H194 4-bit bidirectional universal shift register. 24 12
Bidirectional Shift Registers Sample timing diagram for a 74H194 shift register. LK Mode control inputs S 0 S 1 Serial data inputs LR SR SER SL SER Parallel data inputs D 0 D 1 D 2 D 3 Q 0 Parallel outputs Q 1 Q 2 Q 3 lear Load Shift right Shift left Inhibit lear 25 Shift Register ounter Shift registers can form useful counters by recirculating a pattern of 0 s and 1 s. Two important shift register counters are the Johnson counter and the ring counter. The Johnson counter can be made with a series of D flip-flops FF0 FF1 FF2 FF3 D 0 Q 0 D 1 Q 1 D 2 Q 2 D 3 Q 3 Q 3 Q 3 LK or with a series of J-K flip flops. Here Q 3 and Q 3 are fed back to the J and K inputs with a twist. LK J 0 Q 0 J 1 Q 1 J 2 Q 2 J 3 FF0 FF1 FF2 FF3 Q3 Q 3 Q3 K 0 Q 0 K 1 Q 1 K 2 Q 2 K 3 Q 3 26 13
Johnson ounter The Johnson counter is useful when you need a sequence that changes by only one bit at a time but it has a limited number of states (2n, where n = number of stages). The first five counts for a 4-bit Johnson counter that is initially cleared are: LK Q 0 Q 1 Q 2 Q 3 What are the remaining 3 states? 0 1 2 3 4 5 6 7 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 27 Johnson ounter 28 14
Johnson ounter Four-bit Johnson counter. 29 Johnson ounter 5-bit Johnson counter 30 15
Ring ounter The ring counter can also be implemented with either D flip-flops or J-K flip-flops. Here is a 4-bit ring counter constructed from a series of D flip-flops. Notice the feedback. LK FF0 FF1 FF2 FF3 Q3 D 0 Q 0 D 1 Q 1 D 2 Q 2 D 3 Q 3 Like the Johnson counter, it can also be implemented with J-K flip flops. J 0 Q 0 J 1 Q 1 J 2 Q 2 J 3 FF0 FF1 FF2 FF3 Q3 K 0 Q 0 K 1 Q 1 K 2 Q 2 K 3 Q 3 Q 3 Q3 LK 31 Ring ounter A 10-bit ring counter. 32 16
Ring ounter A common pattern for a ring counter is to load it with a single 1 or a single 0. The waveforms shown here are for an 8-bit ring counter with a single 1. LK 1 2 3 4 5 6 7 8 9 10 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 33 Ring ounter 34 17
Shift Register Application Time Delay Serial-to-Parallel Data onverter Universal Asynchronous Receiver Transmitter (UART) Keyboard Encoder 35 Time Delay Shift registers can be used to delay a digital signal by a predetermined amount. An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through the register? The delay for each clock is 1/40 MHz = 25 ns The total delay is 8 x 25 ns = 200 ns Data in LK Data in 25 ns A B LK 40 MHz SRG 8 Q 7 Q 7 Data out Data out t d = 200 ns 36 18
Serial-to-Parallel Data onverter Simplified logic diagram of a serial-to-parallel converter. 37 Universal Asynchronous Receiver Transmitter 38 19
Universal Asynchronous Receiver Transmitter A UART (Universal Asynchronous Receiver Transmitter) is a serial-toparallel converter and a parallel to serial converter. Data bus Buffers UARTs are commonly used in small systems where one device must communicate with another. Parallel data is converted to asynchronous serial form and transmitted. The serial data format is: LK Transmitter data register Transmitter shift register Serial data out LK Receiver data register Receiver shift register Serial data in Start Bit (0) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D Stop Bits (1) 0 t 39 Keyboard Encoder The keyboard encoder is an example of where a ring counter is used in a small system to encode a key press. LK (5 khz) Power on LOAD SH/LD +V D 0 D 1 D 2 D 3 J K SRG 4 74H195 Q 0 Q 1 Q 2 Q 3 Ring counter D 4 D 5 D 6 D 7 J K SRG 4 74H195 Q 4 Q 5 Q 6 Q 7 +V lock inhibit 1 2 3 4 5 6 7 8 ROW encoder 74H147 1 2 4 1 2 3 4 5 6 7 8 OLUMN encoder 74H147 1 2 4 Switch closure Q Q D 0 D 1 D 2 D 3 D 4 D 5 Key code register 74H174 Q One-shots Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 To ROM 40 20